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1. 发明专利

JP2004025513A Document folder with index 审中-公开
公开(公告)号：JP2004025513A
公开(公告)日：2004-01-29
申请号：JP2002182392
申请日：2002-06-24
申请人： Hideo Mochizuki , 望月秀雄
发明人： MOCHIZUKI HIDEO
IPC分类号： B42F7/00
摘要： PROBLEM TO BE SOLVED: To provide a document folder with an index which enables arbitrary change of the position of the index and which has a self-sustaining property and is safe for the fingers.
SOLUTION: A rectangular sheet comprising a front cover S1, a shelfback S2 and an upper flap S3 is bent in thesame direction to form fold lines 1 and 2. The sheet is bent in the opposite direction in a narrow width from the fold line 2 within the face of the upper flap so as to form a fold line 4 and is further bent in the same direction in the same narrow width. In a strip-shaped part occupied by the three fold lines 2, 4 and 5 thus formed, cuts 8 intersecting each of these lines perpendicularly are provided at positions where the rectangular sheet is divided in the direction of the short length thereof in desired numbers. The folded portion of an arbitrary part held between the end part of the sheet and the cut or between the adjacent cuts is inverted so as to be made the index in the lateral direction. It is also allowable that a lateral flap is jutted out in the lateral direction from the shelfback and that fold lines similar to ones of the upper flap are provided within the face of that flap and an index in the longitudinal direction intersecting the lateral index perpendicularly is provided in the strip-shaped part formed.
COPYRIGHT: (C)2004,JPO

2. 发明授权

US08406065B2 Memory interface circuit and semiconductor device 失效
公开(公告)号：US08406065B2
公开(公告)日：2013-03-26
申请号：US13617421
申请日：2012-09-14
申请人： Hideo Mochizuki
发明人： Hideo Mochizuki
IPC分类号： G11C7/10
CPC分类号： G11C7/10 , G06F13/1673 , G06F13/1689
摘要： There is a need to provide a small-sized memory interface circuit capable of adjusting timing between a strobe signal and a data signal without interrupting a normal memory access.An expected value acquisition latch latches write data in synchronization with a clock signal. A WDLL outputs a write strobe signal WDQS. An RDLL outputs a delayed write strobe signal WDQS_d. A read data latch latches looped-back write data in synchronization with the delayed write strobe signal WDQS_d. A comparator compares the read data latch with an output from the expected value acquisition latch. A register portion stores a delay value to be placed in the RDLL. A register control portion updates a delay value in the register portion in accordance with a comparison result. A delay selection portion places a delay value read from the register portion in the RDLL.

3. 发明申请

US20120218844A1 MEMORY CONTROLLER, SYSTEM INCLUDING THE CONTROLLER, AND MEMORY DELAY AMOUNT CONTROL METHOD 失效
标题翻译：存储器控制器，包括控制器的系统和存储器延迟量控制方法
公开(公告)号：US20120218844A1
公开(公告)日：2012-08-30
申请号：US13462689
申请日：2012-05-02
申请人： Hideo Mochizuki , Kazuaki Masuda
发明人： Hideo Mochizuki , Kazuaki Masuda
IPC分类号： G11C7/00
CPC分类号： G11C5/14 , G06F13/1689 , Y02D10/14
摘要： A memory controller coupled to a DRAM includes a delay control section including a delay holding section, and coupled to the DRAM to output a delay set value to the DRAM and a delay adjustment section coupled to the DRAM to receive data from the DRAM, and to arrange a delay amount of the received data based on the delay set value. The delay set value is stored in both the delay holding section of the memory controller and the DRAM.
摘要翻译：耦合到DRAM的存储器控制器包括延迟控制部分，该延迟控制部分包括延迟保持部分，并且耦合到DRAM以向DRAM提供延迟设置值，以及延迟调整部分，其耦合到DRAM以从DRAM接收数据，以及基于延迟设定值排列接收到的数据的延迟量。延迟设定值存储在存储器控制器的延迟保持部分和DRAM中。

4. 发明授权

US07339389B2 Semiconductor device incorporating characteristic evaluating circuit operated by high frequency clock signal 有权
标题翻译：具有由高频时钟信号操作的特征评估电路的半导体装置
公开(公告)号：US07339389B2
公开(公告)日：2008-03-04
申请号：US11086742
申请日：2005-03-23
申请人： Hideo Mochizuki
发明人： Hideo Mochizuki
IPC分类号： G01R31/02
CPC分类号： G01R31/2879 , G01R31/31727
摘要： In a semiconductor device, a main circuit is operated by a first clock signal, and at least one characteristic evaluating circuit is operated by a second clock signal whose frequency is higher than a frequency of the first clock signal. Also, at least one deterioration detecting circuit is connected to the characteristic evaluating circuit and Is adapted to detect deterioration of the characteristic evaluating circuit.
摘要翻译：在半导体器件中，主电路由第一时钟信号操作，并且至少一个特性评估电路由频率高于第一时钟信号的频率的第二时钟信号操作。此外，至少一个劣化检测电路连接到特性评估电路，并且适于检测特性评估电路的劣化。

5. 发明申请

US20050212550A1 Semiconductor device incorporating characteristic evaluating circuit operated by high frequency clock signal 有权
标题翻译：具有由高频时钟信号操作的特征评估电路的半导体装置
公开(公告)号：US20050212550A1
公开(公告)日：2005-09-29
申请号：US11086742
申请日：2005-03-23
申请人： Hideo Mochizuki
发明人： Hideo Mochizuki
IPC分类号： G01R31/28 , G01R31/317 , H01L21/822 , H01L27/04 , H03K19/003
CPC分类号： G01R31/2879 , G01R31/31727
摘要： In a semiconductor device, a main circuit is operated by a first clock signal, and at least one characteristic evaluating circuit is operated by a second clock signal whose frequency is higher than a frequency of the first clock signal. Also, at least one deterioration detecting circuit is connected to the characteristic evaluating circuit and Is adapted to detect deterioration of the characteristic evaluating circuit.
摘要翻译：在半导体器件中，主电路由第一时钟信号操作，并且至少一个特性评估电路由频率高于第一时钟信号的频率的第二时钟信号操作。此外，至少一个劣化检测电路连接到特性评估电路，并且适于检测特性评估电路的劣化。

6. 发明授权

US5763205A Producing pure chondroitinase ABC from Proteus vulgaris ATCC 6896 失效
标题翻译：从普通变形菌ATCC 6896生产纯软骨素酶ABC
公开(公告)号：US5763205A
公开(公告)日：1998-06-09
申请号：US443675
申请日：1995-05-18
申请人： Nobukazu Hashimoto , Hideo Mochizuki , Akio Hamai
发明人： Nobukazu Hashimoto , Hideo Mochizuki , Akio Hamai
IPC分类号： A61K38/43 , A61K38/00 , C12N9/16 , C12N9/20 , C12N9/88 , C12N9/44
CPC分类号： C12N9/88 , A61K38/00 , G03C2001/0471 , Y10S435/873
摘要： A crystallizable, purified chondroitinase ABC having a molecular weight of about 100,000 dalton by the measurement of the SDS-polyacrylamide gel electrophoresis (SDS-PAGE) and the measurement by the gel permeation chromatography method, having alanine as the N-terminal amino acid and proline as the C-terminal amino acid is disclosed. A process for the purification of the crystallizable purified chondroitinase ABC comprising removing nucleic acid from an surfactant solution extract obtained from cells of chondroitinase ABC-producing microorganisms and chromatographically treating by concentration gradient elution using a weak cation exchange resin or a strong cation exchange resin is disclosed. A composition comprising a chondroitinase and serum albumin, gelatin, or a nonionic surfactant is disclosed. The enzyme is isolated from Proteus vulgaris ATCC 6896.
摘要翻译：通过SDS-聚丙烯酰胺凝胶电泳（SDS-PAGE）的测量和通过凝胶渗透色谱法测定的具有约100,000道尔顿分子量的可结晶纯化的软骨素酶ABC，其具有丙氨酸作为N-末端氨基酸和脯氨酸因为公开了C-末端氨基酸。公开了一种纯化可结晶纯化软骨素酶ABC的方法，包括从由软骨素酶ABC产生的微生物的细胞获得的表面活性剂溶液提取物中除去核酸，并使用弱阳离子交换树脂或强阳离子交换树脂进行色谱法处理。。公开了包含软骨素酶和血清白蛋白，明胶或非离子表面活性剂的组合物。该酶从普通变形杆菌ATCC 6896中分离。

7. 发明授权

US08359490B2 Memory controller, system including the controller, and memory delay amount control method 失效
标题翻译：存储器控制器，包括控制器的系统和存储器延迟量控制方法
公开(公告)号：US08359490B2
公开(公告)日：2013-01-22
申请号：US13462689
申请日：2012-05-02
申请人： Hideo Mochizuki , Kazuaki Masuda
发明人： Hideo Mochizuki , Kazuaki Masuda
IPC分类号： G06F1/12
CPC分类号： G11C5/14 , G06F13/1689 , Y02D10/14
摘要： A memory controller coupled to a DRAM includes a delay control section including a delay holding section, and coupled to the DRAM to output a delay set value to the DRAM and a delay adjustment section coupled to the DRAM to receive data from the DRAM, and to arrange a delay amount of the received data based on the delay set value. The delay set value is stored in both the delay holding section of the memory controller and the DRAM.
摘要翻译：耦合到DRAM的存储器控制器包括延迟控制部分，该延迟控制部分包括延迟保持部分，并且耦合到DRAM以向DRAM提供延迟设置值，以及延迟调整部分，其耦合到DRAM以从DRAM接收数据，以及基于延迟设定值排列接收到的数据的延迟量。延迟设定值存储在存储器控制器的延迟保持部分和DRAM中。

8. 发明申请

US20120113729A1 MEMORY INTERFACE CIRCUIT AND SEMICONDUCTOR DEVICE 失效
标题翻译：存储器接口电路和半导体器件
公开(公告)号：US20120113729A1
公开(公告)日：2012-05-10
申请号：US13272856
申请日：2011-10-13
申请人： Hideo MOCHIZUKI
发明人： Hideo MOCHIZUKI
IPC分类号： G11C7/10
CPC分类号： G11C7/10 , G06F13/1673 , G06F13/1689
摘要： There is a need to provide a small-sized memory interface circuit capable of adjusting timing between a strobe signal and a data signal without interrupting a normal memory access.An expected value acquisition latch latches write data in synchronization with a clock signal. A WDLL outputs a write strobe signal WDQS. An RDLL outputs a delayed write strobe signal WDQS_d. A read data latch latches looped-back write data in synchronization with the delayed write strobe signal WDQS_d. A comparator compares the read data latch with an output from the expected value acquisition latch. A register portion stores a delay value to be placed in the RDLL. A register control portion updates a delay value in the register portion in accordance with a comparison result. A delay selection portion places a delay value read from the register portion in the RDLL.
摘要翻译：需要提供能够调整选通信号和数据信号之间的定时的小型存储器接口电路，而不中断正常的存储器访问。期望值采集锁存器与时钟信号同步地锁存写入数据。 WDLL输出写选通信号WDQS。 RDLL输出延迟的写选通信号WDQS_d。读取数据锁存器与延迟写入选通信号WDQS_d同步地锁存环回写入数据。比较器将读取的数据锁存器与期望值采集锁存器的输出进行比较。寄存器部分存储要放置在RDLL中的延迟值。寄存器控制部分根据比较结果更新寄存器部分中的延迟值。延迟选择部分将从寄存器部分读取的延迟值放在RDLL中。

9. 发明申请

US20090292940A1 Memory controller, system including the controller, and memory delay amount control method 失效
标题翻译：存储器控制器，包括控制器的系统和存储器延迟量控制方法
公开(公告)号：US20090292940A1
公开(公告)日：2009-11-26
申请号：US12453553
申请日：2009-05-14
申请人： Hideo Mochizuki , Kazuaki Masuda
发明人： Hideo Mochizuki , Kazuaki Masuda
IPC分类号： G06F12/00 , G06F1/08
CPC分类号： G11C5/14 , G06F13/1689 , Y02D10/14
摘要： A memory controller transmits and receives data to and from a memory. The memory controller includes a delay control section deciding a set value indicative of a determined delay amount in response to a result of a comparison between a test data transmitted to the memory and test data received from the memory, and transmitting the decided set value to the memory, a taking-in section receiving the set value stored in the memory, and a delay adjustment section receiving data from the memory, and arranging a delay amount of the received data in response to the set value received by the taking-in section.
摘要翻译：存储器控制器向存储器发送数据和从存储器接收数据。存储器控制器包括响应于发送到存储器的测试数据与从存储器接收的测试数据之间的比较的结果而确定指示所确定的延迟量的设定值的延迟控制部分，并将所确定的设定值发送到存储器，接收存储在存储器中的设定值的接收部分，以及从存储器接收数据的延迟调整部分，并且响应于由接收部分接收的设定值来布置接收到的数据的延迟量。

10. 发明授权

US08315109B2 Memory interface circuit and semiconductor device 失效
标题翻译：存储器接口电路和半导体器件
公开(公告)号：US08315109B2
公开(公告)日：2012-11-20
申请号：US13272856
申请日：2011-10-13
申请人： Hideo Mochizuki
发明人： Hideo Mochizuki
IPC分类号： G11C7/10
CPC分类号： G11C7/10 , G06F13/1673 , G06F13/1689
摘要： There is a need to provide a small-sized memory interface circuit capable of adjusting timing between a strobe signal and a data signal without interrupting a normal memory access.An expected value acquisition latch latches write data in synchronization with a clock signal. A WDLL outputs a write strobe signal WDQS. An RDLL outputs a delayed write strobe signal WDQS_d. A read data latch latches looped-back write data in synchronization with the delayed write strobe signal WDQS_d. A comparator compares the read data latch with an output from the expected value acquisition latch. A register portion stores a delay value to be placed in the RDLL. A register control portion updates a delay value in the register portion in accordance with a comparison result. A delay selection portion places a delay value read from the register portion in the RDLL.
摘要翻译：需要提供能够调整选通信号和数据信号之间的定时的小型存储器接口电路，而不中断正常的存储器访问。期望值采集锁存器与时钟信号同步地锁存写入数据。 WDLL输出写选通信号WDQS。 RDLL输出延迟的写选通信号WDQS_d。读取数据锁存器与延迟写入选通信号WDQS_d同步地锁存环回写入数据。比较器将读取的数据锁存器与期望值采集锁存器的输出进行比较。寄存器部分存储要放置在RDLL中的延迟值。寄存器控制部分根据比较结果更新寄存器部分中的延迟值。延迟选择部分将从寄存器部分读取的延迟值放在RDLL中。

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