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1. 发明申请

US20110317478A1 Method and Circuit Arrangement for Performing a Write Through Operation, and SRAM Array With Write Through Capability 审中-公开
标题翻译：用于执行写入操作的方法和电路布置，以及具有写入能力的SRAM阵列
公开(公告)号：US20110317478A1
公开(公告)日：2011-12-29
申请号：US13150458
申请日：2011-06-01
申请人： Yuen H. Chan , Michael Kugel , Antonio Pelella , Tobias Werner
发明人： Yuen H. Chan , Michael Kugel , Antonio Pelella , Tobias Werner
IPC分类号： G11C11/34 , G11C11/00
CPC分类号： G11C11/419 , G11C11/41 , G11C29/1201 , G11C29/48
摘要： An improved method for performing a write through operation during a write operation of a SRAM cell (10) of a SRAM array (1) is disclosed. The method comprises suppressing a false write through data propagation at an output node (C, F) of the SRAM array (1) in case of a failure causing transition at a first node (t) or a second node (c) of the SRAM cell (10) by using information about the input data (data, data_b) to be written in the SRAM cell (10) and read data propagation paths to retain the output node (C, F) after a global bit line (gb_t, gb_c) at a precharge level independently from a logical level of the global bit line (gb_t, gb_c), if a corresponding node (c, t) of the SRAM cell (10) is performing the failure causing transition based on input data (data, data_b) to be written in the SRAM cell (10).
摘要翻译：公开了一种用于在SRAM阵列（1）的SRAM单元（10）的写入操作期间执行写入操作的改进方法。该方法包括在SRAM的第一节点（t）或第二节点（c）处的故障导致故障的情况下，通过SRAM阵列（1）的输出节点（C，F）处的数据传播来抑制错误写入通过使用关于要写入SRAM单元（10）的输入数据（数据，data_b）的信息，读取数据传播路径以在全局位线（gb_t，gb_c）之后保持输出节点（C，F）的单元（10）），如果SRAM单元（10）的对应节点（c，t）正在执行基于输入数据的失败导致转换（数据， data_b）写入SRAM单元（10）。

2. 发明授权

US07170799B2 SRAM and dual single ended bit sense for an SRAM 失效
标题翻译：用于SRAM的SRAM和双单端位检测
公开(公告)号：US07170799B2
公开(公告)日：2007-01-30
申请号：US11055416
申请日：2005-02-10
申请人： Yuen H. Chan , Timothy J. Charest , Rajiv V. Joshi , Antonio Pelella
发明人： Yuen H. Chan , Timothy J. Charest , Rajiv V. Joshi , Antonio Pelella
IPC分类号： G11C7/00
CPC分类号： G11C11/417
摘要： A CMOS static random access memory (SRAM) and a bit select for the SRAM. The bit select includes a dual single-ended sense receiving a difference signal on a bit line pair and selectively sensing signals developing on each bit line independently of the other. Single ended outputs from the dual-ended sense are provided to an output driver. The output driver provides a pair of selectively-complementary output signals.
摘要翻译： CMOS静态随机存取存储器（SRAM）和SRAM的位选择。位选择包括双位单端感测，其接收位线对上的差分信号，并且选择性地感测在每个位线上独立于另一位置产生的信号。双端输出的单端输出提供给输出驱动器。输出驱动器提供一对选择性互补的输出信号。

3. 发明申请

US20070058421A1 Global Bit Line Restore Timing Scheme and Circuit 失效
标题翻译：全局位线恢复时序方案和电路
公开(公告)号：US20070058421A1
公开(公告)日：2007-03-15
申请号：US11554072
申请日：2006-10-30
申请人： Yuen Chan , Ryan Freese , Antonio Pelella , Uma Srinivasan , Arthur Tuminaro , Jatinder Wadhwa
发明人： Yuen Chan , Ryan Freese , Antonio Pelella , Uma Srinivasan , Arthur Tuminaro , Jatinder Wadhwa
IPC分类号： G11C11/00
CPC分类号： G11C7/18 , G11C7/12 , G11C11/417
摘要： A domino SRAM array restore pulse generation system launches the work decode line by the same local clock as the restore pulse, thus eliminating any race issues with the word line select. This system allows the global bit select (or column select) to have fast activation by releasing the reset signal (with the earliest arriving array clock, ck1), while guaranteeing almost perfect tracking with the bit decode system. This allows for the widest possible write window; earliest release of the pre-charge in the global column select, and resetting only after the bit decode system is deactivated.
摘要翻译：多米诺SRAM阵列恢复脉冲发生系统通过与恢复脉冲相同的本地时钟启动工作解码线，从而消除了字线选择的任何种族问题。该系统允许全局位选择（或列选择）通过释放复位信号（具有最早到达的阵列时钟ck 1）来快速激活，同时保证使用位解码系统几乎完美的跟踪。这允许最广泛的写入窗口; 全局列中最早发布预充电选择，仅在位解码系统被禁用后进行复位。

4. 发明申请

US20060176732A1 SRAM and dual single ended bit sense for an SRAM 失效
标题翻译：用于SRAM的SRAM和双单端位检测
公开(公告)号：US20060176732A1
公开(公告)日：2006-08-10
申请号：US11055416
申请日：2005-02-10
申请人： Yuen Chan , Timothy Charest , Rajiv Joshi , Antonio Pelella
发明人： Yuen Chan , Timothy Charest , Rajiv Joshi , Antonio Pelella
IPC分类号： G11C11/00
CPC分类号： G11C11/417
摘要： A CMOS static random access memory (SRAM) and a bit select for the SRAM. The bit select includes a dual single-ended sense receiving a difference signal on a bit line pair and selectively sensing signals developing on each bit line independently of the other. Single ended outputs from the dual-ended sense are provided to an output driver. The output driver provides a pair of selectively-complementary output signals.
摘要翻译： CMOS静态随机存取存储器（SRAM）和SRAM的位选择。位选择包括双位单端感测，其接收位线对上的差分信号，并且选择性地感测在每个位线上独立于另一位置产生的信号。双端输出的单端输出提供给输出驱动器。输出驱动器提供一对选择性互补的输出信号。

5. 发明申请

US20060176728A1 LOCAL BIT SELECT CIRCUIT WITH SLOW READ RECOVERY SCHEME 失效
标题翻译：具有慢速读取方案的本地位选择电路
公开(公告)号：US20060176728A1
公开(公告)日：2006-08-10
申请号：US11054148
申请日：2005-02-09
申请人： Antonio Pelella
发明人： Antonio Pelella
IPC分类号： G11C11/00
CPC分类号： G11C11/413 , G11C7/06 , G11C7/08 , G11C11/41 , G11C11/419 , G11C2207/065
摘要： Local bit line pairs in a domino SRAM include an amplifier to amplify the voltage differential across the bit lines during a read operation if a cell in the local group of cells has been identified as a slow to read cell. The amplifier includes a transistor switch that is turned on by a timing pulse during the read operation, but only if the Array Built In Self-Test (ABIST) has detected a slow to read cell in the local group. If there is no slow cell, the amplifier is not activated, and the domino read operation is carried out. The amplifier can be used globally across the SRAM or selectively in certain sub-arrays.
摘要翻译：多米诺SRAM中的本地位线对包括放大器，用于在读取操作期间放大位线上的电压差，如果本地单元组中的单元已被识别为读取单元的缓慢。放大器包括一个晶体管开关，它在读取操作期间由定时脉冲导通，但只有在内置自检阵列（ABIST）检测到本地组中读取的单元格较慢时才会导通。如果没有慢速单元，则放大器未被激活，并且执行多米诺骨牌读取操作。放大器可以跨SRAM全局使用，也可以选择性地在某些子阵列中使用。

6. 发明申请

US20050254285A1 Cache late select circuit 失效
标题翻译：缓存迟选电路
公开(公告)号：US20050254285A1
公开(公告)日：2005-11-17
申请号：US10844296
申请日：2004-05-12
申请人： Yuen Chan , Timothy Charest , Antonio Pelella , John Rawlins
发明人： Yuen Chan , Timothy Charest , Antonio Pelella , John Rawlins
IPC分类号： G11C11/00 , G11C11/417
CPC分类号： G11C11/417 , G11C11/41 , G11C2029/3202
摘要： A late select circuit topology has pseudo-static circuits that provide fast dynamic circuit operation without the use of dynamic clock timing signals. An output from a selected set is enabled by the conjunction of bit line pulse and set select signal.
摘要翻译：迟选择电路拓扑具有伪静态电路，其在不使用动态时钟定时信号的情况下提供快速动态电路操作。来自所选集合的输出由位线脉冲和置位选择信号的结合使能。

7. 发明申请

US20060179375A1 Split L2 latch with glitch free programmable delay 失效
标题翻译：分离L2锁存器，无毛刺可编程延迟
公开(公告)号：US20060179375A1
公开(公告)日：2006-08-10
申请号：US11054311
申请日：2005-02-09
申请人： Yuen Chan , Ryan Freese , Antonio Pelella
发明人： Yuen Chan , Ryan Freese , Antonio Pelella
IPC分类号： G01R31/28
CPC分类号： G01R31/318552
摘要： A programmable delay circuit that delays the C2 clock signal by a variable amount that allows the output from the L1 latch to be captured even when there is a large delta between the L1 latch and its L2 latch. This allows the C2 signal to be adjusted within the system dependent upon the amount of cycle steal is needed. The C2 clock delay is inhibited during scan operation to prevent glitches and the trailing edge of the delayed C2 is controlled to maintain a constant C2 duty cycle.
摘要翻译：一个可编程延迟电路，将C2时钟信号延迟一个可变量，即使在L1锁存器和其L2锁存器之间存在大的增量时，允许来自L1锁存器的输出被捕获。这允许在系统内调整C2信号，这取决于所需的循环窃取量。在扫描操作期间C2时钟延迟被禁止以防止毛刺，并且延迟的C2的后沿被控制以保持恒定的C2占空比。

8. 发明申请

US20060176753A1 Global bit select circuit with dual read and write bit line pairs 失效
标题翻译：具有双读和写位线对的全局位选择电路
公开(公告)号：US20060176753A1
公开(公告)日：2006-08-10
申请号：US11054309
申请日：2005-02-09
申请人： Yuen Chan , Ryan Freese , Antonio Pelella , Arthur Tuminaro
发明人： Yuen Chan , Ryan Freese , Antonio Pelella , Arthur Tuminaro
IPC分类号： G11C8/00
CPC分类号： G11C11/413
摘要： A domino SRAM global bit select circuit provides an interface between dual global read and write bit line pairs to a “local bit select” circuit.
摘要翻译：多米诺SRAM全局位选择电路提供了双局域读和写位线对之间的接口到“本地位选择”电路。

9. 发明申请

US20060176729A1 Local bit select with suppression of fast read before write 失效
标题翻译：本地位选择与写入前禁止快速读取
公开(公告)号：US20060176729A1
公开(公告)日：2006-08-10
申请号：US11054402
申请日：2005-02-09
申请人： Yuen Chan , Ryan Freese , Antonio Pelella , Arthur Tuminaro
发明人： Yuen Chan , Ryan Freese , Antonio Pelella , Arthur Tuminaro
IPC分类号： G11C11/00
CPC分类号： G11C11/413 , G11C7/12 , G11C7/18 , G11C2207/002
摘要： A domino SRAM is provided with active pull-up PFET devices that overwhelm “slow to write but very fast to read” cells and allow the cells to recover from timing mismatch situations. This approach allows the traditional “bit select” clamp to actively control the “local select” through “wired-or” PFET pull-up transistors. Separate read and write global “bit line” pairs allow the read and write performance to be optimized independently
摘要翻译：多米诺SRAM提供有有源上拉PFET器件，它们淹没“读写速度慢但读取速度非常快”，并允许单元从定时不匹配情况中恢复。这种方法允许传统的“位选择”钳位通过“有线或”PFET上拉晶体管主动地控制“局部选择”。单独的读写全局“位线”对可以独立优化读写性能

10. 发明申请

US20050253639A1 Output driver with pulse to static converter 失效
标题翻译：具有脉冲到静态转换器的输出驱动器
公开(公告)号：US20050253639A1
公开(公告)日：2005-11-17
申请号：US10844298
申请日：2004-05-12
申请人： Yuen Chan , Antonio Pelella , Jatinder Wadhwa , Otto Wagner
发明人： Yuen Chan , Antonio Pelella , Jatinder Wadhwa , Otto Wagner
IPC分类号： G11C7/10 , G11C11/34 , G11C11/419 , G11C29/32
CPC分类号： G11C7/1069 , G11C7/1051 , G11C11/41 , G11C11/419 , G11C29/32 , G11C2029/3202
摘要： A pulse to static converter for SRAM in which the converter latch is comprised of two cross-coupled, complementary, FET pairs. The FETs of each pair are coupled drain to drain between a positive voltage source and ground. The output state of SRAM sense amplifier is coupled as an input to the grates of one FET pair and the state established by this input is latched via the cross coupling with the other FET pair.
摘要翻译：用于SRAM的脉冲到静态转换器，其中转换器锁存器由两个交叉耦合的互补FET对组成。每对的FET在正电压源和地之间将漏极耦合到漏极。 SRAM读出放大器的输出状态作为一个FET对的栅极的输入耦合，由该输入建立的状态通过与另一个FET对的交叉耦合而锁存。

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