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1. 发明授权

US07031899B2 System for characterizing simulated circuit logic and behavior 有权
公开(公告)号：US07031899B2
公开(公告)日：2006-04-18
申请号：US09829535
申请日：2001-04-09
申请人： Yu-Chin Hsu , Furshing Tsai , Tayung Liu , Bassam Tabbara , Kunming Ho , George Bakewell , Yirng-An Chen , Scott Sandler
发明人： Yu-Chin Hsu , Furshing Tsai , Tayung Liu , Bassam Tabbara , Kunming Ho , George Bakewell , Yirng-An Chen , Scott Sandler
IPC分类号： G06F3/147 , G06F3/153
CPC分类号： G06F17/5022
摘要： A circuit simulator simulates a circuit described by a circuit logic model as having a set of clocked registers interconnected by un-clocked logic to produce waveform data indicating states of each circuit input signal and of each register output signal as functions of clock signal edge timing. The waveform data and the logic model are then processed to produce a temporal schema model characterizing the circuit's logic and behavior. A display based on the temporal schema model depicts circuit behavior using separate symbols to represent successive circuit input signal states and register output signal states at various times during the simulation. The same display also graphically depicts fan-in or fan-out logical relationships by which circuit input signal states and register output signal states influence register input signal states.

2. 发明授权

US07079997B1 IC behavior analysis system 有权
标题翻译： IC行为分析系统
公开(公告)号：US07079997B1
公开(公告)日：2006-07-18
申请号：US10143347
申请日：2002-05-10
申请人： Yu-Chin Hsu , Furshing Tsai , Yirng-An Chen , Kunming Ho , Tayung Liu , Chieh Changfan , Wells Woei-Tzy Jong
发明人： Yu-Chin Hsu , Furshing Tsai , Yirng-An Chen , Kunming Ho , Tayung Liu , Chieh Changfan , Wells Woei-Tzy Jong
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： A debugger produces a display based on instructions executed by a circuit simulator or verification tool and on waveform data produced by the simulator or verification tool when executing the instructions. The instructions include a set of statements, each corresponding to a separate circuit signal generated by a circuit and each including a function defining a value of the circuit signal as a function of values of other circuit signals. The simulator evaluates the statements at various simulation times to compute signal values at those simulation times. The waveform data indicates signal values the simulator computes when evaluating the statements. The debugger display includes a set of statement event symbols, each corresponding to a separate evaluation of a statement and each positioned in the display to indicate a simulation time at which the simulator evaluated the statement. Each statement event symbol references the signal whose value is computed by the corresponding statement evaluation and indicates a value of that signal computed when the statement was evaluated. Each statement event symbol also references the other signals having values of which the statement indicates the computed signal value is a function and indicates those other signals values as of the simulation time at which the statement was evaluated.
摘要翻译：调试器根据由电路仿真器或验证工具执行的指令以及在执行指令时由仿真器或验证工具产生的波形数据产生显示。指令包括一组语句，每个语句对应于由电路产生的单独的电路信号，并且每个语句包括定义电路信号的值作为其他电路信号的值的函数的函数。模拟器在各种模拟时间对语句进行评估，以在这些模拟时间计算信号值。波形数据表示模拟器在评估语句时计算的信号值。调试器显示包括一组语句事件符号，每个对应于语句的单独评估，并且每个语句事件符号分别位于显示器中，以指示模拟器评估该语句的模拟时间。每个语句事件符号引用其值由相应的语句评估计算的信号，并指示在评估语句时计算的该信号的值。每个语句事件符号还引用具有值的其他信号，其中语句指示计算的信号值是函数，并且指示在评估语句时的模拟时间的那些其他信号值。

3. 发明申请

US20060190870A1 Latch modeling technique for formal verification 有权
标题翻译：锁定建模技术进行形式验证
公开(公告)号：US20060190870A1
公开(公告)日：2006-08-24
申请号：US11051109
申请日：2005-02-04
申请人： Yirng-An Chen , Robert Damiano , Bharat Kalyanpur , James Kukula
发明人： Yirng-An Chen , Robert Damiano , Bharat Kalyanpur , James Kukula
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F17/504 , G06F17/5045
摘要： A method for formal verification includes a latch remodeling process to reduce computational requirements for clock modeling. Latches that exhibit flip flop-like output behavior in a synthesized layout of sequential logic are identified and replaced with flip flops to generate a remodeled layout. This latch replacement can be performed using rules that filter out latches that do not exhibit flip flop-like output behavior. Clock modeling is then performed on the remodeled layout. Because the remodeled layout contains fewer latches than the original synthesized layout, the computational expense and time required for clock modeling (and hence, formal verification) on the remodeled layout can be significantly reduced over the requirements for clock modeling (and formal verification) on the original synthesized layout.
摘要翻译：用于形式验证的方法包括锁定重建过程以减少对时钟建模的计算需求。在顺序逻辑的合成布局中显示触发器状输出行为的锁存器被识别并用触发器代替以产生改造的布局。可以使用过滤掉不显示触发器状输出行为的锁存器的规则来执行该锁存器替换。然后在重新设计的布局上执行时钟建模。由于重新设计的布局包含比原始合成布局少的锁存器，因此在重构布局上的时钟建模（因此，形式验证）所需的计算费用和时间可以大大降低对时钟建模（和形式验证）对原始合成布局。

4. 发明授权

US07254793B2 Latch modeling technique for formal verification 有权
标题翻译：锁定建模技术进行形式验证
公开(公告)号：US07254793B2
公开(公告)日：2007-08-07
申请号：US11051109
申请日：2005-02-04
申请人： Yirng-An Chen , Robert F. Damiano , Bharat Kalyanpur , James H. Kukula
发明人： Yirng-An Chen , Robert F. Damiano , Bharat Kalyanpur , James H. Kukula
IPC分类号： G06F17/50 , G06F9/45 , G06F9/455
CPC分类号： G06F17/5022 , G06F17/504 , G06F17/5045
摘要： A method for formal verification includes a latch remodeling process to reduce computational requirements for clock modeling. Latches that exhibit flip flop-like output behavior in a synthesized layout of sequential logic are identified and replaced with flip flops to generate a remodeled layout. This latch replacement can be performed using rules that filter out latches that do not exhibit flip flop-like output behavior. Clock modeling is then performed on the remodeled layout. Because the remodeled layout contains fewer latches than the original synthesized layout, the computational expense and time required for clock modeling (and hence, formal verification) on the remodeled layout can be significantly reduced over the requirements for clock modeling (and formal verification) on the original synthesized layout.
摘要翻译：用于形式验证的方法包括锁定重建过程以减少对时钟建模的计算需求。在顺序逻辑的合成布局中显示触发器状输出行为的锁存器被识别并用触发器代替以产生改造的布局。可以使用过滤掉不显示触发器状输出行为的锁存器的规则来执行该锁存器替换。然后在重新设计的布局上执行时钟建模。由于重新设计的布局包含比原始合成布局少的锁存器，因此在重构布局上的时钟建模（因此，形式验证）所需的计算费用和时间可以大大降低对时钟建模（和形式验证）对原始合成布局。

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