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1. 发明申请

US20060190870A1 Latch modeling technique for formal verification 有权
标题翻译：锁定建模技术进行形式验证
公开(公告)号：US20060190870A1
公开(公告)日：2006-08-24
申请号：US11051109
申请日：2005-02-04
申请人： Yirng-An Chen , Robert Damiano , Bharat Kalyanpur , James Kukula
发明人： Yirng-An Chen , Robert Damiano , Bharat Kalyanpur , James Kukula
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F17/504 , G06F17/5045
摘要： A method for formal verification includes a latch remodeling process to reduce computational requirements for clock modeling. Latches that exhibit flip flop-like output behavior in a synthesized layout of sequential logic are identified and replaced with flip flops to generate a remodeled layout. This latch replacement can be performed using rules that filter out latches that do not exhibit flip flop-like output behavior. Clock modeling is then performed on the remodeled layout. Because the remodeled layout contains fewer latches than the original synthesized layout, the computational expense and time required for clock modeling (and hence, formal verification) on the remodeled layout can be significantly reduced over the requirements for clock modeling (and formal verification) on the original synthesized layout.
摘要翻译：用于形式验证的方法包括锁定重建过程以减少对时钟建模的计算需求。在顺序逻辑的合成布局中显示触发器状输出行为的锁存器被识别并用触发器代替以产生改造的布局。可以使用过滤掉不显示触发器状输出行为的锁存器的规则来执行该锁存器替换。然后在重新设计的布局上执行时钟建模。由于重新设计的布局包含比原始合成布局少的锁存器，因此在重构布局上的时钟建模（因此，形式验证）所需的计算费用和时间可以大大降低对时钟建模（和形式验证）对原始合成布局。

2. 发明申请

US20050044512A1 Method and apparatus for solving constraints 有权
标题翻译：解决约束的方法和装置
公开(公告)号：US20050044512A1
公开(公告)日：2005-02-24
申请号：US10642885
申请日：2003-08-18
申请人： Brian Lockyear , James Kukula , Robert Damiano
发明人： Brian Lockyear , James Kukula , Robert Damiano
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： A decomposition technique, for solving combinational constraint expressions, is presented. Decomposing a set of constraints can increase the opportunities for dividing them into independent sets that do not need to be conjoined in a constraint-solving process using a BDD representation. An AND decomposition, relying on a Theorem 1, is presented. An OR decomposition, relying on a corollary of Theorem 1, is presented. Theorem 1 provides an operation to test for, and create, a pair of sub-constraints G and H which are independent in any two variables x0 and x1. A decomposition procedure is presented for separating as many variables as possible, of an input constraint, into disjoint sub-constraints. A merging procedure is presented, that can be used if a decomposition does not only contain constraints whose support sets are disjoint from each other. The decomposition procedure can also be used to identify hold constraints.
摘要翻译：提出了一种解决组合约束表达式的分解技术。分解一组约束可以增加将它们划分为独立集合的机会，这些集合在使用BDD表示的约束解决过程中不需要联合。提出了依赖于定理1的AND分解。提出了依赖于定理1的推论的OR分解。定理1提供了测试和创建一对在任何两个变量x0和x1中独立的子约束G和H的操作。提出了一个分解过程，将尽可能多的输入约束变量分离成不相交的子约束。提出了合并过程，如果分解不仅包含其支持集彼此不相关的约束，则可以使用合并过程。分解过程也可用于识别持有约束。

3. 发明授权

US5754824A Logic synthesis for logic array modules 失效
标题翻译：逻辑阵列模块的逻辑综合
公开(公告)号：US5754824A
公开(公告)日：1998-05-19
申请号：US437918
申请日：1995-05-10
申请人： Robert Damiano , Ilan Yitshak Spillinger , Louise Helen Trevillyan , Lukas Paul Pieter Pepijn Van Ginneken
发明人： Robert Damiano , Ilan Yitshak Spillinger , Louise Helen Trevillyan , Lukas Paul Pieter Pepijn Van Ginneken
IPC分类号： G06F17/50 , G06F15/00
CPC分类号： G06F17/5054
摘要： A general approach to the synthesis of logic array modules (LAMs) is used to implement a multilevel combinational acyclic network. The network consists of abstract gates, which perform primitive logic functions and nets to connect them. The inputs to the entire network are called the primary inputs and the outputs of the entire network are the primary outputs. The first step in the synthesis of the LAMs used to implement the network is to partition the network vertically to define a plurality of logic segments wherein each output of a logic segment can potentially be implemented in a single logic array module. The second step is to partition horizontally the plurality of logic segments to reduce the size of the segments to a size that can efficiently be implemented as a logic array module. A symbolic representation is generated in a logic array module table of an internal structure of the logic array module based on the horizontally partitioned logic segments.
摘要翻译：逻辑阵列模块（LAM）的综合方法用于实现多电平组合非循环网络。网络由抽象门组成，执行原始逻辑功能和网络连接。整个网络的输入被称为主要输入，整个网络的输出是主要输出。用于实现网络的LAM的合成的第一步是垂直分割网络以定义多个逻辑段，其中逻辑段的每个输出可潜在地在单个逻辑阵列模块中实现。第二步是水平分割多个逻辑段以将段的大小减小到可以被有效地实现为逻辑阵列模块的大小。在逻辑阵列模块的逻辑阵列模块表中，基于水平分割的逻辑段生成符号表示。

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