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1. 发明授权

US07031899B2 System for characterizing simulated circuit logic and behavior 有权
公开(公告)号：US07031899B2
公开(公告)日：2006-04-18
申请号：US09829535
申请日：2001-04-09
申请人： Yu-Chin Hsu , Furshing Tsai , Tayung Liu , Bassam Tabbara , Kunming Ho , George Bakewell , Yirng-An Chen , Scott Sandler
发明人： Yu-Chin Hsu , Furshing Tsai , Tayung Liu , Bassam Tabbara , Kunming Ho , George Bakewell , Yirng-An Chen , Scott Sandler
IPC分类号： G06F3/147 , G06F3/153
CPC分类号： G06F17/5022
摘要： A circuit simulator simulates a circuit described by a circuit logic model as having a set of clocked registers interconnected by un-clocked logic to produce waveform data indicating states of each circuit input signal and of each register output signal as functions of clock signal edge timing. The waveform data and the logic model are then processed to produce a temporal schema model characterizing the circuit's logic and behavior. A display based on the temporal schema model depicts circuit behavior using separate symbols to represent successive circuit input signal states and register output signal states at various times during the simulation. The same display also graphically depicts fan-in or fan-out logical relationships by which circuit input signal states and register output signal states influence register input signal states.

2. 发明授权

US07079997B1 IC behavior analysis system 有权
标题翻译： IC行为分析系统
公开(公告)号：US07079997B1
公开(公告)日：2006-07-18
申请号：US10143347
申请日：2002-05-10
申请人： Yu-Chin Hsu , Furshing Tsai , Yirng-An Chen , Kunming Ho , Tayung Liu , Chieh Changfan , Wells Woei-Tzy Jong
发明人： Yu-Chin Hsu , Furshing Tsai , Yirng-An Chen , Kunming Ho , Tayung Liu , Chieh Changfan , Wells Woei-Tzy Jong
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： A debugger produces a display based on instructions executed by a circuit simulator or verification tool and on waveform data produced by the simulator or verification tool when executing the instructions. The instructions include a set of statements, each corresponding to a separate circuit signal generated by a circuit and each including a function defining a value of the circuit signal as a function of values of other circuit signals. The simulator evaluates the statements at various simulation times to compute signal values at those simulation times. The waveform data indicates signal values the simulator computes when evaluating the statements. The debugger display includes a set of statement event symbols, each corresponding to a separate evaluation of a statement and each positioned in the display to indicate a simulation time at which the simulator evaluated the statement. Each statement event symbol references the signal whose value is computed by the corresponding statement evaluation and indicates a value of that signal computed when the statement was evaluated. Each statement event symbol also references the other signals having values of which the statement indicates the computed signal value is a function and indicates those other signals values as of the simulation time at which the statement was evaluated.
摘要翻译：调试器根据由电路仿真器或验证工具执行的指令以及在执行指令时由仿真器或验证工具产生的波形数据产生显示。指令包括一组语句，每个语句对应于由电路产生的单独的电路信号，并且每个语句包括定义电路信号的值作为其他电路信号的值的函数的函数。模拟器在各种模拟时间对语句进行评估，以在这些模拟时间计算信号值。波形数据表示模拟器在评估语句时计算的信号值。调试器显示包括一组语句事件符号，每个对应于语句的单独评估，并且每个语句事件符号分别位于显示器中，以指示模拟器评估该语句的模拟时间。每个语句事件符号引用其值由相应的语句评估计算的信号，并指示在评估语句时计算的该信号的值。每个语句事件符号还引用具有值的其他信号，其中语句指示计算的信号值是函数，并且指示在评估语句时的模拟时间的那些其他信号值。

3. 发明授权

US06985840B1 Circuit property verification system 有权
标题翻译：电路属性验证系统
公开(公告)号：US06985840B1
公开(公告)日：2006-01-10
申请号：US09630348
申请日：2000-07-31
申请人： Yu-Chin Hsu , Furshing Tsai , Tayung Liu
发明人： Yu-Chin Hsu , Furshing Tsai , Tayung Liu
IPC分类号： G06F7/48
CPC分类号： G01R31/3181 , G01R31/3183 , G01R31/318314
摘要： Described herein is a system for verifying that a circuit described by a hardware description language file has a property of responding to an antecedent event represented by a particular pattern in its input signals by exhibiting a consequent behavior of producing a particular pattern in its output signals during a finite time following the antecedent event. The system includes a conventional circuit simulator for simulating the behavior of the circuit under conditions defined by a user-provided test bench. The simulator produces output waveform data representing the behavior of the circuit input, output and internal signals, including signals representing the circuit's state. When the output waveform data indicates the antecedent event has occurred, the system determines the current state of the circuit from the waveform data. The system then creates and analyzes a temporally expanded model of the circuit to verify whether, starting from that current state, the circuit will exhibit the consequent behavior within that finite time under all input signal conditions.
摘要翻译：这里描述了一种用于验证由硬件描述语言文件描述的电路具有响应于其输入信号中由特定模式表示的先行事件的性质的系统，其表现出在其输出信号中产生特定模式的结果行为在先前事件之后的有限时间。该系统包括用于在由用户提供的测试台定义的条件下模拟电路的行为的常规电路仿真器。模拟器产生表示电路输入，输出和内部信号的行为的输出波形数据，包括表示电路状态的信号。当输出波形数据表示先前事件发生时，系统根据波形数据确定电路的当前状态。然后，系统创建并分析电路的时间扩展模型，以验证从该当前状态开始，电路是否将在所有输入信号条件下的有限时间内展现出相应的行为。

4. 发明授权

US07478346B2 Debugging system for gate level IC designs 有权
标题翻译：门级IC设计调试系统
公开(公告)号：US07478346B2
公开(公告)日：2009-01-13
申请号：US11342125
申请日：2006-01-26
申请人： Yu-Chin Hsu , Furshing Tsai , Wori-Tzy Jong
发明人： Yu-Chin Hsu , Furshing Tsai , Wori-Tzy Jong
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5022
摘要： A synthesizer or emulator processes a gate level IC design derived from an RTL design to produce a gate level dump file indicating how signals of the gate level design behave. The gate level dump file is converted into an RTL dump file indicating how signals of the RTL design behave. A debugger processes the RTL dump file to produce displays depicting the RTL design and behavior of signals indicated by the RTL dump file. Thus while the IC is simulated or emulated at the gate level of the design to produce waveform data for a debugger, the gate level-to-RTL dump file conversion process enables a designer debug the more familiar RTL design based on the gate level simulation or emulation results. file conversion process enables a designer debug the more familiar RTL design based on the gate level simulation or emulation results.
摘要翻译：合成器或仿真器处理从RTL设计派生的门级IC设计，以产生指示门级设计的信号行为的门级转储文件。门级转储文件转换为RTL转储文件，指示RTL设计的信号如何运行。调试器处理RTL转储文件以产生描绘RTL转换文件指示的信号的RTL设计和行为的显示。因此，当IC在设计的门级模拟或仿真以产生调试器的波形数据时，门级到RTL转储文件转换过程使得设计者能够根据门级仿真或调试更熟悉的RTL设计，仿真结果。文件转换过程使设计人员能够根据门级仿真或仿真结果调试更熟悉的RTL设计。

5. 发明申请

US20100192115A1 POWER-AWARE DEBUGGING 有权
标题翻译：功率检测
公开(公告)号：US20100192115A1
公开(公告)日：2010-07-29
申请号：US12558259
申请日：2009-09-11
申请人： Kai Yang , Tayung Liu , Furshing Tsai , Ting Shih Ang , Chih Neng Hsu
发明人： Kai Yang , Tayung Liu , Furshing Tsai , Ting Shih Ang , Chih Neng Hsu
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F2217/78
摘要： A debugging system produces displays in response to an IC design and results of a logic simulation of IC behavior based on the IC design. The IC design includes a hardware description language (HDL) model of the IC describing the IC as comprising cell instances communicating via data signals and power sources for supplying power to the cell instances. The IC design also includes power definition markup language (PDML) model describing a power intent of the IC design. The debugging system generates displays representing HDL code that are annotated to indicate how the power intent of the IC design described by the PDML model relates to the portion of the HDL model represented by the display. The debugging system also generates signals trace displays indicating how both the logic and power intent of the IC design affect the value of a user-selected signal at a user-selected time during the logic simulation.
摘要翻译：调试系统根据IC设计和基于IC设计的IC行为的逻辑仿真结果生成显示器。该IC设计包括描述IC的IC的硬件描述语言（HDL）模型，其包括经由数据信号进行通信的小区实例和用于向小区实例供电的电源。 IC设计还包括描述IC设计的功率意图的功率定义标记语言（PDML）模型。调试系统产生表示HDL代码的显示器，其被注释以指示由PDML模型描述的IC设计的功率意图与由显示器表示的HDL模型的部分有关。调试系统还生成信号跟踪显示，指示IC设计的逻辑和电源意图如何在逻辑模拟期间在用户选择的时间影响用户选择的信号的值。

6. 发明授权

US08176453B2 Power-aware debugging 有权
标题翻译：电源感知调试
公开(公告)号：US08176453B2
公开(公告)日：2012-05-08
申请号：US12558259
申请日：2009-09-11
申请人： Kai Yang , Tayung Liu , Furshing Tsai , Ting Shih Ang , Chih Neng Hsu , Jun Zhao
发明人： Kai Yang , Tayung Liu , Furshing Tsai , Ting Shih Ang , Chih Neng Hsu , Jun Zhao
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F2217/78
摘要： A debugging system produces displays in response to an IC design and results of a logic simulation of IC behavior based on the IC design. The IC design includes a hardware description language (HDL) model of the IC describing the IC as comprising cell instances communicating via data signals and power sources for supplying power to the cell instances. The IC design also includes power definition markup language (PDML) model describing a power intent of the IC design. The debugging system generates displays representing HDL code that are annotated to indicate how the power intent of the IC design described by the PDML model relates to the portion of the HDL model represented by the display. The debugging system also generates signals trace displays indicating how both the logic and power intent of the IC design affect the value of a user-selected signal at a user-selected time during the logic simulation.
摘要翻译：调试系统根据IC设计和基于IC设计的IC行为的逻辑仿真结果生成显示器。该IC设计包括描述IC的IC的硬件描述语言（HDL）模型，其包括经由数据信号进行通信的小区实例和用于向小区实例供电的电源。 IC设计还包括描述IC设计的功率意图的功率定义标记语言（PDML）模型。调试系统产生表示HDL代码的显示器，其被注释以指示由PDML模型描述的IC设计的功率意图与由显示器表示的HDL模型的部分有关。调试系统还生成信号跟踪显示，指示IC设计的逻辑和电源意图如何在逻辑模拟期间在用户选择的时间影响用户选择的信号的值。

7. 发明申请

US20070174805A1 Debugging system for gate level IC designs 有权
标题翻译：门级IC设计调试系统
公开(公告)号：US20070174805A1
公开(公告)日：2007-07-26
申请号：US11342125
申请日：2006-01-26
申请人： Yu-Chin Hsu , Furshing Tsai , Wori-Tzy Jong
发明人： Yu-Chin Hsu , Furshing Tsai , Wori-Tzy Jong
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： A register transfer level (RTL) IC design describing a IC as comprising a plurality of logic blocks communicating via signals and using a high level language to describe the logic blocks according to the logical relationships between signals they receive and signals they generate. A computer-aided synthesizer processes an RTL IC design to produce a gate level design for the IC describing its logic blocks as comprising instances of cells communicating via signals. A synthesizer or emulator processes the gate level design to produce a gate level dump file referencing signals of the gate level design and indicating how those signals behave in response to time-varying signals supplied as inputs to the IC. The gate level dump file is converted into an RTL dump file referencing signals of the RTL design and indicating how those signals behave. A debugger processes the RTL dump file to produce displays depicting the RTL design and behavior of signals indicated by the RTL dump file. Thus while the IC is simulated or emulated at the gate level of the design to produce waveform data for a debugger, the gate level-to-RTL dump file conversion process enables a designer debug the more familiar RTL design based on the gate level simulation or emulation results.
摘要翻译：一种描述IC的寄存器传送级（RTL）IC设计，其包括通过信号通信的多个逻辑块，并且使用高级语言根据它们接收的信号与它们产生的信号之间的逻辑关系来描述逻辑块。计算机辅助合成器处理RTL IC设计以产生描述其逻辑块的IC的门级设计，包括通过信号通信的小区的实例。合成器或仿真器处理门电平设计以产生参考门级设计的信号的栅极电平转储文件，并指示这些信号如何响应于作为IC的输入提供的时变信号而行为。门级转储文件转换为引用RTL设计信号的RTL转储文件，并指示这些信号的行为。调试器处理RTL转储文件以产生描绘RTL转换文件指示的信号的RTL设计和行为的显示。因此，当IC在设计的门级模拟或仿真以产生调试器的波形数据时，门级到RTL转储文件转换过程使得设计者能够根据门级仿真或调试更熟悉的RTL设计，仿真结果。

8. 发明申请

US20120084744A1 Methods and Systems for Debugging Equivalent Designs Described at Different Design Levels 有权
标题翻译：用于调试不同设计级别的等效设计的方法和系统
公开(公告)号：US20120084744A1
公开(公告)日：2012-04-05
申请号：US13084061
申请日：2011-04-11
申请人： Lu-An Ko , Xi Chen , Arnold Sher , Furshing Tsai
发明人： Lu-An Ko , Xi Chen , Arnold Sher , Furshing Tsai
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： Methods for debugging designs are provided. First, signal correlation information for signals of a design at least two design level is obtained. Then, design descriptions corresponding to the design at the at least two design levels are loaded and presented in at least two sets of windows or at least two debugging processes which controls the respective set of windows. A selection of a first signal in a first set of windows or a first debugging process is received. In response to the selection, a second signal corresponding to the first signal is queried according to the signal correlation information, and the second signal in a second set of windows or a second debugging process is automatically selected.
摘要翻译：提供了调试设计的方法。首先，获得设计信号至少两个设计级的信号相关信息。然后，在至少两个设计级别对应于设计的设计描述被加载并呈现在至少两组窗口中，或者至少两个控制相应窗口集合的调试过程。接收在第一组窗口中的第一信号的选择或第一调试过程。响应于选择，根据信号相关信息查询对应于第一信号的第二信号，并且自动选择第二组窗口中的第二信号或第二调试过程。

9. 发明授权

US08359560B2 Methods and systems for debugging equivalent designs described at different design levels 有权
标题翻译：用于调试在不同设计级别描述的等效设计的方法和系统
公开(公告)号：US08359560B2
公开(公告)日：2013-01-22
申请号：US13084061
申请日：2011-04-11
申请人： Lu-An Ko , Xi Chen , Arnold Sher , Furshing Tsai
发明人： Lu-An Ko , Xi Chen , Arnold Sher , Furshing Tsai
IPC分类号： G06F9/455
CPC分类号： G06F17/5022
摘要： Methods for debugging designs are provided. First, signal correlation information for signals of a design at least two design level is obtained. Then, design descriptions corresponding to the design at the at least two design levels are loaded and presented in at least two sets of windows or at least two debugging processes which controls the respective set of windows. A selection of a first signal in a first set of windows or a first debugging process is received. In response to the selection, a second signal corresponding to the first signal is queried according to the signal correlation information, and the second signal in a second set of windows or a second debugging process is automatically selected.
摘要翻译：提供了调试设计的方法。首先，获得设计信号至少两个设计级的信号相关信息。然后，在至少两个设计级别对应于设计的设计描述被加载并呈现在至少两组窗口中，或者至少两个控制相应窗口集合的调试过程。接收在第一组窗口中的第一信号的选择或第一调试过程。响应于选择，根据信号相关信息查询对应于第一信号的第二信号，并且自动选择第二组窗口中的第二信号或第二调试过程。

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