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1. 发明授权

US08176453B2 Power-aware debugging 有权
标题翻译：电源感知调试
公开(公告)号：US08176453B2
公开(公告)日：2012-05-08
申请号：US12558259
申请日：2009-09-11
申请人： Kai Yang , Tayung Liu , Furshing Tsai , Ting Shih Ang , Chih Neng Hsu , Jun Zhao
发明人： Kai Yang , Tayung Liu , Furshing Tsai , Ting Shih Ang , Chih Neng Hsu , Jun Zhao
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F2217/78
摘要： A debugging system produces displays in response to an IC design and results of a logic simulation of IC behavior based on the IC design. The IC design includes a hardware description language (HDL) model of the IC describing the IC as comprising cell instances communicating via data signals and power sources for supplying power to the cell instances. The IC design also includes power definition markup language (PDML) model describing a power intent of the IC design. The debugging system generates displays representing HDL code that are annotated to indicate how the power intent of the IC design described by the PDML model relates to the portion of the HDL model represented by the display. The debugging system also generates signals trace displays indicating how both the logic and power intent of the IC design affect the value of a user-selected signal at a user-selected time during the logic simulation.
摘要翻译：调试系统根据IC设计和基于IC设计的IC行为的逻辑仿真结果生成显示器。该IC设计包括描述IC的IC的硬件描述语言（HDL）模型，其包括经由数据信号进行通信的小区实例和用于向小区实例供电的电源。 IC设计还包括描述IC设计的功率意图的功率定义标记语言（PDML）模型。调试系统产生表示HDL代码的显示器，其被注释以指示由PDML模型描述的IC设计的功率意图与由显示器表示的HDL模型的部分有关。调试系统还生成信号跟踪显示，指示IC设计的逻辑和电源意图如何在逻辑模拟期间在用户选择的时间影响用户选择的信号的值。

2. 发明申请

US20100192115A1 POWER-AWARE DEBUGGING 有权
标题翻译：功率检测
公开(公告)号：US20100192115A1
公开(公告)日：2010-07-29
申请号：US12558259
申请日：2009-09-11
申请人： Kai Yang , Tayung Liu , Furshing Tsai , Ting Shih Ang , Chih Neng Hsu
发明人： Kai Yang , Tayung Liu , Furshing Tsai , Ting Shih Ang , Chih Neng Hsu
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F2217/78
摘要： A debugging system produces displays in response to an IC design and results of a logic simulation of IC behavior based on the IC design. The IC design includes a hardware description language (HDL) model of the IC describing the IC as comprising cell instances communicating via data signals and power sources for supplying power to the cell instances. The IC design also includes power definition markup language (PDML) model describing a power intent of the IC design. The debugging system generates displays representing HDL code that are annotated to indicate how the power intent of the IC design described by the PDML model relates to the portion of the HDL model represented by the display. The debugging system also generates signals trace displays indicating how both the logic and power intent of the IC design affect the value of a user-selected signal at a user-selected time during the logic simulation.
摘要翻译：调试系统根据IC设计和基于IC设计的IC行为的逻辑仿真结果生成显示器。该IC设计包括描述IC的IC的硬件描述语言（HDL）模型，其包括经由数据信号进行通信的小区实例和用于向小区实例供电的电源。 IC设计还包括描述IC设计的功率意图的功率定义标记语言（PDML）模型。调试系统产生表示HDL代码的显示器，其被注释以指示由PDML模型描述的IC设计的功率意图与由显示器表示的HDL模型的部分有关。调试系统还生成信号跟踪显示，指示IC设计的逻辑和电源意图如何在逻辑模拟期间在用户选择的时间影响用户选择的信号的值。

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