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1. 发明申请

US20100065898A1 Integrated circuit semiconductor device having different gate stacks in cell region and core/peripheral region and method of manufacturing the same 审中-公开
标题翻译：在单元区域和核心/外围区域中具有不同栅极堆叠的集成电路半导体器件及其制造方法
公开(公告)号：US20100065898A1
公开(公告)日：2010-03-18
申请号：US12458438
申请日：2009-07-13
申请人： Young-jin Choi , Kang-ill Seo
发明人： Young-jin Choi , Kang-ill Seo
IPC分类号： H01L27/108 , H01L21/8242
CPC分类号： H01L29/66621 , H01L21/823462 , H01L27/10894 , H01L29/78
摘要： The integrated circuit semiconductor device includes a semiconductor substrate having a cell region and a core/peripheral region, a first gate stack including a first gate insulating film and a first gate electrode on the semiconductor substrate in the cell region, wherein the first gate insulating film includes a silicon oxide film and the first gate electrode includes a poly-silicon film doped with impurities, and a second gate stack including a second gate insulating film and a second gate electrode on the semiconductor substrate of the core/peripheral region, the second gate insulating film includes a high dielectric film having a higher dielectric constant than that of the silicon oxide film and the second gate electrode includes a metal film.
摘要翻译：集成电路半导体器件包括具有单元区域和核心/外围区域的半导体衬底，在单元区域中的半导体衬底上的包括第一栅极绝缘膜和第一栅电极的第一栅极堆叠，其中第一栅极绝缘膜包括氧化硅膜，并且所述第一栅极包括掺杂有杂质的多晶硅膜和在所述芯/外围区域的半导体衬底上的包括第二栅极绝缘膜和第二栅电极的第二栅极堆叠，所述第二栅极绝缘膜包括具有比氧化硅膜高的介电常数的高电介质膜，第二栅电极包括金属膜。

2. 发明申请

US20120088342A1 Methods of Fabricating Devices Including Source/Drain Region with Abrupt Junction Profile 有权
标题翻译：制造包括具有突变接头型材的源/排放区域的设备的方法
公开(公告)号：US20120088342A1
公开(公告)日：2012-04-12
申请号：US13218547
申请日：2011-08-26
申请人： Li Ming , Sangpil Sim , Kang-ill Seo , Changwoo Oh , Dongil Bae
发明人： Li Ming , Sangpil Sim , Kang-ill Seo , Changwoo Oh , Dongil Bae
IPC分类号： H01L21/8238 , H01L21/336
CPC分类号： H01L21/823807 , H01L21/823814
摘要： Provided are methods of fabricating a semiconductor device including a metal oxide semiconductor (MOS) transistor. The methods include forming a gate pattern on a semiconductor substrate. The semiconductor substrate is etched using the gate pattern as an etching mask to form a pair of active trenches spaced apart from each other in the semiconductor substrate. Epitaxial layers are formed in the active trenches, respectively. The respective epitaxial layers are formed by sequentially stacking first and second layers. The first and second layers are formed of a semiconductor layer having a lattice constant greater than the semiconductor substrate, and a composition ratio of the second layer is different from that of the first layer. Semiconductor devices having the first and second layers are also provided.
摘要翻译：提供制造包括金属氧化物半导体（MOS）晶体管的半导体器件的方法。所述方法包括在半导体衬底上形成栅极图案。使用栅极图案蚀刻半导体衬底作为蚀刻掩模，以在半导体衬底中形成彼此间隔开的一对有源沟槽。分别在有源沟槽中形成外延层。通过依次层叠第一层和第二层形成各个外延层。第一层和第二层由具有大于半导体衬底的晶格常数的半导体层形成，并且第二层的组成比不同于第一层的组成比。还提供具有第一和第二层的半导体器件。

3. 发明授权

US06642107B2 Non-volatile memory device having self-aligned gate structure and method of manufacturing same 有权
标题翻译：具有自对准栅极结构的非易失性存储器件及其制造方法
公开(公告)号：US06642107B2
公开(公告)日：2003-11-04
申请号：US10191119
申请日：2002-07-09
申请人： Kang-ill Seo , Jae-seung Hwang , Seung-min Lee
发明人： Kang-ill Seo , Jae-seung Hwang , Seung-min Lee
IPC分类号： H01L21336
CPC分类号： H01L21/28273 , H01L27/115 , H01L27/11521
摘要： A method for manufacturing a non-volatile memory device including a self-aligned gate structure, and a non-volatile memory device manufactured by the same method, are provided. In the method for manufacturing a non-volatile memory device, a tunnel dielectric layer is formed on a semiconductor substrate. First floating gate patterns are formed on the tunnel dielectric layer. Mold patterns are formed on the first floating gate patterns to selectively expose predetermined portions of the first floating gate patterns. Floating gates are formed by removing the exposed portions of the first floating gate patterns using the mold patterns as a mask. Interlayer dielectric layer patterns are formed for insulating the floating gates from one another by filling gaps between the mold patterns. The mold patterns exposed between the interlayer dielectric layer patterns are formed using the interlayer dielectric layer patterns as an etching mask. A dielectric layer is formed on the floating gates exposed by the removal of the mold patterns, between the interlayer dielectric layer patterns. Control gates are formed, aligned with the floating gates, by filling gaps between the interlayer dielectric layer patterns on the dielectric layer.
摘要翻译：提供了一种用于制造包括自对准栅极结构的非易失性存储器件的方法和通过相同方法制造的非易失性存储器件。在制造非易失性存储器件的方法中，在半导体衬底上形成隧道电介质层。在隧道介电层上形成第一浮栅图形。模具图案形成在第一浮栅图案上以选择性地暴露第一浮栅图案的预定部分。通过使用模具图案作为掩模去除第一浮动栅极图案的暴露部分来形成浮动栅极。形成层间电介质层图案，用于通过填充模具图案之间的间隙来将浮栅彼此绝缘。使用层间电介质层图案作为蚀刻掩模形成在层间电介质层图案之间露出的模具图案。介电层通过在层间电介质层图案之间移除模具图案而在浮栅上形成。通过填充电介质层上的层间电介质层图案之间的间隙，形成与浮动栅极对准的控制栅极。

4. 发明授权

US06573139B2 Method of fabricating cell of flash memory device 失效
公开(公告)号：US06573139B2
公开(公告)日：2003-06-03
申请号：US09903977
申请日：2001-07-12
申请人： Seong-soo Lee , Joon Kim , Kang-ill Seo
发明人： Seong-soo Lee , Joon Kim , Kang-ill Seo
IPC分类号： H01L21336
CPC分类号： H01L27/11521 , H01L27/115
摘要： A method of forming a floating gate electrode of a cell of a flash memory device having an interval less than a critical dimension (CD) in a conventional photolithographic process, in which the reliability of a dielectric layer does not deteriorate and damage to a floating gate electrode during etching is prevented, is provided. According to the present invention, a protective layer formed of a material having a high etching selectivity with respect to a device isolation layer and a doped polysilicon layer is formed on the upper surface of the doped polysilicon layer forming the floating gate electrode. The protective layer is partially etched and includes a recess. Next, a material layer for forming a spacer, which is formed of a material having a high etching selectivity with respect to the device isolation layer and the doped polysilicon layer, is formed on the upper surface of the protective layer and is etched back, thus forming the spacer. Damage to the doped polysilicon layer during etching is prevented by the protective layer containing the recess. The floating gate electrode, which is arranged at an interval less than a limit value in a photolithographic process, can be formed by the spacer. The spacer and the protective layer are removed, and a step difference does not occur at edges of the floating gate electrode. Thus deterioration of the reliability of a dielectric layer formed on top of the floating gate electrode can be prevented.

5. 发明授权

US08679910B2 Methods of fabricating devices including source/drain region with abrupt junction profile 有权
标题翻译：制造器件的方法包括具有突变结型材的源极/漏极区域
公开(公告)号：US08679910B2
公开(公告)日：2014-03-25
申请号：US13218547
申请日：2011-08-26
申请人： Li Ming , Sangpil Sim , Kang-ill Seo , Changwoo Oh , Dongil Bae
发明人： Li Ming , Sangpil Sim , Kang-ill Seo , Changwoo Oh , Dongil Bae
IPC分类号： H01L21/00
CPC分类号： H01L21/823807 , H01L21/823814
摘要： Provided are methods of fabricating a semiconductor device including a metal oxide semiconductor (MOS) transistor. The methods include forming a gate pattern on a semiconductor substrate. The semiconductor substrate is etched using the gate pattern as an etching mask to form a pair of active trenches spaced apart from each other in the semiconductor substrate. Epitaxial layers are formed in the active trenches, respectively. The respective epitaxial layers are formed by sequentially stacking first and second layers. The first and second layers are formed of a semiconductor layer having a lattice constant greater than the semiconductor substrate, and a composition ratio of the second layer is different from that of the first layer. Semiconductor devices having the first and second layers are also provided.
摘要翻译：提供制造包括金属氧化物半导体（MOS）晶体管的半导体器件的方法。所述方法包括在半导体衬底上形成栅极图案。使用栅极图案作为蚀刻掩模蚀刻半导体衬底，以在半导体衬底中形成彼此间隔开的一对有源沟槽。分别在有源沟槽中形成外延层。通过依次层叠第一层和第二层形成各个外延层。第一层和第二层由具有大于半导体衬底的晶格常数的半导体层形成，并且第二层的组成比不同于第一层的组成比。还提供具有第一和第二层的半导体器件。

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