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1. 发明申请

US20110204434A1 SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20110204434A1
公开(公告)日：2011-08-25
申请号：US12955084
申请日：2010-11-29
申请人： SEUNGHUN SON , Dongil Bae , Jongchol Kim , Seong-Cheol Paek
发明人： SEUNGHUN SON , Dongil Bae , Jongchol Kim , Seong-Cheol Paek
IPC分类号： H01L29/78
CPC分类号： H01L29/7833 , H01L29/0653 , H01L29/6659 , H01L29/66636
摘要： Provided are a semiconductor device and a method of fabricating the same. The semiconductor device includes, a gate structure having a gate dielectric layer, a gate electrode, and a spacer, which are each formed on a substrate, a first impurity area formed in a portion of the substrate located below the spacer, a second impurity area in contact with a sidewall of the first impurity area and formed in the substrate on both sides of the gate structure, and a dielectric pattern in contact with a portion of the first impurity area and formed on a sidewall of the second impurity area. At this time, the second impurity area may include an upper part with an upward-narrowing width and a lower part with a downward-narrowing width.
摘要翻译：提供半导体器件及其制造方法。半导体器件包括：栅极电介质层，栅极电极和间隔物的栅极结构，各自形成在衬底上;第一杂质区域，形成在衬底的位于间隔物下方的部分;第二杂质区域与第一杂质区域的侧壁接触并形成在栅极结构的两侧的基板中，以及与第一杂质区域的一部分接触并形成在第二杂质区域的侧壁上的电介质图案。此时，第二杂质区域可以包括具有向上变窄宽度的上部和具有向下变窄的宽度的下部。

2. 发明授权

US08679910B2 Methods of fabricating devices including source/drain region with abrupt junction profile 有权
标题翻译：制造器件的方法包括具有突变结型材的源极/漏极区域
公开(公告)号：US08679910B2
公开(公告)日：2014-03-25
申请号：US13218547
申请日：2011-08-26
申请人： Li Ming , Sangpil Sim , Kang-ill Seo , Changwoo Oh , Dongil Bae
发明人： Li Ming , Sangpil Sim , Kang-ill Seo , Changwoo Oh , Dongil Bae
IPC分类号： H01L21/00
CPC分类号： H01L21/823807 , H01L21/823814
摘要： Provided are methods of fabricating a semiconductor device including a metal oxide semiconductor (MOS) transistor. The methods include forming a gate pattern on a semiconductor substrate. The semiconductor substrate is etched using the gate pattern as an etching mask to form a pair of active trenches spaced apart from each other in the semiconductor substrate. Epitaxial layers are formed in the active trenches, respectively. The respective epitaxial layers are formed by sequentially stacking first and second layers. The first and second layers are formed of a semiconductor layer having a lattice constant greater than the semiconductor substrate, and a composition ratio of the second layer is different from that of the first layer. Semiconductor devices having the first and second layers are also provided.
摘要翻译：提供制造包括金属氧化物半导体（MOS）晶体管的半导体器件的方法。所述方法包括在半导体衬底上形成栅极图案。使用栅极图案作为蚀刻掩模蚀刻半导体衬底，以在半导体衬底中形成彼此间隔开的一对有源沟槽。分别在有源沟槽中形成外延层。通过依次层叠第一层和第二层形成各个外延层。第一层和第二层由具有大于半导体衬底的晶格常数的半导体层形成，并且第二层的组成比不同于第一层的组成比。还提供具有第一和第二层的半导体器件。

3. 发明申请

US20120088342A1 Methods of Fabricating Devices Including Source/Drain Region with Abrupt Junction Profile 有权
标题翻译：制造包括具有突变接头型材的源/排放区域的设备的方法
公开(公告)号：US20120088342A1
公开(公告)日：2012-04-12
申请号：US13218547
申请日：2011-08-26
申请人： Li Ming , Sangpil Sim , Kang-ill Seo , Changwoo Oh , Dongil Bae
发明人： Li Ming , Sangpil Sim , Kang-ill Seo , Changwoo Oh , Dongil Bae
IPC分类号： H01L21/8238 , H01L21/336
CPC分类号： H01L21/823807 , H01L21/823814
摘要： Provided are methods of fabricating a semiconductor device including a metal oxide semiconductor (MOS) transistor. The methods include forming a gate pattern on a semiconductor substrate. The semiconductor substrate is etched using the gate pattern as an etching mask to form a pair of active trenches spaced apart from each other in the semiconductor substrate. Epitaxial layers are formed in the active trenches, respectively. The respective epitaxial layers are formed by sequentially stacking first and second layers. The first and second layers are formed of a semiconductor layer having a lattice constant greater than the semiconductor substrate, and a composition ratio of the second layer is different from that of the first layer. Semiconductor devices having the first and second layers are also provided.
摘要翻译：提供制造包括金属氧化物半导体（MOS）晶体管的半导体器件的方法。所述方法包括在半导体衬底上形成栅极图案。使用栅极图案蚀刻半导体衬底作为蚀刻掩模，以在半导体衬底中形成彼此间隔开的一对有源沟槽。分别在有源沟槽中形成外延层。通过依次层叠第一层和第二层形成各个外延层。第一层和第二层由具有大于半导体衬底的晶格常数的半导体层形成，并且第二层的组成比不同于第一层的组成比。还提供具有第一和第二层的半导体器件。

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