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1. 发明授权

US07659162B2 Phase change memory device and method of manufacturing the same 有权
标题翻译：相变存储器件及其制造方法
公开(公告)号：US07659162B2
公开(公告)日：2010-02-09
申请号：US12285531
申请日：2008-10-08
申请人： Young-Soo Lim , Yong-Sun Ko , Sung-Un Kwon , Jae-Seung Hwang
发明人： Young-Soo Lim , Yong-Sun Ko , Sung-Un Kwon , Jae-Seung Hwang
IPC分类号： H01L21/8242
CPC分类号： H01L45/12 , H01L27/2436 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/1675
摘要： A method of manufacturing a phase change memory device includes forming at least one active device on a substrate, forming a bottom electrode electrically connected to the at least one active device, forming a phase change material layer and a top electrode on the bottom electrode, forming a capping layer on an upper surface of the top electrode and on side surfaces of the top electrode and phase change material layer, removing a portion of the capping layer overlapping the upper surface of the top electrode to define capping layer sidewall portions, forming an interlayer insulation film on the capping layer sidewall portions and on the top electrode, removing a portion of the interlayer insulation film from the top electrode to form a contact hole through the interlayer insulation film, and forming a contact plug in the contact hole.
摘要翻译：一种制造相变存储器件的方法包括在衬底上形成至少一个有源器件，形成与该至少一个有源器件电连接的底部电极，在底部电极上形成相变材料层和顶部电极，形成在顶部电极的上表面上和顶部电极和相变材料层的侧表面上的覆盖层，去除与顶部电极的上表面重叠的覆盖层的一部分以限定覆盖层侧壁部分，形成中间层绝缘膜在顶盖电极上，从上电极去除一部分层间绝缘膜，以形成穿过层间绝缘膜的接触孔，并在接触孔中形成接触塞。

2. 发明申请

US20090090899A1 Phase change memory device and method of manufacturing the same 有权
标题翻译：相变存储器件及其制造方法
公开(公告)号：US20090090899A1
公开(公告)日：2009-04-09
申请号：US12285531
申请日：2008-10-08
申请人： Young-Soo Lim , Yong-Sun Ko , Sung-Un Kwon , Jae-Seung Hwang
发明人： Young-Soo Lim , Yong-Sun Ko , Sung-Un Kwon , Jae-Seung Hwang
IPC分类号： H01L45/00
CPC分类号： H01L45/12 , H01L27/2436 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/1675
摘要： A method of manufacturing a phase change memory device includes forming at least one active device on a substrate, forming a bottom electrode electrically connected to the at least one active device, forming a phase change material layer and a top electrode on the bottom electrode, forming a capping layer on an upper surface of the top electrode and on side surfaces of the top electrode and phase change material layer, removing a portion of the capping layer overlapping the upper surface of the top electrode to define capping layer sidewall portions, forming an interlayer insulation film on the capping layer sidewall portions and on the top electrode, removing a portion of the interlayer insulation film from the top electrode to form a contact hole through the interlayer insulation film, and forming a contact plug in the contact hole.
摘要翻译：一种制造相变存储器件的方法包括在衬底上形成至少一个有源器件，形成与该至少一个有源器件电连接的底部电极，在底部电极上形成相变材料层和顶部电极，形成在顶部电极的上表面上以及顶部电极和相变材料层的侧表面上的覆盖层，去除与顶部电极的上表面重叠的覆盖层的一部分以限定覆盖层侧壁部分，形成中间层绝缘膜在顶盖电极上，从上电极去除一部分层间绝缘膜，以形成穿过层间绝缘膜的接触孔，并在接触孔中形成接触塞。

3. 发明申请

US20070210334A1 Phase change memory device and method of fabricating the same 审中-公开
标题翻译：相变存储器件及其制造方法
公开(公告)号：US20070210334A1
公开(公告)日：2007-09-13
申请号：US11698155
申请日：2007-01-26
申请人： Young-Soo Lim , Yong-Sun Ko , Hyuk-Jin Kwon , Jae-Seung Hwang
发明人： Young-Soo Lim , Yong-Sun Ko , Hyuk-Jin Kwon , Jae-Seung Hwang
IPC分类号： H01L31/00
CPC分类号： H01L45/143 , H01L27/2436 , H01L45/06 , H01L45/126 , H01L45/144 , H01L45/1675
摘要： Example embodiments relate to a semiconductor memory device and a method of fabricating the same. Other example embodiments relate to a phase change memory device and a method of fabricating the same. There are provided a phase change memory device and a method of fabricating the same for improving or maximizing a production yield. The method comprises: after first removing a first hard mask layer used to form a contact pad electrically connected to a semiconductor substrate, forming a lower electrode to be electrically connected to the contact pad through a first contact hole in a first interlayer insulating layer formed on the contact pad and to have a thickness equal or similar to a thickness of the first interlayer insulating layer; and forming a phase change layer and an upper electrode on the lower electrode. Because change of the resistance value of the lower electrode is reduced or prevented, which has been caused due to a non-uniform thickness of a conventional first hard mask layer, a production yield may be improved.
摘要翻译：示例性实施例涉及半导体存储器件及其制造方法。其他示例性实施例涉及相变存储器件及其制造方法。提供了一种相变存储器件及其制造方法，用于改善或最大化产量。该方法包括：在首先去除用于形成与半导体衬底电连接的接触焊盘的第一硬掩模层之后，通过形成在第一层间绝缘层上的第一层间绝缘层中的第一接触孔形成下电极以与接触焊盘电连接所述接触焊盘的厚度等于或类似于所述第一层间绝缘层的厚度; 并在下电极上形成相变层和上电极。由于由于常规的第一硬掩模层的厚度不均匀而导致的下部电极的电阻值的变化被降低或防止，所以可以提高生产率。

4. 发明授权

US08133757B2 Method of manufacturing a phase changeable memory unit having an enhanced structure to reduce a reset current 有权
标题翻译：制造具有增强结构以减少复位电流的相变存储器单元的方法
公开(公告)号：US08133757B2
公开(公告)日：2012-03-13
申请号：US12592816
申请日：2009-12-03
申请人： Hyun-Suk Kwon , Young-Soo Lim , Sung-Un Kwon , Yong-Ho Ha , Jeong-Hee Park , Joon-Sang Park , Myung-Jin Kang , Doo-Hwan Park
发明人： Hyun-Suk Kwon , Young-Soo Lim , Sung-Un Kwon , Yong-Ho Ha , Jeong-Hee Park , Joon-Sang Park , Myung-Jin Kang , Doo-Hwan Park
IPC分类号： H01L29/02
CPC分类号： H01L27/2436 , H01L27/2409 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/1625 , H01L45/1683
摘要： A phase changeable memory unit includes a lower electrode, an insulating interlayer structure having an opening, a phase changeable material layer and an upper electrode. The lower electrode is formed on a substrate. The insulating interlayer structure has an opening and is formed on the lower electrode and the substrate. The opening exposes the lower electrode and has a width gradually decreasing downward. The phase changeable material layer fills the opening and partially covers an upper face of the insulating interlayer structure. The upper electrode is formed on the phase changeable material layer.
摘要翻译：相变存储单元包括下电极，具有开口的绝缘层间结构，相变材料层和上电极。下电极形成在基板上。绝缘层间结构具有开口并且形成在下电极和基板上。开口露出下电极并且具有向下逐渐减小的宽度。相变材料层填充开口并部分地覆盖绝缘层间结构的上表面。上电极形成在相变材料层上。

5. 发明申请

US20100144135A1 Method of manufacturing a phase changeable memory unit 有权
标题翻译：制造相变存储器单元的方法
公开(公告)号：US20100144135A1
公开(公告)日：2010-06-10
申请号：US12592816
申请日：2009-12-03
申请人： Hyun-Suk Kwon , Young-Soo Lim , Sung-Un Kwon , Yong-Ho Ha , Jeong-Hee Park , Joon-Sang Park , Myung-Jin Kang , Doo-Hwan Park
发明人： Hyun-Suk Kwon , Young-Soo Lim , Sung-Un Kwon , Yong-Ho Ha , Jeong-Hee Park , Joon-Sang Park , Myung-Jin Kang , Doo-Hwan Park
IPC分类号： H01L21/443
CPC分类号： H01L27/2436 , H01L27/2409 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/1625 , H01L45/1683
摘要： A phase changeable memory unit includes a lower electrode, an insulating interlayer structure having an opening, a phase changeable material layer and an upper electrode. The lower electrode is formed on a substrate. The insulating interlayer structure has an opening and is formed on the lower electrode and the substrate. The opening exposes the lower electrode and has a width gradually decreasing downward. The phase changeable material layer fills the opening and partially covers an upper face of the insulating interlayer structure. The upper electrode is formed on the phase changeable material layer.
摘要翻译：相变存储单元包括下电极，具有开口的绝缘层间结构，相变材料层和上电极。下电极形成在基板上。绝缘层间结构具有开口并且形成在下电极和基板上。开口露出下电极并且具有向下逐渐减小的宽度。相变材料层填充开口并部分地覆盖绝缘层间结构的上表面。上电极形成在相变材料层上。

6. 发明申请

US20090283741A1 METHOD OF FORMING A PHASE CHANGEABLE STRUCTURE 审中-公开
标题翻译：形成相位可变结构的方法
公开(公告)号：US20090283741A1
公开(公告)日：2009-11-19
申请号：US12509048
申请日：2009-07-24
申请人： Young-Soo Lim , Jun-Soo Bae
发明人： Young-Soo Lim , Jun-Soo Bae
IPC分类号： H01L47/00
CPC分类号： H01L45/1233 , H01L45/06 , H01L45/144 , H01L45/1675
摘要： The present invention relates to a method of forming a phase changeable structure wherein an upper electrode is formed on a phase changeable layer. A material including fluorine can be provided to the phase changeable layer and the upper electrode. The phase changeable layer can be etched to form a phase changeable pattern. Oxygen plasma or water vapor plasma can then be provided to the upper electrode and the phase changeable pattern.
摘要翻译：本发明涉及形成可变相结构的方法，其中上电极形成在相变层上。可以向相变层和上电极提供包含氟的材料。相变层可被蚀刻以形成相变图案。然后可以将氧等离子体或水蒸气等离子体提供给上电极和相变图案。

7. 发明授权

US08865251B2 Metal nanobelt and method of manufacturing the same, and conductive ink composition and conductive film comprising the same 有权
标题翻译：金属纳米带及其制造方法，以及导电油墨组合物及其导电膜
公开(公告)号：US08865251B2
公开(公告)日：2014-10-21
申请号：US13063656
申请日：2009-09-10
申请人： Won-Jong Kwon , Jae-Hong Kim , Sun-Mi Jin , Sang-Uck Lee , Young-Soo Lim
发明人： Won-Jong Kwon , Jae-Hong Kim , Sun-Mi Jin , Sang-Uck Lee , Young-Soo Lim
IPC分类号： H01B1/02 , B82Y40/00 , H05K1/09 , B82Y30/00 , H01B1/22 , H01L31/0224 , B82Y10/00 , B22F9/24 , H01B1/24 , B22F1/00
CPC分类号： H01B1/22 , B22F1/0018 , B22F9/24 , B22F2001/0033 , B82Y10/00 , B82Y30/00 , C09D11/52 , H01B1/24 , H01L31/022433 , H05K1/092 , H05K1/097 , H05K2201/026 , Y02E10/50 , Y10S977/762 , Y10S977/81 , Y10S977/895 , Y10S977/90 , Y10T428/12229
摘要： The present invention relates to a metal nanobelt and a method of manufacturing the same, and a conductive ink composition and a conductive film including the same. The metal nanobelt can be easily manufactured at a normal temperature and pressure without requiring the application of high temperature and pressure, and also can be used to form a conductive film or conductive pattern that exhibits excellent conductivity if the conductive ink composition including the same is printed onto a substrate before a heat treatment or a drying process is carried out at low temperature. Therefore, the metal nanobelt and the conductive ink composition may be applied very appropriately for the formation of conductive patterns or conductive films for semiconductor devices, displays, solar cells in environments requiring low temperature heating. The metal nanobelt has a length of 500 nm or more, a length/width ratio of 10 or more, and a width/thickness ratio of 3 or more.
摘要翻译：金属纳米带及其制造方法技术领域本发明涉及一种金属纳米带及其制造方法，以及导电性油墨组合物及其导电性膜。金属纳米带可以容易地在正常温度和压力下制造，而不需要施加高温和高压，并且还可以用于形成导电膜或导电图案，其导电性如果包括其的导电油墨组合物被印刷在低温下进行热处理或干燥处理之前，在基板上。因此，金属纳米带和导电油墨组合物可以非常适用于在需要低温加热的环境中形成用于半导体器件，显示器，太阳能电池的导电图案或导电膜。金属纳米带的长度为500nm以上，长宽比为10以上，宽度/厚度比为3以上。

8. 发明申请

US20120128996A1 METAL NANOBELT AND METHOD OF MANUFACTURING THE SAME, AND CONDUCTIVE INK COMPOSITION AND CONDUCTIVE FILM COMPRISING THE SAME 有权
标题翻译：金属纳米微粒及其制造方法以及导电墨水组合物和包含其的导电膜
公开(公告)号：US20120128996A1
公开(公告)日：2012-05-24
申请号：US13063656
申请日：2009-09-10
申请人： Won-Jong Kwon , Jae-Hong Kim , Sun-Mi Jin , Sang-Uck Lee , Young-Soo Lim
发明人： Won-Jong Kwon , Jae-Hong Kim , Sun-Mi Jin , Sang-Uck Lee , Young-Soo Lim
IPC分类号： B32B3/00 , H01B1/04 , B22F9/18 , H05K1/09 , H01B1/02 , B82Y30/00
CPC分类号： H01B1/22 , B22F1/0018 , B22F9/24 , B22F2001/0033 , B82Y10/00 , B82Y30/00 , C09D11/52 , H01B1/24 , H01L31/022433 , H05K1/092 , H05K1/097 , H05K2201/026 , Y02E10/50 , Y10S977/762 , Y10S977/81 , Y10S977/895 , Y10S977/90 , Y10T428/12229
摘要： The present invention relates to a metal nanobelt and a method of manufacturing the same, and a conductive ink composition and a conductive film including the same. The metal nanobelt can be easily manufactured at a normal temperature and pressure without requiring the application of high temperature and pressure, and also can be used to form a conductive film or conductive pattern that exhibits excellent conductivity if the conductive ink composition including the same is printed onto a substrate before a heat treatment or a drying process is carried out at low temperature. Therefore, the metal nanobelt and the conductive ink composition may be applied very appropriately for the formation of conductive patterns or conductive films for semiconductor devices, displays, solar cells in environments requiring low temperature heating. The metal nanobelt has a length of 500 nm or more, a length/width ratio of 10 or more, and a width/thickness ratio of 3 or more.
摘要翻译：金属纳米带及其制造方法技术领域本发明涉及一种金属纳米带及其制造方法，以及导电性油墨组合物及其导电性膜。金属纳米带可以容易地在正常温度和压力下制造，而不需要施加高温和高压，并且还可以用于形成导电膜或导电图案，其导电性如果包括其的导电油墨组合物被印刷在低温下进行热处理或干燥处理之前，在基板上。因此，金属纳米带和导电油墨组合物可以非常适用于在需要低温加热的环境中形成用于半导体器件，显示器，太阳能电池的导电图案或导电膜。金属纳米带的长度为500nm以上，长宽比为10以上，宽度/厚度比为3以上。

9. 发明授权

US07569430B2 Phase changeable structure and method of forming the same 有权
标题翻译：相变结构及其形成方法
公开(公告)号：US07569430B2
公开(公告)日：2009-08-04
申请号：US11674580
申请日：2007-02-13
申请人： Jun-Soo Bae , Hideki Horii , Ji-Hye Yi , Young-Soo Lim
发明人： Jun-Soo Bae , Hideki Horii , Ji-Hye Yi , Young-Soo Lim
IPC分类号： H01L21/82
CPC分类号： H01L45/1675 , H01L45/06 , H01L45/1233 , H01L45/144
摘要： The present invention relates to a phase changeable structure having decreased amounts of defects and a method of forming the phase changeable structure. A stacked composite is first formed by (i) forming a phase changeable layer including a chalcogenide is formed on a lower electrode, (ii) forming an etch stop layer having a first etch rate with respect to a first etching material including chlorine on the phase changeable layer, and (iii) forming a conductive layer having a second etch rate with respect to the first etching material on the etch stop layer. The conductive layer of the stacked composite is then etched using the first etching material to form an upper electrode. The etch stop layer and the phase changeable layer are then etched using a second etching material that is substantially flee of chlorine to form an etch stop pattern and a phase changeable pattern, respectively.
摘要翻译：本发明涉及具有减少的缺陷量的相变结构和形成相变结构的方法。首先通过（i）在下电极上形成包括硫族化物的相变层来形成堆叠复合体，（ii）形成相对于在相上包括氯的第一蚀刻材料具有第一蚀刻速率的蚀刻停止层可变层，和（iii）形成相对于蚀刻停止层上的第一蚀刻材料具有第二蚀刻速率的导电层。然后使用第一蚀刻材料蚀刻层叠复合体的导电层以形成上电极。然后使用基本上不含氯的第二蚀刻材料来蚀刻蚀刻停止层和相变层，以分别形成蚀刻停止图案和相变图案。

10. 发明申请

US20090017577A1 Methods of Forming Phase Change Memory Devices Having Bottom Electrodes 有权
标题翻译：形成具有底部电极的相变存储器件的方法
公开(公告)号：US20090017577A1
公开(公告)日：2009-01-15
申请号：US12170038
申请日：2008-07-09
申请人： Hyeong-Geun An , Dong-Ho Ahn , Young-Soo Lim , Yong-Ho Ha , Jun-Young Jang , Dong-Won Lim , Gyeo-Re Lee , Joon-Sang Park , Han-Bong Ko , Young-Lim Park
发明人： Hyeong-Geun An , Dong-Ho Ahn , Young-Soo Lim , Yong-Ho Ha , Jun-Young Jang , Dong-Won Lim , Gyeo-Re Lee , Joon-Sang Park , Han-Bong Ko , Young-Lim Park
IPC分类号： H01L45/00
CPC分类号： H01L45/1253 , H01L27/2409 , H01L27/2436 , H01L27/2472 , H01L45/06 , H01L45/1233 , H01L45/1273 , H01L45/141 , H01L45/16 , Y10S438/90
摘要： Phase change memory devices can have bottom patterns on a substrate. Line-shaped or L-shaped bottom electrodes can be formed in contact with respective bottom patterns on a substrate and to have top surfaces defined by dimensions in x and y axes directions on the substrate. The dimension along the x-axis of the top surface of the bottom electrodes has less width than a resolution limit of a photolithography process used to fabricate the phase change memory device. Phase change patterns can be formed in contact with the top surface of the bottom electrodes to have a greater width than each of the dimensions in the x and y axes directions of the top surface of the bottom electrodes and top electrodes can be formed on the phase change patterns, wherein the line shape or the L shape represents a sectional line shape or a sectional L shape of the bottom electrodes in the x-axis direction.
摘要翻译：相变存储器件可以在衬底上具有底部图案。线形或L形底部电极可以形成为与衬底上的相应底部图案接触并且具有由衬底上沿x和y轴方向的尺寸限定的顶表面。沿着底部电极的顶表面的x轴的尺寸比用于制造相变存储器件的光刻工艺的分辨率极限具有更小的宽度。相变图案可以形成为与底部电极的顶表面接触以具有比底部电极的顶表面的x和y轴方向上的每个尺寸更大的宽度，并且顶部电极可以形成在相位上其中线形或L形表示底部电极在x轴方向上的截面线形状或截面L形。

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