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1. 发明申请

US20090090899A1 Phase change memory device and method of manufacturing the same 有权
标题翻译：相变存储器件及其制造方法
公开(公告)号：US20090090899A1
公开(公告)日：2009-04-09
申请号：US12285531
申请日：2008-10-08
申请人： Young-Soo Lim , Yong-Sun Ko , Sung-Un Kwon , Jae-Seung Hwang
发明人： Young-Soo Lim , Yong-Sun Ko , Sung-Un Kwon , Jae-Seung Hwang
IPC分类号： H01L45/00
CPC分类号： H01L45/12 , H01L27/2436 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/1675
摘要： A method of manufacturing a phase change memory device includes forming at least one active device on a substrate, forming a bottom electrode electrically connected to the at least one active device, forming a phase change material layer and a top electrode on the bottom electrode, forming a capping layer on an upper surface of the top electrode and on side surfaces of the top electrode and phase change material layer, removing a portion of the capping layer overlapping the upper surface of the top electrode to define capping layer sidewall portions, forming an interlayer insulation film on the capping layer sidewall portions and on the top electrode, removing a portion of the interlayer insulation film from the top electrode to form a contact hole through the interlayer insulation film, and forming a contact plug in the contact hole.
摘要翻译：一种制造相变存储器件的方法包括在衬底上形成至少一个有源器件，形成与该至少一个有源器件电连接的底部电极，在底部电极上形成相变材料层和顶部电极，形成在顶部电极的上表面上以及顶部电极和相变材料层的侧表面上的覆盖层，去除与顶部电极的上表面重叠的覆盖层的一部分以限定覆盖层侧壁部分，形成中间层绝缘膜在顶盖电极上，从上电极去除一部分层间绝缘膜，以形成穿过层间绝缘膜的接触孔，并在接触孔中形成接触塞。

2. 发明授权

US07659162B2 Phase change memory device and method of manufacturing the same 有权
标题翻译：相变存储器件及其制造方法
公开(公告)号：US07659162B2
公开(公告)日：2010-02-09
申请号：US12285531
申请日：2008-10-08
申请人： Young-Soo Lim , Yong-Sun Ko , Sung-Un Kwon , Jae-Seung Hwang
发明人： Young-Soo Lim , Yong-Sun Ko , Sung-Un Kwon , Jae-Seung Hwang
IPC分类号： H01L21/8242
CPC分类号： H01L45/12 , H01L27/2436 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/1675
摘要： A method of manufacturing a phase change memory device includes forming at least one active device on a substrate, forming a bottom electrode electrically connected to the at least one active device, forming a phase change material layer and a top electrode on the bottom electrode, forming a capping layer on an upper surface of the top electrode and on side surfaces of the top electrode and phase change material layer, removing a portion of the capping layer overlapping the upper surface of the top electrode to define capping layer sidewall portions, forming an interlayer insulation film on the capping layer sidewall portions and on the top electrode, removing a portion of the interlayer insulation film from the top electrode to form a contact hole through the interlayer insulation film, and forming a contact plug in the contact hole.
摘要翻译：一种制造相变存储器件的方法包括在衬底上形成至少一个有源器件，形成与该至少一个有源器件电连接的底部电极，在底部电极上形成相变材料层和顶部电极，形成在顶部电极的上表面上和顶部电极和相变材料层的侧表面上的覆盖层，去除与顶部电极的上表面重叠的覆盖层的一部分以限定覆盖层侧壁部分，形成中间层绝缘膜在顶盖电极上，从上电极去除一部分层间绝缘膜，以形成穿过层间绝缘膜的接触孔，并在接触孔中形成接触塞。

3. 发明申请

US20060292795A1 Method of manufacturing a flash memory device 失效
标题翻译：制造闪存装置的方法
公开(公告)号：US20060292795A1
公开(公告)日：2006-12-28
申请号：US11449848
申请日：2006-06-09
申请人： Sung-Un Kwon , Yong-Sun Ko , Jae-Seung Hwang
发明人： Sung-Un Kwon , Yong-Sun Ko , Jae-Seung Hwang
IPC分类号： H01L21/336
CPC分类号： H01L27/105 , H01L27/11526 , H01L27/11534 , H01L29/66825
摘要： In a method of manufacturing a flash memory device, an insulation layer pattern is formed on a substrate having cell and peripheral regions. Trenches formed in the substrate are converted into trench structures. A tunnel oxide layer is formed on the substrate. A space between the trench structures is filled with a first conductive layer. The trench structures are removed to form trench isolation structures and to convert the first conductive layer into a first conductive layer pattern. A dielectric layer is formed on the first conductive layer patterns and the trench isolation structures. An insulation layer is formed on the substrate in the peripheral region. A third conductive layer is formed on the second conductive layer, the insulation layer and the trench isolation layers. First and second gate structures are formed in the cell region and the peripheral region, respectively.
摘要翻译：在制造闪速存储器件的方法中，在具有单元和外围区域的衬底上形成绝缘层图案。在衬底中形成的沟槽被转换为沟槽结构。在衬底上形成隧道氧化物层。沟槽结构之间的空间填充有第一导电层。去除沟槽结构以形成沟槽隔离结构并将第一导电层转换成第一导电层图案。在第一导电层图案和沟槽隔离结构上形成介电层。在周边区域的基板上形成绝缘层。在第二导电层，绝缘层和沟槽隔离层上形成第三导电层。分别在单元区域和外围区域中形成第一和第二栅极结构。

4. 发明授权

US07452773B2 Method of manufacturing a flash memory device 失效
标题翻译：制造闪存装置的方法
公开(公告)号：US07452773B2
公开(公告)日：2008-11-18
申请号：US11449848
申请日：2006-06-09
申请人： Sung-Un Kwon , Yong-Sun Ko , Jae-Seung Hwang
发明人： Sung-Un Kwon , Yong-Sun Ko , Jae-Seung Hwang
IPC分类号： H01L21/336
CPC分类号： H01L27/105 , H01L27/11526 , H01L27/11534 , H01L29/66825
摘要： In a method of manufacturing a flash memory device, an insulation layer pattern is formed on a substrate having cell and peripheral regions. Trenches formed in the substrate are converted into trench structures. A tunnel oxide layer is formed on the substrate. A space between the trench structures is filled with a first conductive layer. The trench structures are removed to form trench isolation structures and to convert the first conductive layer into a first conductive layer pattern. A dielectric layer is formed on the first conductive layer patterns and the trench isolation structures. An insulation layer is formed on the substrate in the peripheral region. A third conductive layer is formed on the second conductive layer, the insulation layer and the trench isolation layers. First and second gate structures are formed in the cell region and the peripheral region, respectively.
摘要翻译：在制造闪速存储器件的方法中，在具有单元和外围区域的衬底上形成绝缘层图案。在衬底中形成的沟槽被转换为沟槽结构。在衬底上形成隧道氧化物层。沟槽结构之间的空间填充有第一导电层。去除沟槽结构以形成沟槽隔离结构并将第一导电层转换成第一导电层图案。在第一导电层图案和沟槽隔离结构上形成介电层。在周边区域的基板上形成绝缘层。在第二导电层，绝缘层和沟槽隔离层上形成第三导电层。分别在单元区域和外围区域中形成第一和第二栅极结构。

5. 发明申请

US20070210334A1 Phase change memory device and method of fabricating the same 审中-公开
标题翻译：相变存储器件及其制造方法
公开(公告)号：US20070210334A1
公开(公告)日：2007-09-13
申请号：US11698155
申请日：2007-01-26
申请人： Young-Soo Lim , Yong-Sun Ko , Hyuk-Jin Kwon , Jae-Seung Hwang
发明人： Young-Soo Lim , Yong-Sun Ko , Hyuk-Jin Kwon , Jae-Seung Hwang
IPC分类号： H01L31/00
CPC分类号： H01L45/143 , H01L27/2436 , H01L45/06 , H01L45/126 , H01L45/144 , H01L45/1675
摘要： Example embodiments relate to a semiconductor memory device and a method of fabricating the same. Other example embodiments relate to a phase change memory device and a method of fabricating the same. There are provided a phase change memory device and a method of fabricating the same for improving or maximizing a production yield. The method comprises: after first removing a first hard mask layer used to form a contact pad electrically connected to a semiconductor substrate, forming a lower electrode to be electrically connected to the contact pad through a first contact hole in a first interlayer insulating layer formed on the contact pad and to have a thickness equal or similar to a thickness of the first interlayer insulating layer; and forming a phase change layer and an upper electrode on the lower electrode. Because change of the resistance value of the lower electrode is reduced or prevented, which has been caused due to a non-uniform thickness of a conventional first hard mask layer, a production yield may be improved.
摘要翻译：示例性实施例涉及半导体存储器件及其制造方法。其他示例性实施例涉及相变存储器件及其制造方法。提供了一种相变存储器件及其制造方法，用于改善或最大化产量。该方法包括：在首先去除用于形成与半导体衬底电连接的接触焊盘的第一硬掩模层之后，通过形成在第一层间绝缘层上的第一层间绝缘层中的第一接触孔形成下电极以与接触焊盘电连接所述接触焊盘的厚度等于或类似于所述第一层间绝缘层的厚度; 并在下电极上形成相变层和上电极。由于由于常规的第一硬掩模层的厚度不均匀而导致的下部电极的电阻值的变化被降低或防止，所以可以提高生产率。

6. 发明授权

US08158445B2 Methods of forming pattern structures and methods of manufacturing semiconductor devices using the same 有权
标题翻译：形成图案结构的方法和使用其制造半导体器件的方法
公开(公告)号：US08158445B2
公开(公告)日：2012-04-17
申请号：US12940535
申请日：2010-11-05
申请人： Yong-Hwan Ryu , Jae-Seung Hwang , Sung-Un Kwon , Kyoung-Ha Eom
发明人： Yong-Hwan Ryu , Jae-Seung Hwang , Sung-Un Kwon , Kyoung-Ha Eom
IPC分类号： H01L21/00
CPC分类号： H01L43/12 , H01L27/228 , H01L27/2409 , H01L45/06 , H01L45/144 , H01L45/1675
摘要： Methods of forming pattern structures and methods of manufacturing memory devices using the same are provided, the methods of forming pattern structures include forming an etching object layer on a substrate and performing a plasma reactive etching process on the etching object layer using an etching gas including at least ammonia (NH3) gas. The etching object layer includes a magnetic material or a phase change material.
摘要翻译：提供了形成图案结构的方法和使用其制造存储器件的方法，形成图案结构的方法包括在衬底上形成蚀刻对象层，并使用包括在蚀刻对象层上的蚀刻气体对蚀刻对象层进行等离子体反应蚀刻处理最少氨（NH 3）气。蚀刻对象层包括磁性材料或相变材料。

7. 发明申请

US20110281428A1 METHOD OF FABRICATING SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20110281428A1
公开(公告)日：2011-11-17
申请号：US13183574
申请日：2011-07-15
申请人： Yong-Hwan Ryu , Jun Seo , Eun-Young Kang , Jae-Seung Hwang , Sung-Un Kwon
发明人： Yong-Hwan Ryu , Jun Seo , Eun-Young Kang , Jae-Seung Hwang , Sung-Un Kwon
IPC分类号： H01L21/28
CPC分类号： H01L23/535 , H01L21/743 , H01L27/105 , H01L27/1052 , H01L27/11531 , H01L2924/0002 , H01L2924/00
摘要： A method of fabricating a semiconductor device in which a plurality of conductive lines having a fine pitch and a uniform thickness can be formed is provided. The method includes forming a plurality of first conductive patterns in a insulation layer as closed curves, forming a plurality of mask patterns on the insulation layer, the mask patterns exposing end portions of each of the first conductive patterns, and forming a plurality of second conductive patterns in the insulation layer as lines by removing the end portions of each of the first conductive patterns.
摘要翻译：提供一种制造半导体器件的方法，其中可以形成具有细间距和均匀厚度的多条导线。该方法包括在绝缘层中形成多个第一导电图案作为闭合曲线，在绝缘层上形成多个掩模图案，掩模图案暴露出每个第一导电图案的端部，并且形成多个第二导电通过去除每个第一导电图案的端部，将绝缘层中的图案作为线。

8. 发明授权

US08361849B2 Method of fabricating semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08361849B2
公开(公告)日：2013-01-29
申请号：US13183574
申请日：2011-07-15
申请人： Yong-Hwan Ryu , Jun Seo , Eun-Young Kang , Jae-Seung Hwang , Sung-Un Kwon
发明人： Yong-Hwan Ryu , Jun Seo , Eun-Young Kang , Jae-Seung Hwang , Sung-Un Kwon
IPC分类号： H01L21/338 , H01L21/336
CPC分类号： H01L23/535 , H01L21/743 , H01L27/105 , H01L27/1052 , H01L27/11531 , H01L2924/0002 , H01L2924/00
摘要： A method of fabricating a semiconductor device in which a plurality of conductive lines having a fine pitch and a uniform thickness can be formed is provided. The method includes forming a plurality of first conductive patterns in a insulation layer as closed curves, forming a plurality of mask patterns on the insulation layer, the mask patterns exposing end portions of each of the first conductive patterns, and forming a plurality of second conductive patterns in the insulation layer as lines by removing the end portions of each of the first conductive patterns.
摘要翻译：提供一种制造半导体器件的方法，其中可以形成具有细间距和均匀厚度的多条导线。该方法包括在绝缘层中形成多个第一导电图案作为闭合曲线，在绝缘层上形成多个掩模图案，掩模图案暴露出每个第一导电图案的端部，并且形成多个第二导电通过去除每个第一导电图案的端部，将绝缘层中的图案作为线。

9. 发明申请

US20070004140A1 Method of manufacturing a non-volatile semiconductor memory device 审中-公开
标题翻译：制造非易失性半导体存储器件的方法
公开(公告)号：US20070004140A1
公开(公告)日：2007-01-04
申请号：US11475153
申请日：2006-06-27
申请人： Dae-Hyun Jang , Jae-Seung Hwang , Dae-Youp Lee , Sung-Un Kwon
发明人： Dae-Hyun Jang , Jae-Seung Hwang , Dae-Youp Lee , Sung-Un Kwon
IPC分类号： H01L21/336 , H01L29/76
CPC分类号： H01L27/105 , H01L27/11526 , H01L27/11534 , H01L29/665 , H01L29/6659 , H01L29/7833
摘要： In a method of manufacturing a non-volatile semiconductor memory device that includes a first region having a first gate structure and a second region having a second gate structure, the first gate structure may include a tunnel oxide layer pattern, a first conductive layer pattern, a dielectric layer pattern and a second conductive layer pattern. A first photoresist pattern may be formed on the second conductive layer pattern to form a source line which may be formed in a region of the first area by implanting impurities. A second photoresist pattern may be formed on a hard mask layer in the second region of the substrate to form a hard mask pattern on a third conductive layer. The second gate structure having substantially vertical sidewalls may be formed in the second area by etching the third conductive layer using the hard mask pattern.
摘要翻译：在制造包括具有第一栅极结构的第一区域和具有第二栅极结构的第二区域的非易失性半导体存储器件的方法中，第一栅极结构可以包括隧道氧化物层图案，第一导电层图案，电介质层图案和第二导电层图案。第一光致抗蚀剂图案可以形成在第二导电层图案上以形成可以通过注入杂质形成在第一区域的区域中的源极线。可以在基板的第二区域中的硬掩模层上形成第二光致抗蚀剂图案，以在第三导电层上形成硬掩模图案。具有基本垂直侧壁的第二栅极结构可以通过使用硬掩模图案蚀刻第三导电层而形成在第二区域中。

10. 发明授权

US07989279B2 Method of fabricating semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US07989279B2
公开(公告)日：2011-08-02
申请号：US12136626
申请日：2008-06-10
申请人： Yong-Hwan Ryu , Jun Seo , Eun-Young Kang , Jae-Seung Hwang , Sung-Un Kwon
发明人： Yong-Hwan Ryu , Jun Seo , Eun-Young Kang , Jae-Seung Hwang , Sung-Un Kwon
IPC分类号： H01L21/338 , H01L21/336
CPC分类号： H01L23/535 , H01L21/743 , H01L27/105 , H01L27/1052 , H01L27/11531 , H01L2924/0002 , H01L2924/00
摘要： A method of fabricating a semiconductor device in which a plurality of conductive lines having a fine pitch and a uniform thickness can be formed is provided. The method includes forming a plurality of first conductive patterns in a insulation layer as closed curves, forming a plurality of mask patterns on the insulation layer, the mask patterns exposing end portions of each of the first conductive patterns, and forming a plurality of second conductive patterns in the insulation layer as lines by removing the end portions of each of the first conductive patterns.
摘要翻译：提供一种制造半导体器件的方法，其中可以形成具有细间距和均匀厚度的多条导线。该方法包括在绝缘层中形成多个第一导电图案作为闭合曲线，在绝缘层上形成多个掩模图案，掩模图案暴露出每个第一导电图案的端部，并且形成多个第二导电通过去除每个第一导电图案的端部，将绝缘层中的图案作为线。

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