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1. 发明申请

US20100144138A1 METHODS OF FORMING CONTACT STRUCTURES AND SEMICONDUCTOR DEVICES FABRICATED USING CONTACT STRUCTURES 有权
标题翻译：形成接触结构的方法和使用接触结构织造的半导体器件
公开(公告)号：US20100144138A1
公开(公告)日：2010-06-10
申请号：US12627810
申请日：2009-11-30
申请人： Young-Lim Park , Hyeong-Geun An , Gyu-Hwan Oh , Dong-Ho Ahn , Jin-Il Lee
发明人： Young-Lim Park , Hyeong-Geun An , Gyu-Hwan Oh , Dong-Ho Ahn , Jin-Il Lee
IPC分类号： H01L21/768
CPC分类号： H01L21/76816 , H01L27/24
摘要： Provided are methods of forming contact structures and semiconductor devices fabricated using the contact structures. The formation of a contact structure can include forming a first molding pattern on a substrate, forming an insulating layer to cover at least a sidewall of the first molding pattern, forming a second molding pattern to cover a sidewall of the insulating layer and spaced apart from the first molding pattern, removing a portion of the insulating layer between the first and second molding patterns to form a hole, and forming an insulating pattern between the first and second molding patterns, and forming a contact pattern in the hole.
摘要翻译：提供了形成使用接触结构制造的接触结构和半导体器件的方法。接触结构的形成可以包括在基底上形成第一模制图案，形成绝缘层以覆盖至少第一模制图案的侧壁，形成第二模制图案以覆盖绝缘层的侧壁并与第一模制图案，去除第一和第二模制图案之间的绝缘层的一部分以形成孔，并且在第一和第二模制图案之间形成绝缘图案，并在孔中形成接触图案。

2. 发明授权

US08021977B2 Methods of forming contact structures and semiconductor devices fabricated using contact structures 有权
标题翻译：形成接触结构的方法和使用接触结构制造的半导体器件
公开(公告)号：US08021977B2
公开(公告)日：2011-09-20
申请号：US12627810
申请日：2009-11-30
申请人： Young-Lim Park , Hyeong-Geun An , Gyu-Hwan Oh , Dong-Ho Ahn , Jin-Il Lee
发明人： Young-Lim Park , Hyeong-Geun An , Gyu-Hwan Oh , Dong-Ho Ahn , Jin-Il Lee
IPC分类号： H01L21/4763 , H01L21/768
CPC分类号： H01L21/76816 , H01L27/24
摘要： Provided are methods of forming contact structures and semiconductor devices fabricated using the contact structures. The formation of a contact structure can include forming a first molding pattern on a substrate, forming an insulating layer to cover at least a sidewall of the first molding pattern, forming a second molding pattern to cover a sidewall of the insulating layer and spaced apart from the first molding pattern, removing a portion of the insulating layer between the first and second molding patterns to form a hole, and forming an insulating pattern between the first and second molding patterns, and forming a contact pattern in the hole.
摘要翻译：提供了形成使用接触结构制造的接触结构和半导体器件的方法。接触结构的形成可以包括在基底上形成第一模制图案，形成绝缘层以覆盖至少第一模制图案的侧壁，形成第二模制图案以覆盖绝缘层的侧壁并与第一模制图案，去除第一和第二模制图案之间的绝缘层的一部分以形成孔，并且在第一和第二模制图案之间形成绝缘图案，并在孔中形成接触图案。

3. 发明申请

US20100093130A1 Methods of forming multi-level cell of semiconductor memory 有权
标题翻译：形成半导体存储器多级单元的方法
公开(公告)号：US20100093130A1
公开(公告)日：2010-04-15
申请号：US12587772
申请日：2009-10-13
申请人： Gyu-Hwan Oh , Hyeong-Geun An , Soon-Oh Park , Dong-Ho Ahn , Young-Lim Park
发明人： Gyu-Hwan Oh , Hyeong-Geun An , Soon-Oh Park , Dong-Ho Ahn , Young-Lim Park
IPC分类号： H01L21/06
CPC分类号： H01L45/141 , H01L27/2409 , H01L45/06 , H01L45/1233 , H01L45/1253 , H01L45/144 , H01L45/1666 , H01L45/1683
摘要： Provided is a method of forming a semiconductor memory cell in which in order to store two bits or more data in a memory cell, three or more bottom electrode contacts (BECs) and phase-change materials (GST) have a parallel structure on a single contact plug (CP) and set resistances are changed depending on thicknesses (S), lengths (L) or resistivities (ρ) of the three or more bottom electrode contacts, so that a reset resistance and three different set resistances enable data other than in set and reset states to be stored. Also, a method of forming a memory cell in which three or more phase-change materials (GST) have a parallel structure on a single bottom electrode contact, and the phase-change materials have different set resistances depending on composition ratio or type, so that four or more different resistances can be implemented is provided.
摘要翻译：提供了一种形成半导体存储单元的方法，其中为了在存储单元中存储两个或更多个数据，三个或更多个底部电极触点（BEC）和相变材料（GST）在单个存储单元上具有并联结构接触插头（CP）和设定电阻根据三个或更多个底部电极触点的厚度（S），长度（L）或电阻率（＆rgr）而改变，因此复位电阻和三种不同的设定电阻使数据不能在设置和复位状态下存储。此外，形成其中三个或更多个相变材料（GST）在单个底部电极接触上具有平行结构的存储单元的方法，并且相变材料根据组成比或类型具有不同的设定电阻，因此可以实现四个或更多个不同的电阻。

4. 发明授权

US08187918B2 Methods of forming multi-level cell of semiconductor memory 有权
标题翻译：形成半导体存储器多级单元的方法
公开(公告)号：US08187918B2
公开(公告)日：2012-05-29
申请号：US12587772
申请日：2009-10-13
申请人： Gyu-Hwan Oh , Hyeung-Geun An , Soon-Oh Park , Dong-Ho Ahn , Young-Lim Park
发明人： Gyu-Hwan Oh , Hyeung-Geun An , Soon-Oh Park , Dong-Ho Ahn , Young-Lim Park
IPC分类号： H01L21/06
CPC分类号： H01L45/141 , H01L27/2409 , H01L45/06 , H01L45/1233 , H01L45/1253 , H01L45/144 , H01L45/1666 , H01L45/1683
摘要： Provided is a method of forming a semiconductor memory cell in which in order to store two bits or more data in a memory cell, three or more bottom electrode contacts (BECs) and phase-change materials (GST) have a parallel structure on a single contact plug (CP) and set resistances are changed depending on thicknesses (S), lengths (L) or resistivities (ρ) of the three or more bottom electrode contacts, so that a reset resistance and three different set resistances enable data other than in set and reset states to be stored. Also, a method of forming a memory cell in which three or more phase-change materials (GST) have a parallel structure on a single bottom electrode contact, and the phase-change materials have different set resistances depending on composition ratio or type, so that four or more different resistances can be implemented is provided.
摘要翻译：提供了一种形成半导体存储单元的方法，其中为了在存储单元中存储两个或更多个数据，三个或更多个底部电极触点（BEC）和相变材料（GST）在单个存储单元上具有并联结构接触插头（CP）和设定电阻根据三个或更多个底部电极触点的厚度（S），长度（L）或电阻率（＆rgr）而改变，因此复位电阻和三种不同的设定电阻使数据不能在设置和复位状态下存储。此外，形成其中三个或更多个相变材料（GST）在单个底部电极接触上具有平行结构的存储单元的方法，并且相变材料根据组成比或类型具有不同的设定电阻，因此可以实现四个或更多个不同的电阻。

5. 发明授权

US08133758B2 Method of fabricating phase-change memory device having TiC layer 有权
标题翻译：具有TiC层的相变存储器件的制造方法
公开(公告)号：US08133758B2
公开(公告)日：2012-03-13
申请号：US12623513
申请日：2009-11-23
申请人： Gyu-Hwan Oh , Young-Lim Park , Soon-Oh Park , Jin-Il Lee , Chang-Su Kim
发明人： Gyu-Hwan Oh , Young-Lim Park , Soon-Oh Park , Jin-Il Lee , Chang-Su Kim
IPC分类号： H01L21/00
CPC分类号： H01L45/124 , C23C16/32 , C23C16/45523 , H01L27/2409 , H01L27/2463 , H01L45/06 , H01L45/126 , H01L45/144 , H01L45/148 , H01L45/16 , H01L45/1666
摘要： Provided is a method of fabricating a phase-change memory device. The phase-change memory device includes a memory cell having a switching device and a phase change pattern. The method includes; forming a TiC layer on a contact electrically connecting the switching device using a plasma enhanced cyclic chemical vapor deposition (PE-cyclic CVD) process, patterning the TiC layer to form a lower electrode on the contact, and forming the phase-change pattern on the lower electrode.
摘要翻译：提供一种制造相变存储器件的方法。相变存储器件包括具有开关器件和相变模式的存储器单元。该方法包括：在使用等离子体增强循环化学气相沉积（PE循环CVD）工艺电连接开关装置的触点上形成TiC层，图案化TiC层以在触点上形成下电极，并在下电极。

6. 发明授权

US08830739B2 Non-volatile memory device having multi-level cells and method of forming the same 有权
标题翻译：具有多电平电池的非易失性存储器件及其形成方法
公开(公告)号：US08830739B2
公开(公告)日：2014-09-09
申请号：US13791970
申请日：2013-03-09
申请人： Gyu-Hwan Oh
发明人： Gyu-Hwan Oh
IPC分类号： G11C11/00 , H01L27/24 , H01L45/00 , G11C11/56 , G11C13/00
CPC分类号： H01L45/1233 , G11C11/5678 , G11C13/0004 , G11C13/0069 , H01L27/2409 , H01L27/2463 , H01L45/04 , H01L45/06 , H01L45/126 , H01L45/1273 , H01L45/141 , H01L45/143 , H01L45/144 , H01L45/1683
摘要： A non-volatile memory device including multi-level cells is provided. The device includes first and second conductive patterns. Additionally, the device includes an electrode structure and a data storage pattern between the first and second conductive patterns. The data storage pattern may include a phase change material and a first vertical thickness of a first portion of the data storage pattern may be less than a second vertical thickness of a second portion of the data storage pattern. The electrode structure may include first and second electrodes and a vertical thickness of the first electrode may be greater than that of the second electrode.
摘要翻译：提供了包括多级单元的非易失性存储器件。该装置包括第一和第二导电图案。另外，该装置包括在第一和第二导电图案之间的电极结构和数据存储图案。数据存储图案可以包括相变材料，并且数据存储图案的第一部分的第一垂直厚度可以小于数据存储图案的第二部分的第二垂直厚度。电极结构可以包括第一和第二电极，并且第一电极的垂直厚度可以大于第二电极的垂直厚度。

7. 发明申请

US20120252187A1 Semiconductor Device and Method of Manufacturing the Same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20120252187A1
公开(公告)日：2012-10-04
申请号：US13422487
申请日：2012-03-16
申请人： Gyu-Hwan Oh , Dong-Hyun Kim , Kyung-Min Chung , Dong-Hyun Im
发明人： Gyu-Hwan Oh , Dong-Hyun Kim , Kyung-Min Chung , Dong-Hyun Im
IPC分类号： H01L21/329 , H01L21/283 , H01L21/02
CPC分类号： H01L27/1021 , H01L27/2409 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/1253 , H01L45/16 , H01L45/1683
摘要： A method of manufacturing the semiconductor device includes sequentially forming first to third mold layer patterns on a substrate and spaced apart from each other , forming a first semiconductor pattern between the first mold layer pattern and the second mold layer pattern, and a second semiconductor pattern between the second mold layer pattern and the third mold layer pattern, forming a first trench between the first mold layer pattern and the third mold layer pattern by removing a portion of the second mold layer pattern and portions of the first and second semiconductor patterns, depositing a material for a lower electrode conformally along side and bottom surfaces of the first trench, and forming first and second lower electrodes separated from each other on the first and second semiconductor patterns, respectively, by removing a portion of the material for a lower electrode positioned on the second mold layer pattern.
摘要翻译：制造半导体器件的方法包括在基片上依次形成第一至第三模层图案并彼此分开，在第一模层图案和第二模层图案之间形成第一半导体图案，以及第二半导体图案，第二模层图案和第三模层图案，通过去除第二模层图案的一部分和第一和第二半导体图案的部分，在第一模层图案和第三模层图案之间形成第一沟槽，用于下电极的材料沿着第一沟槽的侧表面和底表面共形地形成，并且通过移除位于第一和第二半导体图案上的下电极的材料的一部分，分别形成在第一和第二半导体图案上彼此分离的第一和第二下电极第二模层图案。

8. 发明申请

US20120040508A1 Method of Forming Semiconductor Device Having Self-Aligned Plug 有权
标题翻译：形成具有自对准插头的半导体器件的方法
公开(公告)号：US20120040508A1
公开(公告)日：2012-02-16
申请号：US13188981
申请日：2011-07-22
申请人： Gyu-Hwan Oh , Sung-Lae Cho , Byoung-Jae Bae , Ik-Soo Kim , Dong-Hyun Im , Doo-Hwan Park , Kyoung-Ha Eom , Sung-Un Kwon , Chul-Ho Shin , Sang-Sup Jeong
发明人： Gyu-Hwan Oh , Sung-Lae Cho , Byoung-Jae Bae , Ik-Soo Kim , Dong-Hyun Im , Doo-Hwan Park , Kyoung-Ha Eom , Sung-Un Kwon , Chul-Ho Shin , Sang-Sup Jeong
IPC分类号： H01L47/00
CPC分类号： H01L45/1683 , H01L27/2463 , H01L45/06
摘要： A conductive pattern on a substrate is formed. An insulating layer having an opening exposing the conductive pattern is formed. A bottom electrode is formed on the conductive pattern and a first sidewall of the opening. A spacer is formed on the bottom electrode and a second sidewall of the opening. The spacer and the bottom electrode are formed to be lower than a top surface of the insulating layer. A data storage plug is formed on the bottom electrode and the spacer. The data storage plug has a first sidewall aligned with a sidewall of the bottom electrode and a second sidewall aligned with a sidewall of the spacer. A bit line is formed on the data storage plug.
摘要翻译：形成基板上的导电图案。形成具有露出导电图案的开口的绝缘层。底部电极形成在导电图案和开口的第一侧壁上。在底部电极和开口的第二侧壁上形成间隔物。间隔件和底部电极形成为低于绝缘层的顶表面。数据存储插头形成在底部电极和间隔件上。数据存储插头具有与底部电极的侧壁对准的第一侧壁和与间隔件的侧壁对准的第二侧壁。在数据存储插头上形成位线。

9. 发明授权

US07759159B2 Variable resistance non-volatile memory cells and methods of fabricating same 有权
标题翻译：可变电阻非易失性存储单元及其制造方法
公开(公告)号：US07759159B2
公开(公告)日：2010-07-20
申请号：US11848379
申请日：2007-08-31
申请人： Gyu-Hwan Oh , Shin-Jae Kang , In-Sun Park , Hyun-Seok Lim , Nak-Hyun Lim , Hyun-Suk Lee
发明人： Gyu-Hwan Oh , Shin-Jae Kang , In-Sun Park , Hyun-Seok Lim , Nak-Hyun Lim , Hyun-Suk Lee
IPC分类号： H01L21/00 , H01L21/20 , H01L47/00 , H01L21/02
CPC分类号： H01L45/06 , G11C13/0004 , H01L27/2409 , H01L27/2436 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/16
摘要： Methods of fabricating integrated circuit memory cells and integrated circuit memory cells are disclosed. An integrated circuit memory cell can be fabricated by forming an ohmic layer on an upper surface of a conductive structure and extending away from the structure along at least a portion of a sidewall of an opening in an insulation layer. An electrode layer is formed on the ohmic layer. A variable resistivity material is formed on the insulation layer and electrically connected to the electrode layer.
摘要翻译：公开了制造集成电路存储单元和集成电路存储单元的方法。可以通过在导电结构的上表面上形成欧姆层并沿着绝缘层中的开口的侧壁的至少一部分远离结构延伸来制造集成电路存储单元。在欧姆层上形成电极层。在绝缘层上形成可变电阻率材料并与电极层电连接。

10. 发明授权

US09196827B2 Non-volatile memory devices having dual heater configurations and methods of fabricating the same 有权
标题翻译：具有双重加热器配置的非易失性存储器件及其制造方法
公开(公告)号：US09196827B2
公开(公告)日：2015-11-24
申请号：US13547663
申请日：2012-07-12
申请人： Gyu-Hwan Oh , Doo-Hwan Park , Young-Kuk Kim
发明人： Gyu-Hwan Oh , Doo-Hwan Park , Young-Kuk Kim
IPC分类号： H05B3/00 , H01L45/00 , H05B3/14 , H01L27/02 , H01L27/102 , H01L27/24
CPC分类号： H01L45/1233 , H01L27/0296 , H01L27/1021 , H01L27/2409 , H01L45/06 , H01L45/1246 , H01L45/126 , H01L45/144 , H01L45/145 , H01L45/1683 , H05B3/141
摘要： A non-volatile memory device includes a data storage structure coupled between first and second conductive lines of the memory device. The data storage structure includes a conductive lower heater element, a data storage pattern, and a conductive upper heater element sequentially stacked. At least one sidewall surface of the data storage pattern is coplanar with a sidewall surface of the upper heater element thereabove and a sidewall surface of the lower heater element therebelow. Related fabrication methods are also discussed.
摘要翻译：非易失性存储器件包括耦合在存储器件的第一和第二导线之间的数据存储结构。数据存储结构包括依次堆叠的导电下加热器元件，数据存储模式和导电上加热器元件。数据存储图案的至少一个侧壁表面与上述上加热器元件的侧壁表面和下加热器元件的侧壁表面共面。还讨论了相关的制造方法。

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