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1. 发明授权

US07795086B2 Method of manufacturing semiconductor device using salicide process 失效
标题翻译：使用自对准硅胶工艺制造半导体器件的方法
公开(公告)号：US07795086B2
公开(公告)日：2010-09-14
申请号：US12346011
申请日：2008-12-30
申请人： Young Jin Lee , Dong Sun Sheen , Seok Pyo Song , Mi Ri Lee , Chi Ho Kim , Gil Jae Park , Bo Min Seo
发明人： Young Jin Lee , Dong Sun Sheen , Seok Pyo Song , Mi Ri Lee , Chi Ho Kim , Gil Jae Park , Bo Min Seo
IPC分类号： H01L21/8238
CPC分类号： H01L21/823814 , H01L21/823425 , H01L21/823835
摘要： A method for manufacturing a semiconductor device using a salicide process, which includes forming a gate dielectric layer over a silicon substrate including a PMOS region and an NMOS region; forming a first silicon pattern in the NMOS region and a second silicon pattern in the PMOS region; forming a first metal layer that is in contact with the first silicon pattern and the exposed first portion of the silicon substrate; and forming a first gate, a first junction, a second gate, and a second junction by performing a heat treatment to silicify the respective first and second silicon patterns and the silicon substrate.
摘要翻译：一种使用自对准硅化物工艺制造半导体器件的方法，包括在包括PMOS区域和NMOS区域的硅衬底上形成栅极电介质层; 在所述NMOS区域中形成第一硅图案和在所述PMOS区域中形成第二硅图案; 形成与所述第一硅图案和所述暴露的所述硅衬底的第一部分接触的第一金属层; 以及通过进行热处理以使相应的第一和第二硅图案和硅衬底硅化而形成第一栅极，第一结，第二栅极和第二结。

2. 发明申请

US20090186456A1 Method of Manufacturing Semiconductor Device using Salicide Process 失效
标题翻译：使用杀菌剂工艺制造半导体器件的方法
公开(公告)号：US20090186456A1
公开(公告)日：2009-07-23
申请号：US12346011
申请日：2008-12-30
申请人： Young Jin Lee , Dong Sun Sheen , Seok Pyo Song , Mi Ri Lee , Chi Ho Kim , Gil Jae Park , Bo Min Seo
发明人： Young Jin Lee , Dong Sun Sheen , Seok Pyo Song , Mi Ri Lee , Chi Ho Kim , Gil Jae Park , Bo Min Seo
IPC分类号： H01L21/8238
CPC分类号： H01L21/823814 , H01L21/823425 , H01L21/823835
摘要： A method for manufacturing a semiconductor device using a salicide process, which includes forming a gate dielectric layer over a silicon substrate including a PMOS region and an NMOS region; forming a first silicon pattern in the NMOS region and a second silicon pattern in the PMOS region; forming a first metal layer that is in contact with the first silicon pattern and the exposed first portion of the silicon substrate; and forming a first gate, a first junction, a second gate, and a second junction by performing a heat treatment to silicify the respective first and second silicon patterns and the silicon substrate.
摘要翻译：一种使用自对准硅化物工艺制造半导体器件的方法，包括在包括PMOS区域和NMOS区域的硅衬底上形成栅极电介质层; 在所述NMOS区域中形成第一硅图案和在所述PMOS区域中形成第二硅图案; 形成与所述第一硅图案和所述暴露的所述硅衬底的第一部分接触的第一金属层; 以及通过进行热处理以使相应的第一和第二硅图案和硅衬底硅化而形成第一栅极，第一结，第二栅极和第二结。

3. 发明授权

US07585730B1 Method of fabricating a non-volatile memory device 失效
标题翻译：制造非易失性存储器件的方法
公开(公告)号：US07585730B1
公开(公告)日：2009-09-08
申请号：US12164721
申请日：2008-06-30
申请人： Seok Pyo Song , Dong Sun Sheen , Young Jin Lee , Mi Ri Lee , Chi Ho Kim , Gil Jae Park , Bo Min Seo
发明人： Seok Pyo Song , Dong Sun Sheen , Young Jin Lee , Mi Ri Lee , Chi Ho Kim , Gil Jae Park , Bo Min Seo
IPC分类号： H01L21/8247
CPC分类号： H01L29/7881 , H01L21/28273 , H01L27/115 , H01L27/11521 , H01L29/42324
摘要： A method of fabricating a non-volatile memory device includes forming a tunneling layer and a conductive layer on a semiconductor substrate, and patterning the conductive layer, the tunneling layer, and the semiconductor substrate to form a conductive pattern, a tunneling pattern, and a trench in the semiconductor substrate. The method also includes filling the trench with a insulating material, and exposing a partial sidewall of the conductive pattern. The method further includes recessing the exposed partial sidewall of the conductive pattern in an inward direction to form a floating gate. The floating gate includes a base portion and a protruding portion having a width smaller than that of the base portion. The method also includes etching the insulating layer to form an isolation layer that exposes the base portion of the floating gate. Still further, the method includes forming a dielectric layer, that extends along the base and protruding portions of the floating gate, and a control gate that covers the base and protruding portions of the floating gate.
摘要翻译：一种制造非易失性存储器件的方法包括在半导体衬底上形成隧道层和导电层，并且对导电层，隧道层和半导体衬底进行构图以形成导电图案，隧道图案和沟槽在半导体衬底中。该方法还包括用绝缘材料填充沟槽，以及暴露导电图案的部分侧壁。该方法还包括将导电图案的暴露部分侧壁向内凹入以形成浮动栅极。浮动门包括基部和具有小于基部的宽度的突出部分。该方法还包括蚀刻绝缘层以形成暴露浮动栅极的基部的隔离层。此外，该方法包括形成沿着基极延伸的电介质层和浮动栅极的突出部分，以及覆盖浮动栅极的基部和突出部分的控制栅极。

4. 发明申请

US20090163013A1 Method for Forming Gate of Non-Volatile Memory Device 审中-公开
标题翻译：非易失性存储器件门形成方法
公开(公告)号：US20090163013A1
公开(公告)日：2009-06-25
申请号：US12131558
申请日：2008-06-02
申请人： Seok Pyo Song , Dong Sun Sheen , Seung Ho Pyi , Ki Seon Park , Sun Hwan Hwang , Mi Ri Lee , Gil Jae Park
发明人： Seok Pyo Song , Dong Sun Sheen , Seung Ho Pyi , Ki Seon Park , Sun Hwan Hwang , Mi Ri Lee , Gil Jae Park
IPC分类号： H01L21/28
CPC分类号： H01L27/11568 , H01L27/115 , H01L27/11521
摘要： Provided is a method for forming a gate of a non-volatile memory device. A tunneling layer, a charge trapping layer, a blocking layer, and a control gate layer are formed on a semiconductor substrate. A hard mask is formed on the control gate layer. The hard mask defines a region on which a gate is formed. A gate pattern is formed by etching the control gate layer, the blocking layer, the charge trapping layer, and the tunneling layer. A damage compensation layer on a side of the gate pattern is formed using ultra low pressure plasma of a pressure range from approximately 1 mT to approximately 100 mT.
摘要翻译：提供了一种用于形成非易失性存储器件的栅极的方法。在半导体衬底上形成隧道层，电荷俘获层，阻挡层和控制栅极层。在控制栅极层上形成硬掩膜。硬掩模限定形成栅极的区域。通过蚀刻控制栅极层，阻挡层，电荷俘获层和隧道层形成栅极图案。使用压力范围为约1mT至约100mT的超低压等离子体形成栅极图案侧的损伤补偿层。

5. 发明授权

US07687371B2 Method of forming isolation structure of semiconductor device for preventing excessive loss during recess gate formation 失效
标题翻译：形成半导体器件的隔离结构的方法，用于防止在凹陷栅极形成期间的过度损耗
公开(公告)号：US07687371B2
公开(公告)日：2010-03-30
申请号：US12243133
申请日：2008-10-01
申请人： Dong Sun Sheen , Seok Pyo Song , Sang Tae Ahn , Hyeon Ju An
发明人： Dong Sun Sheen , Seok Pyo Song , Sang Tae Ahn , Hyeon Ju An
IPC分类号： H01L21/76
CPC分类号： H01L21/76224
摘要： An isolation structure of a semiconductor device is formed by forming a hard mask layer on a semiconductor substrate having active and field regions to expose the field region. A trench is defined by etching the exposed field region of the semiconductor substrate using the hard mask as an etch mask. An SOG layer is formed in the trench partially filling the trench. An amorphous aluminum oxide layer is formed on the resultant substrate including the SOG layer. An HDP layer is formed on the amorphous aluminum oxide layer to completely fill the trench. The HDP layer and the amorphous aluminum oxide layer are subjected to CMP to expose the hard mask. The hard mask and portions of the amorphous aluminum oxide layer that are formed on the HDP layer are removed. The amorphous aluminum oxide layer is crystallized.
摘要翻译：半导体器件的隔离结构通过在具有活性和场区域的半导体衬底上形成硬掩模层以暴露场区而形成。通过使用硬掩模作为蚀刻掩模蚀刻半导体衬底的曝光场区来限定沟槽。 SOG层形成在部分填充沟槽的沟槽中。在包含SOG层的所得基板上形成无定形氧化铝层。在无定形氧化铝层上形成HDP层以完全填充沟槽。对HDP层和无定形氧化铝层进行CMP以暴露硬掩模。去除形成在HDP层上的硬掩模和无定形氧化铝层的部分。无定形氧化铝层结晶。

6. 发明授权

US07687355B2 Method for manufacturing fin transistor that prevents etching loss of a spin-on-glass insulation layer 失效
标题翻译：用于制造防止玻璃化玻璃绝缘层的蚀刻损失的鳍式晶体管的方法
公开(公告)号：US07687355B2
公开(公告)日：2010-03-30
申请号：US11965835
申请日：2007-12-28
申请人： Dong Sun Sheen , Seok Pyo Song , Young Ho Lee
发明人： Dong Sun Sheen , Seok Pyo Song , Young Ho Lee
IPC分类号： H01L21/336
CPC分类号： H01L29/66795 , H01L29/7851
摘要： A method for manufacturing a fin transistor includes forming a trench by etching a semiconductor substrate. A flowable insulation layer is filled in the trench to form a field insulation layer defining an active region. The portion of the flowable insulation layer coming into contact with a gate forming region is etched so as to protrude the gate forming region in the active region. A protective layer over the semiconductor substrate is formed to fill the portion of the etched flowable insulation layer. The portion of the protective layer formed over the active region is removed to expose the active region of the semiconductor substrate. The exposed active region of the semiconductor substrate is cleaned. The protective layer remaining on the portion of the etched flowable insulation layer is removed. Gates are formed over the protruded gate forming regions in the active region.
摘要翻译：一种制造鳍式晶体管的方法包括：通过蚀刻半导体衬底形成沟槽。可流动的绝缘层填充在沟槽中以形成限定有源区的场绝缘层。与栅极形成区域接触的可流动绝缘层的部分被蚀刻以便在有源区域中突出栅极形成区域。形成半导体衬底上方的保护层以填充该可蚀刻的可流动绝缘层的部分。在有源区上形成的保护层的部分被去除以暴露半导体衬底的有源区。清洁半导体衬底的暴露的有源区。残留在可蚀刻的可流动绝缘层的部分上的保护层被去除。在活性区域中的突出的栅极形成区域上形成栅极。

7. 发明申请

US20090170283A1 Method of Fabricating Non-Volatile Memory Device 失效
标题翻译：制造非易失性存储器件的方法
公开(公告)号：US20090170283A1
公开(公告)日：2009-07-02
申请号：US12164879
申请日：2008-06-30
申请人： Dong Sun Sheen , Seok Pyo Song
发明人： Dong Sun Sheen , Seok Pyo Song
IPC分类号： H01L21/762 , H01L21/28
CPC分类号： H01L21/76232 , H01L27/11521
摘要： A method of fabricating a non-volatile memory device, A tunnel insulating layer, a floating gate, and a pad nitride layer is formed on a semiconductor substrate. A isolation region of the semiconductor substrate is formed by etching to a predetermined depth, and a liner insulating layer is formed on an entire surface of the resulting trench for device isolation. A filling insulation layer is formed on the liner insulating layer to fill the trench and a first etching process is performed on the filling insulation layer and the liner insulating layer. The surface of semiconductor is recessed by performing a second etching process on the filling insulation layer. A capping layer is formed on an entire surface of the result formed by the second etching process. The device isolation layer of a concave shape is formed by performing an etching process on the capping layer.
摘要翻译：一种制造非易失性存储器件的方法，在半导体衬底上形成隧道绝缘层，浮栅和衬垫氮化物层。通过蚀刻到预定深度形成半导体衬底的隔离区域，并且在所形成的用于器件隔离的沟槽的整个表面上形成衬垫绝缘层。填充绝缘层形成在衬垫绝缘层上以填充沟槽，并且在填充绝缘层和衬里绝缘层上执行第一蚀刻工艺。通过对填充绝缘层进行第二蚀刻工艺来使半导体的表面凹陷。在通过第二蚀刻工艺形成的结果的整个表面上形成覆盖层。通过对封盖层进行蚀刻工艺来形成凹形的器件隔离层。

8. 发明授权

US07687362B2 Semiconductor device with increased channel length and width and method for manufacturing the same 失效
标题翻译：具有增加的通道长度和宽度的半导体器件及其制造方法
公开(公告)号：US07687362B2
公开(公告)日：2010-03-30
申请号：US11941194
申请日：2007-11-16
申请人： Seok Pyo Song , Dong Sun Sheen , Young Ho Lee
发明人： Seok Pyo Song , Dong Sun Sheen , Young Ho Lee
IPC分类号： H01L29/78
CPC分类号： H01L29/66621 , H01L29/4236
摘要： A semiconductor device includes a semiconductor substrate having an active region including a channel portion. An isolation layer is formed in the semiconductor substrate to define the active region, and a gate is formed over the channel portion in the active region. The active region of the semiconductor substrate is etched to such that the entire active region is below an upper surface of the isolation layer. A U-shaped groove is formed in the channel portion of the active region, except the edges in a direction of the channel width thereof, in order to increase the channel width. In the semiconductor device, there is an increase in channel length and channel width leading to a reduction in leakage current and on increase in operation current.
摘要翻译：半导体器件包括具有包括沟道部分的有源区的半导体衬底。在半导体衬底中形成隔离层以限定有源区，并且在有源区中的沟道部分之上形成栅极。蚀刻半导体衬底的有源区，使得整个有源区在隔离层的上表面下方。为了增加通道宽度，在活性区域的通道部分中形成U形槽，除了其通道宽度方向上的边缘之外。在半导体器件中，通道长度和通道宽度增加，导致漏电流的减小和工作电流的增加。

9. 发明授权

US07563654B2 Method of manufacturing semiconductor device for formation of pin transistor 有权
标题翻译：用于形成pin晶体管的半导体器件的制造方法
公开(公告)号：US07563654B2
公开(公告)日：2009-07-21
申请号：US11647759
申请日：2006-12-29
申请人： Dong Sun Sheen , Seok Pyo Song , Sang Tae Ahn , Hyeon Ju An , Hyun Chul Sohn
发明人： Dong Sun Sheen , Seok Pyo Song , Sang Tae Ahn , Hyeon Ju An , Hyun Chul Sohn
IPC分类号： H01L21/335
CPC分类号： H01L27/0886 , H01L27/1214
摘要： A method for manufacturing a semiconductor device is disclosed. The method includes the steps of defining a trench into a field region of a semiconductor substrate having an active region and the field region; partially filing the trench with a flowable insulation layer; completely filling the trench with an isolation structure by depositing a close-packed insulation layer on the flowable insulation layer in the trench; etching through a portion of the close-packed insulation layer and etching into a partial thickness of the flowable insulation layer of the insulation structure to expose a portion of the active region; cleaning the resultant substrate having the active region relatively projected; forming spacers on etched portions of the flowable insulation layer where bowing occurs during the cleaning step; and forming gates on the active region and the insulation structure to border the exposed portion of the active region.
摘要翻译：公开了一种制造半导体器件的方法。该方法包括以下步骤：将沟槽定义为具有有源区域和场区域的半导体衬底的场区域; 用可流动的绝缘层部分地填充沟槽; 通过在沟槽中的可流动绝缘层上沉积紧密堆积的绝缘层，通过隔离结构完全填充沟槽; 蚀刻通过所述紧密封装绝缘层的一部分并蚀刻成所述绝缘结构的可流动绝缘层的部分厚度以暴露所述有源区的一部分; 清洁具有相对投影的活性区域的所得基材; 在清洁步骤中发生弯曲的可流动绝缘层的蚀刻部分上形成间隔物; 以及在所述有源区和所述绝缘结构上形成栅极以与所述有源区的所述暴露部分相接触。

10. 发明授权

US08178921B2 Semiconductor device having reduced standby leakage current and increased driving current and method for manufacturing the same 有权
标题翻译：具有降低的待机漏电流和增加的驱动电流的半导体器件及其制造方法
公开(公告)号：US08178921B2
公开(公告)日：2012-05-15
申请号：US12638233
申请日：2009-12-15
申请人： Dong Sun Sheen , Sang Tae Ahn , Seok Pyo Song , Hyeon Ju An
发明人： Dong Sun Sheen , Sang Tae Ahn , Seok Pyo Song , Hyeon Ju An
IPC分类号： H01L29/78
CPC分类号： H01L29/78609 , H01L29/66795 , H01L29/7851
摘要： A semiconductor device includes a semiconductor substrate having an active region which includes a gate forming zone and an isolation region; an isolation layer formed in the isolation region of the semiconductor substrate to expose side surfaces of a portion of the active region including the gate forming zone, such that the portion of the active region including the gate forming zone constitutes a fin pattern; a silicon epitaxial layer formed on the active region including the fin pattern; and a gate formed to cover the fin pattern on which the silicon epitaxial layer is formed.
摘要翻译：半导体器件包括具有包括栅极形成区和隔离区的有源区的半导体衬底; 隔离层，其形成在所述半导体衬底的隔离区域中，以暴露包括所述栅极形成区的有源区的一部分的侧表面，使得包括所述栅极形成区的有源区的所述部分构成鳍状图案; 形成在包括鳍状图案的有源区上的硅外延层; 以及形成为覆盖其上形成有硅外延层的鳍图案的栅极。

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