专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20120020179A1 METHOD AND APPARATUS FOR WORD LINE DECODER LAYOUT 有权
标题翻译：字线解码器布局的方法和装置
公开(公告)号：US20120020179A1
公开(公告)日：2012-01-26
申请号：US12839490
申请日：2010-07-20
申请人： You-Cheng XIAO , Hong-Chen CHENG , Chung-Ji LU , Cheng Hung LEE , Jung-Hsuan CHEN , Li-Chun TIEN
发明人： You-Cheng XIAO , Hong-Chen CHENG , Chung-Ji LU , Cheng Hung LEE , Jung-Hsuan CHEN , Li-Chun TIEN
IPC分类号： G11C8/10
CPC分类号： G11C8/10 , G11C11/413
摘要： A word line decoder comprises a plurality of driver circuits, a plurality of word lines provided at respective outputs of the driver circuits, and a plurality of primary input lines coupled to the driver circuits and oriented in a first direction. The word line decoder also comprises a plurality of secondary input lines coupled to the driver circuits and oriented in the first direction. The word line decoder also comprises a local decode line coupled to each of the primary input lines. The word line decoder also comprises a decode line coupled to the local decode line and oriented in the first direction. A cluster decode line is coupled to the decode line. The word line decoder is configured to select at least one of the word lines based on signals provided by the cluster decode line and the secondary input lines.
摘要翻译：字线解码器包括多个驱动器电路，设置在驱动器电路的各个输出处的多个字线以及耦合到驱动器电路并沿第一方向取向的多个主输入线。字线解码器还包括耦合到驱动器电路并沿第一方向定向的多个次级输入线。字线解码器还包括耦合到每个主输入线的本地解码线。字线解码器还包括耦合到本地解码线并沿第一方向定向的解码线。集群解码线耦合到解码线。字线解码器被配置为基于由群集解码线和辅助输入线提供的信号来选择至少一个字线。

2. 发明申请

US20130010560A1 GENERATING AND AMPLIFYING DIFFERENTIAL SIGNALS 有权
标题翻译：生成和放大差分信号
公开(公告)号：US20130010560A1
公开(公告)日：2013-01-10
申请号：US13535075
申请日：2012-06-27
申请人： Chung-Ji LU , Hung-Jen LIAO , Cheng Hung LEE , Derek C. TAO , Annie-Li-Keow LUM , Hong-Chen CHENG
发明人： Chung-Ji LU , Hung-Jen LIAO , Cheng Hung LEE , Derek C. TAO , Annie-Li-Keow LUM , Hong-Chen CHENG
IPC分类号： H03F3/45 , G11C7/06
CPC分类号： G11C7/067 , G11C7/065
摘要： A circuit includes a first node, a second node, a first current mirror circuit, and a second current minor circuit. The first current mirror circuit has a reference end and a mirrored end. The reference end of the first current minor circuit is coupled to the first node, and the mirrored end of the first current minor circuit is coupled to the second node. The second current minor circuit has a reference end and a mirrored end. The reference end of the second current minor circuit is coupled to the second node, and the mirrored end of the second current minor circuit is coupled to the first node.
摘要翻译：电路包括第一节点，第二节点，第一电流镜电路和第二电流次要电路。第一电流镜电路具有参考端和镜像端。第一当前次要电路的参考端耦合到第一节点，并且第一当前次要电路的镜像端耦合到第二节点。第二个当前次级电路具有参考端和镜像端。第二电流次级电路的参考端耦合到第二节点，并且第二电流次级电路的镜像端耦合到第一节点。

3. 发明申请

US20120195139A1 MULTI-POWER DOMAIN DESIGN 有权
标题翻译：多功能域设计
公开(公告)号：US20120195139A1
公开(公告)日：2012-08-02
申请号：US13443619
申请日：2012-04-10
申请人： Hsu-Shun CHEN , Cheng Hung LEE , Chung-Ji LU , Hong-Chen CHENG , Chung-Yi WU , Chih-Chieh CHIU
发明人： Hsu-Shun CHEN , Cheng Hung LEE , Chung-Ji LU , Hong-Chen CHENG , Chung-Yi WU , Chih-Chieh CHIU
IPC分类号： G11C7/00 , G11C5/14
CPC分类号： G11C7/1048 , G11C5/14
摘要： In some embodiments related to a memory array, a sense amplifier (SA) uses a first power supply, e.g., voltage VDDA, while other circuitry, e.g., signal output logic, uses a second power supply, e.g., voltage VDDB. Various embodiments place the SA and a pair of transferring devices at a local IO row, and a voltage keeper at the main IO section of the same memory array. The SA, the transferring devices, and the voltage keeper, when appropriate, operate together so that the data logic of the circuitry provided by voltage VDDB is the same as the data logic of the circuitry provided by voltage VDDA.
摘要翻译：在与存储器阵列相关的一些实施例中，读出放大器（SA）使用第一电源，例如电压VDDA，而其它电路（例如，信号输出逻辑）使用第二电源，例如电压VDDB。各种实施例将SA和一对传送装置放置在本地IO行上，并将电压保持器放置在同一存储器阵列的主IO部分。 SA，传输装置和电压保持器在适当的情况下一起工作，使得由电压VDDB提供的电路的数据逻辑与由电压VDDA提供的电路的数据逻辑相同。

4. 发明申请

US20120182792A1 BIASING CIRCUIT AND TECHNIQUE FOR SRAM DATA RETENTION 有权
标题翻译：用于SRAM数据保持的偏置电路和技术
公开(公告)号：US20120182792A1
公开(公告)日：2012-07-19
申请号：US13008992
申请日：2011-01-19
申请人： Hong-Chen CHENG , Chih-Chieh CHIU , Hsu-Shun CHEN , Chung-Ji LU , Cheng-Hung LEE , Hung-Jen LIAO
发明人： Hong-Chen CHENG , Chih-Chieh CHIU , Hsu-Shun CHEN , Chung-Ji LU , Cheng-Hung LEE , Hung-Jen LIAO
IPC分类号： G11C11/413 , G11C5/14
CPC分类号： G11C11/413
摘要： A SRAM system includes: a SRAM cell array coupled between high and low supply nodes, a difference therebetween defining a data retention voltage (VDR) for a low power data retention mode; a main power switch coupling one of high and low supply nodes to a main power supply and disconnecting the one high and low supply nodes from the main power supply during the low power data retention mode; a monitor cell including a SRAM cell preloaded with a data bit and configured for data destruction responsive to a reduction in VDR before data destruction occurs in the SRAM cell array; and a clamping power switch responsive to data destruction in the monitor cell to couple the one of the high and low supply nodes to the main power supply.
摘要翻译： SRAM系统包括：耦合在高电源节点和低电源节点之间的SRAM单元阵列，其间限定用于低功率数据保持模式的数据保持电压（VDR）; 主电源开关将高电源和低电源节点之一耦合到主电源，并且在低功率数据保持模式期间将一个高电源和低电源节点与主电源断开; 监控单元，其包括预先装载有数据位的SRAM单元，并且被配置为在SRAM单元阵列中发生数据破坏之前响应于VDR的减小而进行的数据破坏; 以及钳位电源开关，其响应于监视器单元中的数据破坏，将高电源节点和低电源节点中的一个耦合到主电源。

5. 发明申请

US20120092939A1 SINGLE-ENDED SENSING SCHEME FOR MEMORY 有权
标题翻译：内存单端感应方案
公开(公告)号：US20120092939A1
公开(公告)日：2012-04-19
申请号：US12917708
申请日：2010-11-02
申请人： Hong-Chen CHENG , Chih-Chieh CHIU , Chung-Ji LU , Cheng Hung LEE
发明人： Hong-Chen CHENG , Chih-Chieh CHIU , Chung-Ji LU , Cheng Hung LEE
IPC分类号： G11C7/12 , G11C7/06
CPC分类号： G11C7/067 , G11C7/12 , G11C11/419
摘要： A memory having a single-ended sensing scheme includes a bit line, a memory cell coupled to the bit line, and a precharge circuit. The precharge circuit is configured to precharge the bit line to a precharge voltage between a power supply voltage and a ground.
摘要翻译：具有单端感测方案的存储器包括位线，耦合到位线的存储单元和预充电电路。预充电电路被配置为将位线预充电到电源电压和地之间的预充电电压。

6. 发明申请

US20120061764A1 MODIFIED DESIGN RULES TO IMPROVE DEVICE PERFORMANCE 有权
标题翻译：改进设计规范，以提高设备性能
公开(公告)号：US20120061764A1
公开(公告)日：2012-03-15
申请号：US12879447
申请日：2010-09-10
申请人： Annie LUM , Derek C. TAO , Cheng Hung LEE , Chung-Ji LU , Hong-Chen CHENG , Vineet Kumar AGRAWAL , Keun-Young KIM , Pyong Yun CHO
发明人： Annie LUM , Derek C. TAO , Cheng Hung LEE , Chung-Ji LU , Hong-Chen CHENG , Vineet Kumar AGRAWAL , Keun-Young KIM , Pyong Yun CHO
IPC分类号： H01L27/088 , G06F17/50
CPC分类号： G06F17/5068 , G06F17/5081 , G06F2217/12 , H01L27/0207 , H01L27/088 , Y02P90/265
摘要： The layouts, device structures, and methods described above utilize dummy devices to extend the diffusion regions of edge structures and/or non-allowed structures to the dummy device. Such extension of diffusion regions resolves or reduces LOD and edge effect issues. In addition, treating the gate structure of a dummy device next to an edge device also allows only one dummy structure to be added next to the dummy device and saves the real estate on the semiconductor chip. The dummy devices are deactivated and their performance is not important. Therefore, utilizing dummy devices to extend the diffusion regions of edge structures and/or non-allowed structures according to design rules allows the resolution or reduction or LOD and edge effect issues without the penalty of yield reduction or increase in layout areas.
摘要翻译：上述布局，装置结构和方法利用虚设装置将边缘结构和/或非允许结构的扩散区域扩展到虚设装置。这种扩散区域的扩展可解决或减少LOD和边缘效应问题。此外，在边缘装置旁边处理伪装置的栅极结构也仅允许在虚设装置旁边添加一个虚拟结构，并将该不动产保存在半导体芯片上。虚拟设备被禁用，其性能不重要。因此，利用虚设装置根据设计规则扩展边缘结构和/或非允许结构的扩散区域允许分辨率或降低或LOD和边缘效应发生，而不会降低成品率或增加布局面积。

7. 发明申请

US20110194362A1 WORD-LINE DRIVER USING LEVEL SHIFTER AT LOCAL CONTROL CIRCUIT 有权
标题翻译：在本地控制电路上使用电平变换器的字线驱动器
公开(公告)号：US20110194362A1
公开(公告)日：2011-08-11
申请号：US12702594
申请日：2010-02-09
申请人： Chung-Ji LU , Lee-Cheng HUNG , Hung-Jen LIAO , Hsu-Shun CHEN , Hong-Chen CHENG , Chung-Yi Wu , Uppu Sharath CHANDRA
发明人： Chung-Ji LU , Lee-Cheng HUNG , Hung-Jen LIAO , Hsu-Shun CHEN , Hong-Chen CHENG , Chung-Yi Wu , Uppu Sharath CHANDRA
IPC分类号： G11C7/00 , G11C8/08
CPC分类号： G11C8/08 , G11C8/10
摘要： A representative circuit device includes a local control circuit having a level shifter, wherein in response to receipt of a first address signal the level shifter shifts the first address signal from a first voltage level to a second voltage level, providing a level shifted first address signal; and a word-line driver having at least one input for receiving a plurality of address signals, wherein the at least one input includes a first input that is coupled to the local control circuit to receive the level shifted first address signal, and an output that is electrically coupled to a word line of a memory cell array.
摘要翻译：代表性电路装置包括具有电平移位器的本地控制电路，其中响应于接收到第一地址信号，电平移位器将第一地址信号从第一电压电平移位到第二电压电平，提供电平移位的第一地址信号 ; 以及具有用于接收多个地址信号的至少一个输入的字线驱动器，其中所述至少一个输入包括耦合到所述本地控制电路以接收所述电平移位的第一地址信号的第一输入，以及输出，电耦合到存储单元阵列的字线。

8. 发明申请

US20110090753A1 POWER MANAGEMENT 有权
标题翻译：能源管理
公开(公告)号：US20110090753A1
公开(公告)日：2011-04-21
申请号：US12885826
申请日：2010-09-20
申请人： Cheng Hung LEE , Chung-Yi WU , Hsu-Shun CHEN , Chung-Ji LU
发明人： Cheng Hung LEE , Chung-Yi WU , Hsu-Shun CHEN , Chung-Ji LU
IPC分类号： G11C5/14
CPC分类号： G11C11/413
摘要： An SRAM includes circuitry configured for the SRAM to operate at different operation modes using different voltage levels wherein the voltage level and thus the supply current leakage is regulated based on the operation mode. For example, the SRAM, in a normal operation mode, consumes power as other SRAMs. In a deep sleep mode the supply voltage (e.g., VDDI) for the bit cell in the SRAM macro is lowered by about 20-40% of the SRAM supply voltage (e.g., VDD), sufficient to retain the data in the bit cell. When access to the SRAM is not needed, the SRAM operates in the sleep mode, consuming little or no power.
摘要翻译： SRAM包括被配置用于使用不同的电压电平在不同的操作模式下工作的电路，其中基于操作模式调节电压电平和因此的电流泄漏。例如，在正常工作模式下，SRAM将作为其他SRAM消耗电力。在深度睡眠模式下，SRAM宏中的位单元的电源电压（例如，VDDI）降低SRAM电源电压（例如VDD）的约20-40％，足以将数据保留在位单元中。当不需要访问SRAM时，SRAM在睡眠模式下运行，消耗很少或没有电源。

9. 发明申请

US20100246311A1 CLOCK GENERATORS, MEMORY CIRCUITS, SYSTEMS, AND METHODS FOR PROVIDING AN INTERNAL CLOCK SIGNAL 有权
标题翻译：用于提供内部时钟信号的时钟发生器，存储器电路，系统和方法
公开(公告)号：US20100246311A1
公开(公告)日：2010-09-30
申请号：US12723077
申请日：2010-03-12
申请人： Derek C. TAO , Chung-Ji LU , Annie-Li-Keow LUM
发明人： Derek C. TAO , Chung-Ji LU , Annie-Li-Keow LUM
IPC分类号： G11C8/18 , G06F1/04
CPC分类号： G06F1/10 , G11C7/22 , G11C7/222 , G11C11/413
摘要： A clock generator includes a first input end and a second input end. The first input end is capable of receiving a first clock signal including a first state transition and a second state transition defining a first pulse width. The second input end is capable of receiving a second clock signal having a third state transition. A time period ranges from the first state transition to the third state transition. The clock generator can compare the first pulse width and the time period. The clock generator can output a third clock signal having a second pulse width ranging from a fourth state transition to a fifth state transition. The fifth state transition of the third clock signal is capable of being triggered by the second state transition of the first clock signal or the third state transition of the second clock signal depending on the comparison of the first pulse width and the time period.
摘要翻译：时钟发生器包括第一输入端和第二输入端。第一输入端能够接收包括定义第一脉冲宽度的第一状态转变和第二状态转换的第一时钟信号。第二输入端能够接收具有第三状态转换的第二时钟信号。时间段从第一状态转换到第三状态转换。时钟发生器可以比较第一个脉冲宽度和时间周期。时钟发生器可以输出具有从第四状态转变到第五状态转变的第二脉冲宽度的第三时钟信号。根据第一脉冲宽度与时间段的比较，第三时钟信号的第五状态转换能够被第一时钟信号的第二状态转换或第二时钟信号的第三状态转换触发。

10. 发明申请

US20120051160A1 MULTIPLE BITCELLS TRACKING SCHEME FOR SEMICONDUCTOR MEMORIES 有权
标题翻译：用于半导体存储器的多个位元跟踪方案
公开(公告)号：US20120051160A1
公开(公告)日：2012-03-01
申请号：US12868909
申请日：2010-08-26
申请人： Derek C. TAO , Annie-Li-Keow LUM , Chung-Ji LU
发明人： Derek C. TAO , Annie-Li-Keow LUM , Chung-Ji LU
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G11C29/50012 , G11C11/41
摘要： A semiconductor memory segment includes a first memory bank having a first tracking cell disposed in a first tracking column. A second memory bank includes a second tracking cell disposed in a second tracking column. A first tracking circuit is coupled to the first and second tracking cells and is configured to output a first signal to memory control circuitry when the first and second tracking cells are accessed. The memory control circuitry is configured to set a clock based on the first signal.
摘要翻译：半导体存储器段包括具有设置在第一跟踪列中的第一跟踪单元的第一存储体。第二存储器组包括设置在第二跟踪列中的第二跟踪单元。第一跟踪电路耦合到第一和第二跟踪单元，并且被配置为当第一和第二跟踪单元被访问时，将第一信号输出到存储器控制电路。存储器控制电路被配置为基于第一信号设置时钟。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式