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1. 发明申请

US20130010560A1 GENERATING AND AMPLIFYING DIFFERENTIAL SIGNALS 有权
标题翻译：生成和放大差分信号
公开(公告)号：US20130010560A1
公开(公告)日：2013-01-10
申请号：US13535075
申请日：2012-06-27
申请人： Chung-Ji LU , Hung-Jen LIAO , Cheng Hung LEE , Derek C. TAO , Annie-Li-Keow LUM , Hong-Chen CHENG
发明人： Chung-Ji LU , Hung-Jen LIAO , Cheng Hung LEE , Derek C. TAO , Annie-Li-Keow LUM , Hong-Chen CHENG
IPC分类号： H03F3/45 , G11C7/06
CPC分类号： G11C7/067 , G11C7/065
摘要： A circuit includes a first node, a second node, a first current mirror circuit, and a second current minor circuit. The first current mirror circuit has a reference end and a mirrored end. The reference end of the first current minor circuit is coupled to the first node, and the mirrored end of the first current minor circuit is coupled to the second node. The second current minor circuit has a reference end and a mirrored end. The reference end of the second current minor circuit is coupled to the second node, and the mirrored end of the second current minor circuit is coupled to the first node.
摘要翻译：电路包括第一节点，第二节点，第一电流镜电路和第二电流次要电路。第一电流镜电路具有参考端和镜像端。第一当前次要电路的参考端耦合到第一节点，并且第一当前次要电路的镜像端耦合到第二节点。第二个当前次级电路具有参考端和镜像端。第二电流次级电路的参考端耦合到第二节点，并且第二电流次级电路的镜像端耦合到第一节点。

2. 发明申请

US20100246311A1 CLOCK GENERATORS, MEMORY CIRCUITS, SYSTEMS, AND METHODS FOR PROVIDING AN INTERNAL CLOCK SIGNAL 有权
标题翻译：用于提供内部时钟信号的时钟发生器，存储器电路，系统和方法
公开(公告)号：US20100246311A1
公开(公告)日：2010-09-30
申请号：US12723077
申请日：2010-03-12
申请人： Derek C. TAO , Chung-Ji LU , Annie-Li-Keow LUM
发明人： Derek C. TAO , Chung-Ji LU , Annie-Li-Keow LUM
IPC分类号： G11C8/18 , G06F1/04
CPC分类号： G06F1/10 , G11C7/22 , G11C7/222 , G11C11/413
摘要： A clock generator includes a first input end and a second input end. The first input end is capable of receiving a first clock signal including a first state transition and a second state transition defining a first pulse width. The second input end is capable of receiving a second clock signal having a third state transition. A time period ranges from the first state transition to the third state transition. The clock generator can compare the first pulse width and the time period. The clock generator can output a third clock signal having a second pulse width ranging from a fourth state transition to a fifth state transition. The fifth state transition of the third clock signal is capable of being triggered by the second state transition of the first clock signal or the third state transition of the second clock signal depending on the comparison of the first pulse width and the time period.
摘要翻译：时钟发生器包括第一输入端和第二输入端。第一输入端能够接收包括定义第一脉冲宽度的第一状态转变和第二状态转换的第一时钟信号。第二输入端能够接收具有第三状态转换的第二时钟信号。时间段从第一状态转换到第三状态转换。时钟发生器可以比较第一个脉冲宽度和时间周期。时钟发生器可以输出具有从第四状态转变到第五状态转变的第二脉冲宽度的第三时钟信号。根据第一脉冲宽度与时间段的比较，第三时钟信号的第五状态转换能够被第一时钟信号的第二状态转换或第二时钟信号的第三状态转换触发。

3. 发明申请

US20120051160A1 MULTIPLE BITCELLS TRACKING SCHEME FOR SEMICONDUCTOR MEMORIES 有权
标题翻译：用于半导体存储器的多个位元跟踪方案
公开(公告)号：US20120051160A1
公开(公告)日：2012-03-01
申请号：US12868909
申请日：2010-08-26
申请人： Derek C. TAO , Annie-Li-Keow LUM , Chung-Ji LU
发明人： Derek C. TAO , Annie-Li-Keow LUM , Chung-Ji LU
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G11C29/50012 , G11C11/41
摘要： A semiconductor memory segment includes a first memory bank having a first tracking cell disposed in a first tracking column. A second memory bank includes a second tracking cell disposed in a second tracking column. A first tracking circuit is coupled to the first and second tracking cells and is configured to output a first signal to memory control circuitry when the first and second tracking cells are accessed. The memory control circuitry is configured to set a clock based on the first signal.
摘要翻译：半导体存储器段包括具有设置在第一跟踪列中的第一跟踪单元的第一存储体。第二存储器组包括设置在第二跟踪列中的第二跟踪单元。第一跟踪电路耦合到第一和第二跟踪单元，并且被配置为当第一和第二跟踪单元被访问时，将第一信号输出到存储器控制电路。存储器控制电路被配置为基于第一信号设置时钟。

4. 发明申请

US20130215693A1 TRACKING CAPACITIVE LOADS 有权
标题翻译：跟踪电容负载
公开(公告)号：US20130215693A1
公开(公告)日：2013-08-22
申请号：US13399877
申请日：2012-02-17
申请人： Derek C. TAO , Young Seog KIM , Kuoyuan (Peter) HSU , Bing WANG , Annie-Li-Keow LUM
发明人： Derek C. TAO , Young Seog KIM , Kuoyuan (Peter) HSU , Bing WANG , Annie-Li-Keow LUM
IPC分类号： G11C7/00
CPC分类号： G11C29/24 , G11C7/222 , G11C11/41 , G11C29/50012 , G11C2029/5002
摘要： A time delay is determined to cover a timing of a memory cell in a memory macro having a tracking circuit. Based on the time delay, a capacitance corresponding to the time delay is determined. A capacitor having the determined capacitance is utilized. The capacitor is coupled to a first data line of a tracking cell of the tracking circuit. A first transition of the first data line causes a first transition of a second data line of the memory cell.
摘要翻译：确定时间延迟以覆盖具有跟踪电路的存储器宏中的存储器单元的定时。基于时间延迟，确定与时间延迟相对应的电容。使用具有确定的电容的电容器。电容器耦合到跟踪电路的跟踪单元的第一数据线。第一数据线的第一转变导致存储器单元的第二数据线的第一转变。

5. 发明申请

US20130088926A1 TRACKING MECHANISMS 有权
标题翻译：跟踪机制
公开(公告)号：US20130088926A1
公开(公告)日：2013-04-11
申请号：US13253749
申请日：2011-10-05
申请人： Derek C. TAO , Annie-Li-Keow LUM , Yukit TANG , Kuoyuan (Peter) HSU
发明人： Derek C. TAO , Annie-Li-Keow LUM , Yukit TANG , Kuoyuan (Peter) HSU
IPC分类号： G11C7/10 , G11C7/00
CPC分类号： G11C7/222 , G11C7/10 , G11C7/1051 , G11C11/419
摘要： A tracking edge of a tracking signal is activated. A buffer is turned off and a latching circuit is turned on, based on the tracking edge of the tracking signal. A buffer output of the buffer is coupled to a latch output of the latching circuit at a node. The buffer receives a data line of a memory macro.
摘要翻译：跟踪信号的跟踪边缘被激活。基于跟踪信号的跟踪边缘，缓冲器被关闭并且锁存电路被接通。缓冲器的缓冲器输出耦合到节点处的锁存电路的锁存器输出。缓冲区接收一个内存宏的数据行。

6. 发明申请

US20140269026A1 TRACKING CIRCUIT 有权
标题翻译：跟踪电路
公开(公告)号：US20140269026A1
公开(公告)日：2014-09-18
申请号：US13840668
申请日：2013-03-15
申请人： Derek C. TAO , Annie-Li-Keow LUM , Kuoyuan (Peter) HSU
发明人： Derek C. TAO , Annie-Li-Keow LUM , Kuoyuan (Peter) HSU
IPC分类号： G11C7/22
CPC分类号： G11C7/227 , G11C11/419
摘要： A circuit is in a memory macro and comprises a write path, a read path, a selection circuit, and a clock generator circuit. The write path includes a first signal generated based on a first edge of a clock signal in a write operation of the memory macro. The read path includes a second signal generated based on a first edge of the clock signal in a read operation of the memory macro. The selection circuit is configured to select the first signal as a third signal in the write operation of the memory macro, and to select the second signal as the third signal in the read operation of the memory macro. The clock generator circuit is configured to generate a second edge of the clock signal in the write operation or in the read operation based on the third signal.
摘要翻译：电路位于存储器宏中，并且包括写入路径，读取路径，选择电路和时钟发生器电路。写入路径包括在存储器宏的写入操作中基于时钟信号的第一边缘生成的第一信号。读取路径包括在存储器宏的读取操作中基于时钟信号的第一边缘生成的第二信号。选择电路被配置为在存储器宏的写入操作中选择第一信号作为第三信号，并且在存储器宏的读取操作中选择第二信号作为第三信号。时钟发生器电路被配置为在写入操作或基于第三信号的读取操作中产生时钟信号的第二边沿。

7. 发明申请

US20120061764A1 MODIFIED DESIGN RULES TO IMPROVE DEVICE PERFORMANCE 有权
标题翻译：改进设计规范，以提高设备性能
公开(公告)号：US20120061764A1
公开(公告)日：2012-03-15
申请号：US12879447
申请日：2010-09-10
申请人： Annie LUM , Derek C. TAO , Cheng Hung LEE , Chung-Ji LU , Hong-Chen CHENG , Vineet Kumar AGRAWAL , Keun-Young KIM , Pyong Yun CHO
发明人： Annie LUM , Derek C. TAO , Cheng Hung LEE , Chung-Ji LU , Hong-Chen CHENG , Vineet Kumar AGRAWAL , Keun-Young KIM , Pyong Yun CHO
IPC分类号： H01L27/088 , G06F17/50
CPC分类号： G06F17/5068 , G06F17/5081 , G06F2217/12 , H01L27/0207 , H01L27/088 , Y02P90/265
摘要： The layouts, device structures, and methods described above utilize dummy devices to extend the diffusion regions of edge structures and/or non-allowed structures to the dummy device. Such extension of diffusion regions resolves or reduces LOD and edge effect issues. In addition, treating the gate structure of a dummy device next to an edge device also allows only one dummy structure to be added next to the dummy device and saves the real estate on the semiconductor chip. The dummy devices are deactivated and their performance is not important. Therefore, utilizing dummy devices to extend the diffusion regions of edge structures and/or non-allowed structures according to design rules allows the resolution or reduction or LOD and edge effect issues without the penalty of yield reduction or increase in layout areas.
摘要翻译：上述布局，装置结构和方法利用虚设装置将边缘结构和/或非允许结构的扩散区域扩展到虚设装置。这种扩散区域的扩展可解决或减少LOD和边缘效应问题。此外，在边缘装置旁边处理伪装置的栅极结构也仅允许在虚设装置旁边添加一个虚拟结构，并将该不动产保存在半导体芯片上。虚拟设备被禁用，其性能不重要。因此，利用虚设装置根据设计规则扩展边缘结构和/或非允许结构的扩散区域允许分辨率或降低或LOD和边缘效应发生，而不会降低成品率或增加布局面积。

8. 发明申请

US20130264718A1 LAYOUT OF MEMORY STRAP CELL 有权
标题翻译：记忆层细胞的布局
公开(公告)号：US20130264718A1
公开(公告)日：2013-10-10
申请号：US13443467
申请日：2012-04-10
申请人： Jacklyn CHANG , Evan Yong ZHANG , Derek C. TAO , Kuoyuan (Peter) HSU
发明人： Jacklyn CHANG , Evan Yong ZHANG , Derek C. TAO , Kuoyuan (Peter) HSU
IPC分类号： H01L23/498
CPC分类号： H01L27/1104 , H01L27/0207
摘要： A layout structure includes a substrate, a well, a first dopant area, a second dopant area, a first poly region, a third dopant area, a fourth dopant area, and a second poly region. The well is in the substrate. The first poly region is in between the first dopant area and the second dopant area. The second poly region is in between the third dopant area and the fourth dopant area. The first dopant area, the second dopant area, the third dopant area, and the fourth dopant area are in the well. The first dopant area is configured to serve as a source of a transistor and to receive a first voltage value from a first power supply source. The well is configured to serve as a bulk of the transistor and to receive a second voltage value from a second power supply source.
摘要翻译：布局结构包括衬底，阱，第一掺杂区，第二掺杂区，第一多晶区，第三掺杂区，第四掺杂区和第二多晶区。井在底层。第一多晶硅区位于第一掺杂区和第二掺杂区之间。第二聚合区位于第三掺杂区和第四掺杂区之间。第一掺杂剂区域，第二掺杂剂区域，第三掺杂剂区域和第四掺杂剂区域在井中。第一掺杂剂区域被配置为用作晶体管的源极并且从第一电源接收第一电压值。阱被配置为用作晶体管的体积并从第二电源接收第二电压值。

9. 发明申请

US20110280096A1 MEMORY CIRCUITS HAVING A PLURALITY OF KEEPERS 有权
标题翻译：具有多个保持者的记忆电路
公开(公告)号：US20110280096A1
公开(公告)日：2011-11-17
申请号：US13025668
申请日：2011-02-11
申请人： Annie LUM , Derek C. TAO , Young Seog KIM
发明人： Annie LUM , Derek C. TAO , Young Seog KIM
IPC分类号： G11C5/14
CPC分类号： G11C7/12 , G11C5/147 , G11C11/412 , G11C11/413
摘要： A memory circuit includes a first plurality of memory arrays disposed in a column fashion. The memory circuit includes a first plurality of keepers each of which is electrically coupled with a corresponding one of the first plurality of memory arrays. A first current limiter is electrically coupled with and shared by the first plurality of keepers. A first plurality of sector switches each are electrically coupled between the first current limiter and a respective one of the first plurality of keepers.
摘要翻译：存储电路包括以列方式设置的第一多个存储器阵列。存储器电路包括第一多个保持器，每个保持器与第一多个存储器阵列中的对应的一个存储器阵列电耦合。第一限流器与第一多个保持器电耦合并共享。第一多个扇区开关各自在第一限流器和第一多个保持器中的相应一个之间电耦合。

10. 发明申请

US20130088925A1 LAYOUT OF MEMORY CELLS 有权
标题翻译：记忆细胞的布局
公开(公告)号：US20130088925A1
公开(公告)日：2013-04-11
申请号：US13267235
申请日：2011-10-06
申请人： Jacklyn CHANG , Derek C. TAO , Yukit TANG , Kuoyuan (Peter) HSU
发明人： Jacklyn CHANG , Derek C. TAO , Yukit TANG , Kuoyuan (Peter) HSU
IPC分类号： G11C7/10
CPC分类号： G11C7/18 , G11C11/412 , G11C11/413 , H01L27/0207 , H01L27/1104
摘要： A semiconductor structure includes a first strap cell, a first read port, and a first VSS terminal. The first strap cell has a first strap cell VSS region. The first read port has a first read port VSS region, a first read port read bit line region, and a first read port poly region. The first VSS terminal is configured to electrically couple the first strap cell VSS region and the first read port VSS region.
摘要翻译：半导体结构包括第一带状电池，第一读取端口和第一VSS端子。第一带状电池具有第一带电池VSS区域。第一读取端口具有第一读取端口VSS区域，第一读取端口读取位线区域和第一读取端口聚合区域。第一VSS端子被配置为电耦合第一带电池VSS区域和第一读取端口VSS区域。

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