专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US09058858B2 Method and apparatus for dual rail SRAM level shifter with latching 有权
标题翻译：具有锁存功能的双轨SRAM电平转换器的方法和装置
公开(公告)号：US09058858B2
公开(公告)日：2015-06-16
申请号：US13303231
申请日：2011-11-23
申请人： Hong-Chen Cheng , Chia-En Huang , Chih-Chieh Chiu , Jung-Ping Yang
发明人： Hong-Chen Cheng , Chia-En Huang , Chih-Chieh Chiu , Jung-Ping Yang
IPC分类号： G11C11/418 , G11C8/10 , G11C11/413
CPC分类号： G11C8/10 , G11C11/413 , G11C11/418
摘要： An apparatus includes a level shifter and a switching circuit. The level shifter includes an input, a first output, and second output having a logic value complementary to a logic value of the first output. The switching circuit includes a data input, a feedback input coupled to the second output of the level shifter, and an output coupled to the input of the level shifter. The switching circuit is configured to selectively latch, based on a select signal, a logic state of the level shifter at the second output.
摘要翻译：一种装置包括电平移位器和开关电路。电平移位器包括具有与第一输出的逻辑值互补的逻辑值的输入，第一输出和第二输出。切换电路包括数据输入，耦合到电平移位器的第二输出的反馈输入以及耦合到电平移位器的输入的输出。开关电路被配置为基于选择信号选择性地锁存第二输出处的电平移位器的逻辑状态。

2. 发明授权

US08982609B2 Memory having read assist device and method of operating the same 有权
标题翻译：具有读取辅助装置的存储器及其操作方法
公开(公告)号：US08982609B2
公开(公告)日：2015-03-17
申请号：US13372099
申请日：2012-02-13
申请人： Jung-Ping Yang , Hong-Chen Cheng , Chih-Chieh Chiu , Chia-En Huang , Cheng Hung Lee
发明人： Jung-Ping Yang , Hong-Chen Cheng , Chih-Chieh Chiu , Chia-En Huang , Cheng Hung Lee
IPC分类号： G11C11/00
CPC分类号： G11C11/4094 , G11C11/419
摘要： A memory includes a first bit line, a memory cell coupled to the first bit line, and a read assist device coupled to the first bit line. The read assist device is configured to pull a first voltage on the first bit line toward a predetermined voltage in response to a first datum being read out from the memory cell. The read assist device includes a first circuit configured to establish a first current path between the first bit line and a node of the predetermined voltage during a first stage. The read assist device further includes a second circuit configured to establish a second current path between the first bit line and the node of the predetermined voltage during a second, subsequent stage.
摘要翻译：存储器包括第一位线，耦合到第一位线的存储器单元和耦合到第一位线的读取辅助器件。读取辅助装置被配置为响应于从存储器单元读出的第一数据，将第一位线上的第一电压拉向预定电压。读取辅助装置包括第一电路，其被配置为在第一阶段期间在第一位线和预定电压的节点之间建立第一电流路径。读取辅助装置还包括第二电路，其被配置为在第二后续阶段期间在第一位线和预定电压的节点之间建立第二电流路径。

3. 发明授权

US08675439B2 Bit line voltage bias for low power memory design 有权
标题翻译：用于低功耗存储器设计的位线电压偏置
公开(公告)号：US08675439B2
公开(公告)日：2014-03-18
申请号：US13271353
申请日：2011-10-12
申请人： Hong-Chen Cheng , Jung-Ping Yang , Chiting Cheng , Cheng-Hung Lee , Sang H. Dong , Hung-Jen Liao
发明人： Hong-Chen Cheng , Jung-Ping Yang , Chiting Cheng , Cheng-Hung Lee , Sang H. Dong , Hung-Jen Liao
IPC分类号： G11C5/14
CPC分类号： G11C7/12 , G11C11/419
摘要： In a digital memory with an array of bit cells coupled to word lines and bit lines, each bit cell having cross coupled inverters isolated from bit lines by passing gate transistors until addressed, some or all of the bit cells are switchable between a sleep mode and a standby mode in response to a control signal. A bit line bias circuit controls the voltage at which the bit lines are caused to float when in the sleep mode. A pull-up transistor for each bit line BL or BLB in a complementary pair has a conductive channel coupled to a positive supply voltage and a gate coupled to the other bit line in the pair, BLB or BL, respectively. A connecting transistor also can be coupled between the bit lines of the complementary pair, bringing the floating bit lines to the supply voltage less a difference voltage ΔV.
摘要翻译：在具有耦合到字线和位线的位单元阵列的数字存储器中，每个位单元具有通过将栅极晶体管直接寻址而与位线隔离的交叉耦合的反相器，部分或全部位单元可在睡眠模式和响应于控制信号的待机模式。位线偏置电路控制在处于睡眠模式时使位线浮动的电压。用于互补对中的每个位线BL或BLB的上拉晶体管具有耦合到正电源电压的导电沟道和耦合到该对BLB或BL中的另一位线的栅极。连接晶体管也可以耦合在互补对的位线之间，使浮置位线降低到差值ΔVV的电源电压。

4. 发明申请

US20140036608A1 TRACKING SIGNALS IN MEMORY WRITE OR READ OPERATION 有权
标题翻译：在记忆写入或读操作中跟踪信号
公开(公告)号：US20140036608A1
公开(公告)日：2014-02-06
申请号：US13776040
申请日：2013-02-25
申请人： Chih-Chieh CHIU , Hong-Chen CHENG
发明人： Chih-Chieh CHIU , Hong-Chen CHENG
IPC分类号： G11C7/22
CPC分类号： G11C11/419 , G11C7/08 , G11C7/227 , G11C11/4076 , G11C11/4099
摘要： A signal generating circuit includes a first circuit, a tracking circuit, and a delay circuit coupled with the first circuit and the tracking circuit. The first circuit is configured to receive a first clock signal and an output signal from an output of the delay circuit and to generate a second clock signal and at least one first tracking signal. The tracking circuit is configured to receive the at least one first tracking signal and to generate a second tracking signal. The delay circuit is configured to receive the second clock signal and the second tracking signal and to generate the output signal.
摘要翻译：信号发生电路包括第一电路，跟踪电路和与第一电路和跟踪电路耦合的延迟电路。第一电路被配置为从延迟电路的输出接收第一时钟信号和输出信号，并且产生第二时钟信号和至少一个第一跟踪信号。跟踪电路被配置为接收至少一个第一跟踪信号并产生第二跟踪信号。延迟电路被配置为接收第二时钟信号和第二跟踪信号并产生输出信号。

5. 发明授权

US08519444B2 Modified design rules to improve device performance 有权
标题翻译：改进设计规则以提高设备性能
公开(公告)号：US08519444B2
公开(公告)日：2013-08-27
申请号：US12879447
申请日：2010-09-10
申请人： Annie Lum , Derek C. Tao , Cheng Hung Lee , Chung-Ji Lu , Hong-Chen Cheng , Vineet Kumar Agrawal , Keun-Young Kim , Pyong Yun Cho
发明人： Annie Lum , Derek C. Tao , Cheng Hung Lee , Chung-Ji Lu , Hong-Chen Cheng , Vineet Kumar Agrawal , Keun-Young Kim , Pyong Yun Cho
IPC分类号： H01L27/118
CPC分类号： G06F17/5068 , G06F17/5081 , G06F2217/12 , H01L27/0207 , H01L27/088 , Y02P90/265
摘要： The layouts, device structures, and methods described above utilize dummy devices to extend the diffusion regions of edge structures and/or non-allowed structures to the dummy device. Such extension of diffusion regions resolves or reduces LOD and edge effect issues. In addition, treating the gate structure of a dummy device next to an edge device also allows only one dummy structure to be added next to the dummy device and saves the real estate on the semiconductor chip. The dummy devices are deactivated and their performance is not important. Therefore, utilizing dummy devices to extend the diffusion regions of edge structures and/or non-allowed structures according to design rules allows the resolution or reduction or LOD and edge effect issues without the penalty of yield reduction or increase in layout areas.
摘要翻译：上述布局，装置结构和方法利用虚设装置将边缘结构和/或非允许结构的扩散区域扩展到虚设装置。这种扩散区域的扩展可解决或减少LOD和边缘效应问题。此外，在边缘装置旁边处理伪装置的栅极结构也仅允许在虚设装置旁边添加一个虚拟结构，并将该不动产保存在半导体芯片上。虚拟设备被禁用，其性能不重要。因此，利用虚设装置根据设计规则扩展边缘结构和/或非允许结构的扩散区域允许分辨率或降低或LOD和边缘效应发生，而不会降低成品率或增加布局面积。

6. 发明授权

US08482990B2 Memory edge cell 有权
标题翻译：内存边缘单元格
公开(公告)号：US08482990B2
公开(公告)日：2013-07-09
申请号：US13025872
申请日：2011-02-11
申请人： Hong-Chen Cheng , Ming-Yi Lee , Kuo-Hua Pan , Jung-Hsuan Chen , Li-Chun Tien , Cheng Hung Lee , Hung-Jen Liao
发明人： Hong-Chen Cheng , Ming-Yi Lee , Kuo-Hua Pan , Jung-Hsuan Chen , Li-Chun Tien , Cheng Hung Lee , Hung-Jen Liao
IPC分类号： G11C7/10
CPC分类号： G11C5/06 , G11C5/147 , G11C5/148 , G11C11/417
摘要： A circuit comprises a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor. The PMOS transistors and the NMOS transistors are configured to provide a first voltage reference node having a first reference voltage and a second voltage reference node having a second reference voltage. The first reference voltage and the second reference voltage serve as a first reference voltage and a second reference voltage for a memory cell, respectively.
摘要翻译：电路包括第一PMOS晶体管，第二PMOS晶体管，第一NMOS晶体管，第二NMOS晶体管，第三NMOS晶体管和第四NMOS晶体管。 PMOS晶体管和NMOS晶体管被配置为提供具有第一参考电压的第一电压参考节点和具有第二参考电压的第二参考电压节点。第一参考电压和第二参考电压分别用作存储器单元的第一参考电压和第二参考电压。

7. 发明申请

US20130128655A1 METHOD AND APPARATUS FOR DUAL RAIL SRAM LEVEL SHIFTER WITH LATCHING 有权
标题翻译：用于双轨SRAM水平移位器的方法和装置
公开(公告)号：US20130128655A1
公开(公告)日：2013-05-23
申请号：US13303231
申请日：2011-11-23
申请人： Hong-Chen CHENG , Chia-En HUANG , Chih-Chieh CHIU , Jung-Ping YANG
发明人： Hong-Chen CHENG , Chia-En HUANG , Chih-Chieh CHIU , Jung-Ping YANG
IPC分类号： G11C11/34 , H03L5/00
CPC分类号： G11C8/10 , G11C11/413 , G11C11/418
摘要： An apparatus includes a level shifter and a switching circuit. The level shifter includes an input, a first output, and second output having a logic value complementary to a logic value of the first output. The switching circuit includes a data input, a feedback input coupled to the second output of the level shifter, and an output coupled to the input of the level shifter. The switching circuit is configured to selectively latch, based on a select signal, a logic state of the level shifter at the second output.
摘要翻译：一种装置包括电平移位器和开关电路。电平移位器包括具有与第一输出的逻辑值互补的逻辑值的输入，第一输出和第二输出。切换电路包括数据输入，耦合到电平移位器的第二输出的反馈输入以及耦合到电平移位器的输入的输出。开关电路被配置为基于选择信号选择性地锁存第二输出处的电平移位器的逻辑状态。

8. 发明申请

US20130010560A1 GENERATING AND AMPLIFYING DIFFERENTIAL SIGNALS 有权
标题翻译：生成和放大差分信号
公开(公告)号：US20130010560A1
公开(公告)日：2013-01-10
申请号：US13535075
申请日：2012-06-27
申请人： Chung-Ji LU , Hung-Jen LIAO , Cheng Hung LEE , Derek C. TAO , Annie-Li-Keow LUM , Hong-Chen CHENG
发明人： Chung-Ji LU , Hung-Jen LIAO , Cheng Hung LEE , Derek C. TAO , Annie-Li-Keow LUM , Hong-Chen CHENG
IPC分类号： H03F3/45 , G11C7/06
CPC分类号： G11C7/067 , G11C7/065
摘要： A circuit includes a first node, a second node, a first current mirror circuit, and a second current minor circuit. The first current mirror circuit has a reference end and a mirrored end. The reference end of the first current minor circuit is coupled to the first node, and the mirrored end of the first current minor circuit is coupled to the second node. The second current minor circuit has a reference end and a mirrored end. The reference end of the second current minor circuit is coupled to the second node, and the mirrored end of the second current minor circuit is coupled to the first node.
摘要翻译：电路包括第一节点，第二节点，第一电流镜电路和第二电流次要电路。第一电流镜电路具有参考端和镜像端。第一当前次要电路的参考端耦合到第一节点，并且第一当前次要电路的镜像端耦合到第二节点。第二个当前次级电路具有参考端和镜像端。第二电流次级电路的参考端耦合到第二节点，并且第二电流次级电路的镜像端耦合到第一节点。

9. 发明授权

US08279684B2 Method for extending word-line pulses 有权
标题翻译：扩展字线脉冲的方法
公开(公告)号：US08279684B2
公开(公告)日：2012-10-02
申请号：US12842189
申请日：2010-07-23
申请人： Hsu-Shun Chen , Cheng Hung Lee , Hong-Chen Cheng , Chung-Yi Wu
发明人： Hsu-Shun Chen , Cheng Hung Lee , Hong-Chen Cheng , Chung-Yi Wu
IPC分类号： G11C7/00
CPC分类号： G11C8/08 , G11C11/413
摘要： An integrated circuit includes a positive power supply node, a current tracking circuit, and a current mirroring circuit including a plurality of current paths coupled in parallel. The currents of the plurality of current paths mirror a current of the current tracking circuit. The current mirroring circuit is configured to turn off the plurality of current paths one-by-one in response to a reduction in a positive power supply voltage on the positive power supply node. The integrated circuit further includes a charging node receiving a summation current of the plurality of current paths, wherein a voltage on the charging node is configured to increase through a charging of the summation current.
摘要翻译：集成电路包括正电源节点，电流跟踪电路和包括并联耦合的多个电流路径的电流镜像电路。多个电流通路的电流反映了电流跟踪电路的电流。电流镜像电路被配置为响应于正电源节点上的正电源电压的减小而逐个关闭多个电流路径。集成电路还包括接收多个电流路径的求和电流的充电节点，其中充电节点上的电压被配置为通过对和电流的充电而增加。

10. 发明申请

US20120195139A1 MULTI-POWER DOMAIN DESIGN 有权
标题翻译：多功能域设计
公开(公告)号：US20120195139A1
公开(公告)日：2012-08-02
申请号：US13443619
申请日：2012-04-10
申请人： Hsu-Shun CHEN , Cheng Hung LEE , Chung-Ji LU , Hong-Chen CHENG , Chung-Yi WU , Chih-Chieh CHIU
发明人： Hsu-Shun CHEN , Cheng Hung LEE , Chung-Ji LU , Hong-Chen CHENG , Chung-Yi WU , Chih-Chieh CHIU
IPC分类号： G11C7/00 , G11C5/14
CPC分类号： G11C7/1048 , G11C5/14
摘要： In some embodiments related to a memory array, a sense amplifier (SA) uses a first power supply, e.g., voltage VDDA, while other circuitry, e.g., signal output logic, uses a second power supply, e.g., voltage VDDB. Various embodiments place the SA and a pair of transferring devices at a local IO row, and a voltage keeper at the main IO section of the same memory array. The SA, the transferring devices, and the voltage keeper, when appropriate, operate together so that the data logic of the circuitry provided by voltage VDDB is the same as the data logic of the circuitry provided by voltage VDDA.
摘要翻译：在与存储器阵列相关的一些实施例中，读出放大器（SA）使用第一电源，例如电压VDDA，而其它电路（例如，信号输出逻辑）使用第二电源，例如电压VDDB。各种实施例将SA和一对传送装置放置在本地IO行上，并将电压保持器放置在同一存储器阵列的主IO部分。 SA，传输装置和电压保持器在适当的情况下一起工作，使得由电压VDDB提供的电路的数据逻辑与由电压VDDA提供的电路的数据逻辑相同。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式