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1. 发明申请

US20110084755A1 ANALOG SWITCH 审中-公开
标题翻译：模拟开关
公开(公告)号：US20110084755A1
公开(公告)日：2011-04-14
申请号：US12971510
申请日：2010-12-17
申请人： Yoshitsugu Inagaki , Koji Oka , Toshiaki Ozeki , Takeshi Okumoto
发明人： Yoshitsugu Inagaki , Koji Oka , Toshiaki Ozeki , Takeshi Okumoto
IPC分类号： H03K17/687
CPC分类号： H03K17/16 , G11C27/024 , H03K2217/0018 , H03K2217/0036 , H03M1/1245
摘要： An analog switch (100) of the present invention is characterized by being constructed by MOS transistors and comprising a switch (102) connecting an input terminal VIN(104) and the substrate voltage of the NMOS transistor (101), a switch (103), being operated in a reverse phase to that of the switch (102), connecting the substrate voltage of the NMOS transistor(101) and the ground (VSS), and a voltage follower circuit (106) which, having a high input impedance and being connected between the input terminal (104) and the switch (102), suppresses the flow of the input current from the input terminal (104). According to the present invention, in an analog switch which is constituted by MOS transistors, it is possible to suppress that the input current flows into the substrate when the analog switch repeats the ON state and the OFF state.
摘要翻译：本发明的模拟开关（100）的特征在于由MOS晶体管构成，包括连接输入端子VIN（104）和NMOS晶体管（101）的衬底电压的开关（102），开关（103），与所述开关（102）的反相工作，连接所述NMOS晶体管（101）和所述地（VSS）的衬底电压，以及电压跟随器电路（106），所述电压跟随器电路具有高输入阻抗和连接在输入端（104）和开关（102）之间，抑制来自输入端（104）的输入电流的流动。根据本发明，在由MOS晶体管构成的模拟开关中，当模拟开关重复接通状态和断开状态时，可以抑制输入电流流入基板。

2. 发明授权

US07042278B2 Voltage reference circuit with reduced power consumption 失效
标题翻译：电压参考电路，功耗降低
公开(公告)号：US07042278B2
公开(公告)日：2006-05-09
申请号：US10844320
申请日：2004-05-13
申请人： Heiji Ikoma , Yoshitsugu Inagaki , Koji Oka
发明人： Heiji Ikoma , Yoshitsugu Inagaki , Koji Oka
IPC分类号： G05F3/02
CPC分类号： G11C5/147
摘要： A semiconductor integrated circuit is provided with a reference voltage generation circuit for generating a voltage to be a reference, a function circuit that is operated using an output voltage of the reference voltage generation circuit, and a reference voltage stabilization capacitor for stabilizing the output voltage, which is connected to an output terminal of the reference voltage generation circuit. During standby, the function circuit stops operating while the reference voltage generation circuit continues operating to prevent discharging of the reference voltage stabilization capacitor, thereby realizing reduction in power consumption of the function circuit such as an analog circuit as well as high-speed recovery from the standby state to the normal operation state.
摘要翻译：半导体集成电路设置有用于产生作为基准的电压的基准电压产生电路，使用参考电压产生电路的输出电压进行操作的功能电路和用于稳定输出电压的基准电压稳定电容器，其连接到参考电压产生电路的输出端子。在待机期间，功能电路在参考电压产生电路继续工作时停止工作，以防止参考稳压电容器的放电，从而实现诸如模拟电路的功能电路的功耗降低以及来自待机状态为正常运行状态。

3. 发明授权

US06806764B2 Reference voltage generation circuit 失效
标题翻译：参考电压发生电路
公开(公告)号：US06806764B2
公开(公告)日：2004-10-19
申请号：US10307446
申请日：2002-12-02
申请人： Yoshitsugu Inagaki , Koji Oka
发明人： Yoshitsugu Inagaki , Koji Oka
IPC分类号： G05F110
CPC分类号： G05F3/242 , G05F3/247
摘要： A start-up section is made up of an input transistor configured to receive at its gate a voltage at a node which varies with the magnitude of a current flowing in one branch of a current mirror in a reference voltage generation section, an inverter for reversing a drain voltage of the input transistor, an output transistor for supplying a start-up current to the reference voltage generation section in response to an output voltage from the inverter, and a current limit transistor serially connected to the input transistor. The current limit transistor receives a reduced gate-source voltage from the reference voltage generation section for limiting a flow of current in the input transistor upon completion of restarting the reference voltage generation section.
摘要翻译：启动部分由输入晶体管构成，该晶体管被配置为在其栅极处接收随着在参考电压产生部分中的电流镜的一个分支中流动的电流的大小而变化的节点的电压，用于反转的逆变器输入晶体管的漏极电压，用于响应于来自反相器的输出电压而向基准电压产生部分提供启动电流的输出晶体管，以及串联连接到输入晶体管的限流晶体管。电流限制晶体管从参考电压产生部分接收减小的栅极 - 源极电压，用于在重新启动参考电压产生部分时限制输入晶体管中的电流流动。

4. 发明授权

US06734817B2 A/D converter, method of A/D conversion, and signal processing device 失效
标题翻译： A / D转换器，A / D转换方法和信号处理装置
公开(公告)号：US06734817B2
公开(公告)日：2004-05-11
申请号：US10328159
申请日：2002-12-26
申请人： Junichi Naka , Yoshitsugu Inagaki , Hiroshi Sakura , Heiji Ikoma , Koji Oka , Youichi Okamoto , Daisuke Nomasaki
发明人： Junichi Naka , Yoshitsugu Inagaki , Hiroshi Sakura , Heiji Ikoma , Koji Oka , Youichi Okamoto , Daisuke Nomasaki
IPC分类号： H03M112
CPC分类号： H03M1/002 , H03M1/007 , H03M1/12
摘要： When the performance of an A/D converter required by a system changes, power consumption of the overall system can be reduced. The resolution of an A/D converter is made variable by changing a current flowing through an amplifier by an external control signal that specifies the resolution. Thus, when the performance required by a system changes, it is possible to change the performance of the A/D converter and to prevent a performance overhead of the A/D converter. Consequently, power consumption of the A/D converter is reduced, and power consumption of the system as a whole is also reduced.
摘要翻译：当系统所需的A / D转换器的性能改变时，可以降低整个系统的功耗。通过用指定分辨率的外部控制信号改变流过放大器的电流，可以使A / D转换器的分辨率可变。因此，当系统所需的性能改变时，可以改变A / D转换器的性能并且防止A / D转换器的性能开销。因此，A / D转换器的功耗降低，整个系统的功耗也降低。

5. 发明授权

US06310492B1 CMOS semiconductor integrated circuit 有权
标题翻译： CMOS半导体集成电路
公开(公告)号：US06310492B1
公开(公告)日：2001-10-30
申请号：US09561962
申请日：2000-05-01
申请人： Heiji Ikoma , Yoshitsugu Inagaki , Hiroyuki Konishi , Koji Oka , Akira Matsuzawa
发明人： Heiji Ikoma , Yoshitsugu Inagaki , Hiroyuki Konishi , Koji Oka , Akira Matsuzawa
IPC分类号： H03K190175
CPC分类号： H03K19/00361 , H03K19/0016 , H03K19/00315
摘要： In order to reduce power consumption, a power supply for a digital circuit portion is shut off, so that the output voltage of the power supply becomes the zero level. A CMOS (complementary metal oxide semiconductor) inverter has a P-channel FET (field effect transistor) with a gate electrode formed of P-type polysilicon. A source electrode of the P-channel FET is connected to the power supply and a back gate electrode of the P-channel FET is in direct connection with the aforesaid source electrode. The P-channel FET is placed in a state of not functioning as a transistor when the power supply is shut off in a low power consumption mode. However, in order to prevent the P-channel FET from undergoing characteristic degradation in that mode, there is the provision of a pull-down switch capable of fixing, in the mode, the voltage of the gate electrode of the P-channel FET at the zero level.
摘要翻译：为了降低功耗，关闭数字电路部分的电源，使得电源的输出电压变为零电平。 CMOS（互补金属氧化物半导体）反相器具有由P型多晶硅形成的栅电极的P沟道FET（场效应晶体管）。 P沟道FET的源电极连接到电源，P沟道FET的背栅极与前述源极直接连接。当在低功耗模式下关闭电源时，P沟道FET被置于不用作晶体管的状态。然而，为了防止P沟道FET在该模式中发生特性劣化，提供了一种下拉开关，其能够在该模式中固定P沟道FET的栅电极的电压零级。

6. 发明授权

US06700524B2 A/D converter for performing pipeline processing 失效
标题翻译：用于执行流水线处理的A / D转换器
公开(公告)号：US06700524B2
公开(公告)日：2004-03-02
申请号：US10256238
申请日：2002-09-27
申请人： Junichi Naka , Yoichi Okamoto , Yoshitsugu Inagaki , Kenji Murata , Koji Oka
发明人： Junichi Naka , Yoichi Okamoto , Yoshitsugu Inagaki , Kenji Murata , Koji Oka
IPC分类号： H03M138
CPC分类号： H03M1/007 , H03M1/0695 , H03M1/44
摘要： An A/D converter comprises a pipeline stage array in which plural pipeline stages are connected in series, each pipeline stage performing a pipeline operation on an inputted analog voltage to output a digital voltage; a number-of-bits control circuit for outputting a number-of-bits selection signal which indicates whether the operation of each pipeline stage should be carried out or halted, according to a number-of-bits control signal which indicates a resolution; and a correction circuit for compensating a digital value to be output, according to the number-of-bits control signal. Therefore, when resolution of the A/D converter, which is requested by the system, is changed, only the pipeline stages required for realizing the requested resolution are operated while the other pipeline stages are halted, whereby a reduction in power consumption of the A/D converter is realized and, simultaneously, a breakdown of an output from the A/D converter is avoided.
摘要翻译： A / D转换器包括一个其中多个流水线级串联连接的流水线阵列，每个流水线级对所输入的模拟电压进行流水线操作以输出数字电压; 根据指示分辨率的位数控制信号，输出指示每个流水线级的操作是否应被执行或停止的位数选择信号的位数控制电路; 以及根据位数控制信号补偿要输出的数字值的校正电路。因此，当系统请求的A / D转换器的分辨率改变时，仅在实现所请求的分辨率所需的流水线阶段在其它流水线级停止的同时被操作，从而降低了A / D转换器，同时避免了A / D转换器的输出故障。

7. 发明授权

US06498528B2 Reference voltage generation circuit 有权
标题翻译：参考电压发生电路
公开(公告)号：US06498528B2
公开(公告)日：2002-12-24
申请号：US09778066
申请日：2001-02-07
申请人： Yoshitsugu Inagaki , Koji Oka
发明人： Yoshitsugu Inagaki , Koji Oka
IPC分类号： G05F110
CPC分类号： G05F3/242 , G05F3/247
摘要： A start-up section is made up of an input transistor configured to receive at its gate a voltage at a node which varies with the magnitude of a current flowing in one branch of a current mirror in a reference voltage generation section, an inverter for reversing a drain voltage of the input transistor, an output transistor for supplying a start-up current to the reference voltage generation section in response to an output voltage from the inverter, and a current limit transistor serially connected to the input transistor. The current limit transistor receives a reduced gate-source voltage from the reference voltage generation section for limiting a flow of current in the input transistor upon completion of restarting the reference voltage generation section.
摘要翻译：启动部分由输入晶体管构成，该晶体管被配置为在其栅极处接收随着在参考电压产生部分中的电流镜的一个分支中流动的电流的大小而变化的节点的电压，用于反转的逆变器输入晶体管的漏极电压，用于响应于来自反相器的输出电压而向基准电压产生部分提供启动电流的输出晶体管，以及串联连接到输入晶体管的限流晶体管。电流限制晶体管从参考电压产生部分接收减小的栅极 - 源极电压，用于在重新启动参考电压产生部分时限制输入晶体管中的电流流动。

8. 发明授权

US06492849B2 Supply voltage detection circuit 有权
标题翻译：电源电压检测电路
公开(公告)号：US06492849B2
公开(公告)日：2002-12-10
申请号：US09820842
申请日：2001-03-30
申请人： Heiji Ikoma , Yoshitsugu Inagaki , Koji Oka
发明人： Heiji Ikoma , Yoshitsugu Inagaki , Koji Oka
IPC分类号： G05F308
CPC分类号： G11C5/143 , G11C5/14
摘要： A monitor circuit for supplying a detection voltage reflecting a supply voltage, a reference voltage generation circuit for generating a high-precision reference voltage not depending upon the supply voltage, and a comparator for comparing the detection voltage with the reference voltage and outputting the result of the comparison are provided and, in addition, a controller is provided which is made up of an auxiliary reference voltage generation circuit for generating a low-precision auxiliary reference voltage with less power dissipation and an auxiliary comparator for comparing the detection voltage with the auxiliary reference voltage. The auxiliary reference voltage is set higher than the reference voltage, and when the detection voltage becomes higher than the auxiliary reference voltage to cause the comparison output of the auxiliary comparator to become active, the reference voltage generation circuit is placed in a power-down state, thereby achieving a reduction in current dissipation.
摘要翻译：用于提供反映电源电压的检测电压的监视器电路，用于产生不依赖于电源电压的高精度参考电压的参考电压产生电路，以及用于将检测电压与参考电压进行比较的比较器，提供了比较，并且还提供了一种控制器，其由辅助参考电压产生电路组成，用于产生具有较少功耗的低精度辅助参考电压和用于将检测电压与辅助参考值进行比较的辅助比较器电压。辅助基准电压设定为高于参考电压，当检测电压变得高于辅助参考电压以使辅助比较器的比较输出变为有效时，基准电压产生电路处于掉电状态，从而实现电流消耗的减小。

9. 发明授权

US07884750B2 A/D converter and A/D conversion method 有权
标题翻译： A / D转换器和A / D转换方法
公开(公告)号：US07884750B2
公开(公告)日：2011-02-08
申请号：US12643613
申请日：2009-12-21
申请人： Toshiaki Ozeki , Daisuke Nomasaki , Koji Oka
发明人： Toshiaki Ozeki , Daisuke Nomasaki , Koji Oka
IPC分类号： H03M1/38
CPC分类号： H03M1/168
摘要： In an A/D converter provided with an A/D converter circuit 101 for operationally amplifying an input signal and outputting an amplified signal, the A/D converter circuit 101 includes an initial value setting circuit 4a in addition to an amplifier 1a, a sub-A/D converter 2a, a sub-D/A converter 3a and capacitors C11 and C12. To ensure that the initial value of the output voltage of the amplifier 1a is a given voltage value close to the target value of operational amplification at the start of the operational amplification by the amplifier 1a, the initial value setting circuit 4a applies a given bias value equal to the given voltage value close to the target value to a next-stage capacitor C13 to be connected to the output side of the amplifier 1a. Such an A/D converter circuit 101 that can perform speedy convergence to the target value of operational amplification is used at each stage of a pipeline A/D converter.
摘要翻译： A / D变换电路101具备A / D转换电路101，用于对输入信号进行运算放大并输出放大信号，A / D变换电路101除了具有放大器1a以外还包括初始值设定电路4a A / D转换器2a，子D / A转换器3a和电容器C11和C12。为了确保放大器1a的输出电压的初始值为放大器1a在工作放大开始时接近于工作放大的目标值的给定电压值，初始值设定电路4a施加给定的偏置值等于接近目标值的给定电压值连接到放大器1a的输出侧的下一级电容器C13。在流水线A / D转换器的各阶段使用能够对运算放大的目标值进行快速收敛的A / D转换电路101。

10. 发明申请

US20090040088A1 A/d Converter and A/D Conversion Method 失效
标题翻译： A / D转换器和A / D转换方法
公开(公告)号：US20090040088A1
公开(公告)日：2009-02-12
申请号：US11631844
申请日：2006-03-24
申请人： Toshiaki Ozeki , Daisuke Nomasaki , Koji Oka
发明人： Toshiaki Ozeki , Daisuke Nomasaki , Koji Oka
IPC分类号： H03M1/38
CPC分类号： H03M1/168
摘要： In an A/D converter provided with an A/D converter circuit 101 for operationally amplifying an input signal and outputting an amplified signal, the A/D converter circuit 101 includes an initial value setting circuit 4a in addition to an amplifier 1a, a sub-A/D converter 2a, a sub-D/A converter 3a and capacitors C11 and C12. To ensure that the initial value of the output voltage of the amplifier 1a is a given voltage value close to the target value of operational amplification at the start of the operational amplification by the amplifier 1a, the initial value setting circuit 4a applies a given bias value equal to the given voltage value close to the target value to a next-stage capacitor C13 to be connected to the output side of the amplifier 1a. Such an A/D converter circuit 101 that can perform speedy convergence to the target value of operational amplification is used at each stage of a pipeline A/D converter.
摘要翻译： A / D变换电路101具备A / D转换电路101，用于对输入信号进行运算放大并输出放大信号，A / D变换电路101除了具有放大器1a以外还包括初始值设定电路4a A / D转换器2a，子D / A转换器3a和电容器C11和C12。为了确保放大器1a的输出电压的初始值为放大器1a在工作放大开始时接近于工作放大的目标值的给定电压值，初始值设定电路4a施加给定的偏置值等于接近目标值的给定电压值连接到放大器1a的输出侧的下一级电容器C13。在流水线A / D转换器的各阶段使用能够对运算放大的目标值进行快速收敛的A / D转换电路101。

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