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    • 7. 发明授权
    • SRAM cell and SRAM device
    • SRAM单元和SRAM器件
    • US08040717B2
    • 2011-10-18
    • US12521408
    • 2007-12-20
    • Shinichi OuchiYongxun LiuMeishoku MasaharaTakashi MatsukawaKazuhiko Endo
    • Shinichi OuchiYongxun LiuMeishoku MasaharaTakashi MatsukawaKazuhiko Endo
    • G11C11/00
    • H01L27/1104H01L21/845H01L27/11H01L27/1211H01L29/785H01L29/7856
    • A static random access memory (SRAM) cell includes a first to a fourth semiconductor thin plate that are provided on a substrate and are arranged parallel to each other. On respective semiconductor thin plates, there is formed a first four-terminal double-gate field effect transistor (FET) with a first conductivity type, a second and a third four-terminal double-gate FET which are connected in series with each other and have a second conductivity type, a fourth and a fifth four-terminal double-gate FET which are connected in series with each other and have the second conductivity type, and a sixth four-terminal double-gate FET with the first conductivity type. The third and the fourth four-terminal double-gate FETs form select transistors, and the first, second, fifth and sixth four-terminal double-gate FETs form a complementary metal-oxide-semiconductor (CMOS) inverter.
    • 静态随机存取存储器(SRAM)单元包括设置在基板上并且彼此平行布置的第一至第四半导体薄板。 在相应的半导体薄板上形成具有第一导电类型的第一四端双栅场效应晶体管(FET),彼此串联连接的第二和第三四端双栅FET 具有彼此串联并具有第二导电类型的第二导电类型,第四和第五四端子双栅极FET以及具有第一导电类型的第六四端子双栅极FET。 第三和第四四端子双栅极FET形成选择晶体管,第一,第二,第五和第六四端子双栅极FET形成互补的金属氧化物半导体(CMOS)反相器。
    • 10. 发明申请
    • Activation signal output circuit and determining circuit
    • 激活信号输出电路和确定电路
    • US20060071654A1
    • 2006-04-06
    • US10536338
    • 2003-11-26
    • Kazuo MizunoRyu KimuraYoshiyuki KagoYukiomi TanakaKazuhiko EndoHisanori UdaHiroaki Hayashi
    • Kazuo MizunoRyu KimuraYoshiyuki KagoYukiomi TanakaKazuhiko EndoHisanori UdaHiroaki Hayashi
    • G01R25/00
    • H03D1/10H03D1/18
    • A start signal output circuit having an RF/DC conversion circuit to which radio frequency power (RF) of specified frequency is inputted and from which a direct current potential (DC) is outputted, comprises a detection/amplification circuit 210 which includes a voltage doubler wave-detector circuit 10 configured including a sensing diode Q1 (Tr34) for sensing the RF power, a differential amplifier including differential pair transistors Tr31 and Tr32, and a current mirror circuit. A base current of one Tr31 of the differential pair transistors is brought into substantial agreement with a DC component of a current flowing through the sensing diode Q1 (Tr34). A total of currents flowing through the differential pair transistors Tr31 and Tr32 is regulated to a substantially constant value by the current mirror circuit. Thus, the start signal output circuit which is small in size, high in sensitivity and low in power consumption can be realized.
    • 具有输入了特定频率的射频功率(RF)并从其输出直流电位(DC)的RF / DC转换电路的启动信号输出电路包括检测/放大电路210,其包括倍压器 波检测器电路10被配置为包括用于感测RF功率的感测二极管Q 1(Tr 34),包括差分对晶体管Tr 31和Tr 32的差分放大器和电流镜电路。 差分对晶体管的一个Tr 31的基极电流与流经感测二极管Q 1(Tr 34)的电流的直流分量基本一致。 流过差分对晶体管Tr 31和Tr 32的总电流通过电流镜电路被调节到基本恒定的值。 因此,可以实现尺寸小,灵敏度高,功耗低的启动信号输出电路。