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1. 发明授权

US5214296A Thin-film semiconductor device and method of fabricating the same 失效
标题翻译：薄膜半导体器件及其制造方法
公开(公告)号：US5214296A
公开(公告)日：1993-05-25
申请号：US848840
申请日：1992-03-10
申请人： Yoshiro Nakata , Naoto Matsuo , Toshiki Yabu , Susumu Matsumoto , Shozo Okada
发明人： Yoshiro Nakata , Naoto Matsuo , Toshiki Yabu , Susumu Matsumoto , Shozo Okada
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108 , H01L29/78 , H01L29/786
CPC分类号： H01L29/78642 , H01L27/10817
摘要： A thin-film semiconductor device having a vertical TFT which includes a gate insulating film formed on a sidewall of a throughhole formed in an insulating layer; a thin-film semiconductor layer formed on the gate insulating film; and a gate electrode formed within the insulating layer. The gate electrode, the gate insulating film, and the thin-film semiconductor layer together form a lateral MOS structure. The thin-film semiconductor layer is connected to a bit line at the bottom of the throughhole and to a storage node of a capacitor formed over the switching transistor.
摘要翻译：一种具有垂直TFT的薄膜半导体器件，其包括形成在绝缘层中形成的通孔的侧壁上的栅极绝缘膜; 形成在所述栅极绝缘膜上的薄膜半导体层; 以及形成在所述绝缘层内的栅电极。栅电极，栅极绝缘膜和薄膜半导体层一起形成横向MOS结构。薄膜半导体层连接到通孔底部的位线和形成在开关晶体管上的电容器的存储节点。

2. 发明授权

US5241201A Dram with concentric adjacent capacitors 失效
标题翻译：与同心相邻的电容器
公开(公告)号：US5241201A
公开(公告)日：1993-08-31
申请号：US678150
申请日：1991-04-02
申请人： Naoto Matsuo , Shozo Okada , Susumu Matsumoto , Yoshiro Nakata , Toshiki Yabu
发明人： Naoto Matsuo , Shozo Okada , Susumu Matsumoto , Yoshiro Nakata , Toshiki Yabu
IPC分类号： H01L27/108
CPC分类号： H01L27/10817
摘要： A new semiconductor memory device for performing a read/write of information of randomly accessed address includes a plurality of memory cells put in parallel arrays. Each memory cell includes a switching transistor region and a capacitor region. The capacitor regions of the two adjacent memory cells are formed in a common region over the switching transistor region of the two adjacent memory cells. The charge storage electrode of the capacitor region has the shape of a loop. The charge storage electrodes are formed by using self-alignment.
摘要翻译：用于执行随机访问地址的信息的读/写的新的半导体存储器件包括以并行阵列放置的多个存储单元。每个存储单元包括开关晶体管区域和电容器区域。两个相邻存储单元的电容器区域形成在两个相邻存储单元的开关晶体管区域上的公共区域中。电容器区域的电荷存储电极具有环形。电荷存储电极通过使用自对准形成。

3. 发明授权

US5399890A Semiconductor memory device in which a capacitor electrode of a memory cell and an interconnection layer of a peripheral circuit are formed in one level 失效
标题翻译：半导体存储器件，其中存储单元的电容器电极和外围电路的互连层形成在一个级中
公开(公告)号：US5399890A
公开(公告)日：1995-03-21
申请号：US257955
申请日：1994-06-10
申请人： Shozo Okada , Hisashi Ogawa , Naoto Matsuo , Yoshiro Nakata , Toshiki Yabu , Susumu Matsumoto
发明人： Shozo Okada , Hisashi Ogawa , Naoto Matsuo , Yoshiro Nakata , Toshiki Yabu , Susumu Matsumoto
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L21/8246 , H01L27/10 , H01L27/105 , H01L27/108 , H01L29/78
CPC分类号： H01L27/105 , H01L27/10808
摘要： A semiconductor memory of the invention includes a semiconductor substrate having a plurality of transistors, a plurality of stacked capacitors connected to portions of the plurality of transistors, a plurality of first level interconnection layers connected to other portions of the plurality of transistors, and a plurality of second level interconnection layers disposed above the stacked capacitors and the first level interconnection layers. Each of the plurality of stacked capacitors includes a first electrode layer, a capacitance insulating film formed on top of the first electrode layer, and a second electrode layer formed on top of the capacitance insulating film. The second electrode layer is connected to a portion of one of the plurality of second level interconnection layers. At least portions of the plurality of first level interconnection layers are connected to other portions of the plurality of second level interconnection layers. Each of the plurality of first level interconnection layers shares the same layer as at least one of the first electrode layer and the second electrode layer.
摘要翻译：本发明的半导体存储器包括具有多个晶体管的半导体衬底，与多个晶体管的一部分连接的多个叠层电容器，与多个晶体管的其它部分连接的多个第一级互连层，以及多个晶体管的多个位于层叠电容器和第一级互连层之上的第二级互连层。多个叠层电容器中的每一个包括第一电极层，形成在第一电极层顶部的电容绝缘膜，以及形成在电容绝缘膜顶部的第二电极层。第二电极层连接到多个第二级互连层之一的一部分。多个第一级互连层的至少一部分连接到多个第二级互连层的其它部分。多个第一级互连层中的每一个与第一电极层和第二电极层中的至少一个共享相同的层。

4. 发明授权

US5217914A Method for making semiconductor integration circuit with stacked capacitor cells 失效
标题翻译：具有层叠电容器单元的半导体积分电路的方法
公开(公告)号：US5217914A
公开(公告)日：1993-06-08
申请号：US683603
申请日：1991-04-10
申请人： Susumu Matsumoto , Toshiki Yabu , Yoshiro Nakata , Naoto Matsuo , Shozo Okada , Hiroyuki Sakai
发明人： Susumu Matsumoto , Toshiki Yabu , Yoshiro Nakata , Naoto Matsuo , Shozo Okada , Hiroyuki Sakai
IPC分类号： H01L21/02 , H01L21/8242
CPC分类号： H01L27/10852 , H01L28/91
摘要： Disclosed is a semiconductor integrating circuit having stacked capacitor cells. Each of the cells includes an electric charge storage electrode for storing an electric charge, and a capacitor insulation film and opposite plate electrode integrated thereon. The electric charge storage electrode consists essentially of a bottom and a part in at least double frame-like portion or at least one column-like portion and at least one frame-like portion surrounding the column-like portion rising upwardly from the bottom surface. The capacitor deposited film consists of a dielectric material film deposited on all of the bottom plane and all surfaces of the charge storage electrode, and constructs a capacitor in cooperation with the opposite plate electrode. The described method for making a stacked capacitor cell can make it possible to form self-aligned capacitors by repeating a deposition of an oxide film and a conductive film and an anisotropic etching.
摘要翻译：公开了具有层叠电容器单元的半导体积分电路。每个单元包括用于存储电荷的电荷存储电极，以及集成在其上的电容器绝缘膜和相对的平板电极。电荷存储电极基本上由至少双框状部分或至少一个柱状部分中的底部和部分组成，以及围绕从底面向上升起的柱状部分的至少一个框状部分。电容器沉积膜由沉积在电荷存储电极的所有底面和所有表面上的介电材料膜构成，并与相对的板电极配合构建电容器。所述制造叠层电容器电池的方法可以通过重复氧化膜和导电膜的沉积以及各向异性蚀刻来形成自对准电容器。

5. 发明授权

US5315543A Semiconductor memory device and a manufacturing method thereof 失效
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US5315543A
公开(公告)日：1994-05-24
申请号：US882064
申请日：1992-05-12
申请人： Naoto Matsuo , Hisashi Ogawa , Yoshiro Nakata , Shozo Okada
发明人： Naoto Matsuo , Hisashi Ogawa , Yoshiro Nakata , Shozo Okada
IPC分类号： H01L27/108 , G11C13/00
CPC分类号： H01L27/10829
摘要： A semiconductor memory device includes a single crystalline semiconductor substrate having a main surface, a plurality of active regions formed at the main surface, and an isolation region which is formed at the main surface and isolates the active regions from one another. Each of the active regions has a transistor region and a capacitor region. The capacitor region has a trench formed in the single crystalline semiconductor substrate. An inner wall of the trench is covered with an insulating layer. At least a portion of the transistor region and the insulating layer are both covered with a semiconductor layer. A portion of the semiconductor layer which covers at least the portion of the transistor region is an epitaxial layer. A portion of the semiconductor layer which covers the insulating layer is a polycrystalline layer, which functions as a storage node of a capacitor. A semiconductor memory device is manufactured by forming an isolation region for isolating a plurality of active regions from one another at a main surface of a single crystalline semiconductor substrate, forming a trench in at least a portion of the active regions of the single crystalline semiconductor substrate, covering an inner wall of the trench with an insulating layer, forming a polysilicon seed film on the insulating layer, and growing a single crystalline silicon layer and a polysilicon layer respectively on an exposed portion of the top surface of the single crystalline semiconductor substrate and on the polysilicon seed film simultaneously and selectively.
摘要翻译：半导体存储器件包括具有主表面，形成在主表面上的多个有源区的单晶半导体衬底和形成在主表面处的隔离区，并且将有源区彼此隔离。每个有源区具有晶体管区和电容区。电容器区域具有在单晶半导体衬底中形成的沟槽。沟槽的内壁被绝缘层覆盖。晶体管区域和绝缘层的至少一部分都被半导体层覆盖。覆盖晶体管区域的至少一部分的半导体层的一部分是外延层。覆盖绝缘层的半导体层的一部分是用作电容器的存储节点的多晶层。半导体存储器件通过在单晶半导体衬底的主表面上形成用于隔离多个有源区彼此的隔离区域而形成，在单晶半导体衬底的至少一部分有源区中形成沟槽用绝缘层覆盖沟槽的内壁，在绝缘层上形成多晶硅种子膜，分别在单晶半导体衬底的顶表面的暴露部分上生长单晶硅层和多晶硅层，以及同时和选择性地在多晶硅种子膜上。

6. 发明授权

US5300814A Semiconductor device having a semiconductor substrate with reduced step between memory cells 失效
标题翻译：半导体器件具有在存储单元之间具有减小的步骤的半导体衬底
公开(公告)号：US5300814A
公开(公告)日：1994-04-05
申请号：US915898
申请日：1992-07-17
申请人： Susumu Matsumoto , Shin Hashimoto , Toshio Yamada , Yoshiro Nakata
发明人： Susumu Matsumoto , Shin Hashimoto , Toshio Yamada , Yoshiro Nakata
IPC分类号： H01L21/768 , H01L21/8242 , H01L23/522 , H01L23/528 , H01L27/10 , H01L27/105 , H01L27/108 , H01L23/48 , H01L29/46
CPC分类号： H01L27/105 , H01L23/522 , H01L23/5226 , H01L23/528 , H01L2924/0002 , Y10S257/92
摘要： A semiconductor device comprising a semiconductor substrate, a plurality of memory cell regions each having a plurality of memory cells disposed on the semiconductor substrate, a word line formed in a first level above the semiconductor substrate, a bit line formed in a second level above the first level, and a backing line having a lower resistance than the word line and formed in a third level above the second level. A dummy bit line is formed in the second level outside the memory cell region so as to reduce the step formed at the periphery of the memory cell region. The dummy bit line is also used to interconnect the word line and the backing line so that an electrical connection therebetween is stabilized.
摘要翻译：一种半导体器件，包括半导体衬底，多个存储单元区域，每个存储单元区域具有设置在半导体衬底上的多个存储单元，形成在半导体衬底上方的第一级中的字线，形成在第二级上方的位线第一级和背衬线，其具有比字线更低的电阻并且形成在高于第二级的第三级中。在存储单元区域外部的第二电平中形成虚拟位线，以便减小形成在存储单元区域周边的台阶。虚拟位线也用于互连字线和背衬线，使得它们之间的电连接稳定。

7. 发明授权

US06297658B1 Wafer burn-in cassette and method of manufacturing probe card for use therein 有权
标题翻译：晶片老化盒及其制造方法
公开(公告)号：US06297658B1
公开(公告)日：2001-10-02
申请号：US09176194
申请日：1998-10-21
申请人： Yoshiro Nakata , Shinichi Oki
发明人： Yoshiro Nakata , Shinichi Oki
IPC分类号： G01R3128
CPC分类号： G01R1/0735 , G01R1/0491
摘要： A wafer tray has a wafer mount portion for carrying a semiconductor wafer formed with a plurality of semiconductor chips. A probe card composed of an elastic material and disposed in opposing relation to the wafer mount portion of the wafer tray has bumps to be connected to the respective electrode pads of the semiconductor chips on the top surface thereof. A holding board is provided to hold the back surface of the probe card. An annular sealing member is disposed on the wafer tray externally of the wafer mount portion and defines a first sealed space in combination with the wafer tray and the probe card. The probe card has connection holes for connecting the first sealed space to a second sealed space formed between the probe card and the holding board.
摘要翻译：晶片托盘具有用于承载形成有多个半导体芯片的半导体晶片的晶片安装部分。由弹性材料构成并且与晶片托盘的晶片安装部分相对设置的探针卡片具有与其顶表面上的半导体芯片的各个电极焊盘连接的凸块。提供保持板以保持探针卡的背面。环形密封构件设置在晶片托盘外部的晶片安装部分上，并且与晶片托盘和探针卡组合形成第一密封空间。探针卡具有用于将第一密封空间连接到形成在探针卡和保持板之间的第二密封空间的连接孔。

8. 发明授权

US06229329B1 Method of testing electrical characteristics of multiple semiconductor integrated circuits simultaneously 有权
标题翻译：同时测试多个半导体集成电路的电气特性的方法
公开(公告)号：US06229329B1
公开(公告)日：2001-05-08
申请号：US09140323
申请日：1998-08-26
申请人： Yoshiro Nakata , Shinichi Oki
发明人： Yoshiro Nakata , Shinichi Oki
IPC分类号： G01R102
CPC分类号： G01R31/2886
摘要： A method of testing semiconductor integrated circuits comprises the step of simultaneously testing a plurality of semiconductor integrated circuit elements for electric characteristics by applying a voltage to the respective testing electrodes of the semiconductor integrated circuit elements. The simultaneous testing step includes the step of applying the voltage to the respective testing electrodes of the semiconductor integrated circuit elements via PTC elements provided for the semiconductor integrated circuit elements in a one-to-one relationship.
摘要翻译：一种测试半导体集成电路的方法包括通过向半导体集成电路元件的各个测试电极施加电压来同时测试用于电特性的多个半导体集成电路元件的步骤。同时测试步骤包括以一对一的关系将电压施加到半导体集成电路元件的各个测试电极的PTC元件。

9. 发明授权

US06781400B2 Method of testing semiconductor integrated circuits and testing board for use therein 有权
标题翻译：半导体集成电路测试方法及其中使用的测试板
公开(公告)号：US06781400B2
公开(公告)日：2004-08-24
申请号：US10322571
申请日：2002-12-19
申请人： Yoshiro Nakata , Shinichi Oki
发明人： Yoshiro Nakata , Shinichi Oki
IPC分类号： G01R3102
CPC分类号： G01R31/2886
摘要： A method of testing semiconductor integrated circuits comprises the step of simultaneously testing a plurality of semiconductor integrated circuit elements for electric characteristics by applying a voltage to the respective testing electrodes of the semiconductor integrated circuit elements. The simultaneous testing step includes the step of applying the voltage to the respective testing electrodes of the semiconductor integrated circuit elements via PTC elements provided for the semiconductor integrated circuit elements in a one-to-one relationship.
摘要翻译：一种测试半导体集成电路的方法包括通过向半导体集成电路元件的各个测试电极施加电压来同时测试用于电特性的多个半导体集成电路元件的步骤。同时测试步骤包括以一对一的关系将电压施加到半导体集成电路元件的各个测试电极的PTC元件。

10. 发明授权

US06518779B1 Probe card 有权
标题翻译：探针卡
公开(公告)号：US06518779B1
公开(公告)日：2003-02-11
申请号：US09174536
申请日：1998-10-19
申请人： Yoshiro Nakata , Shinichi Oki , Masaaki Ishizaka
发明人： Yoshiro Nakata , Shinichi Oki , Masaaki Ishizaka
IPC分类号： G01R3102
CPC分类号： G01R1/07314
摘要： A probe card is used in testing an electric characteristic of plural semiconductor chips formed on a semiconductor wafer in a batch at a wafer level through application of a voltage to electrodes of the semiconductor chips. The probe card includes a card body, plural probe terminals, a wiring and a control element. The plural probe terminals are disposed on one surface of the card body in positions corresponding to the electrodes of the semiconductor chips. The wiring is disposed on the other surface of the card body and electrically connected with the probe terminals. The control element is disposed on the latter surface of the card body between the wiring and the probe terminals and controls input/output of the semiconductor chips.
摘要翻译：探针卡用于通过向半导体芯片的电极施加电压来测试在晶片级别批量形成在半导体晶片上的多个半导体芯片的电特性。探针卡包括卡体，多个探针端子，布线和控制元件。多个探针端子被配置在卡体的与半导体芯片的电极对应的位置的一个面上。布线布置在卡体的另一个表面上并与探针端子电连接。控制元件设置在布线与探针端子之间的卡体的后表面上，并且控制半导体芯片的输入/输出。

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