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1. 发明授权

US4811213A Vector processor with vector registers 失效
标题翻译：带向量寄存器的向量处理器
公开(公告)号：US4811213A
公开(公告)日：1989-03-07
申请号：US918003
申请日：1986-10-14
申请人： Yoshio Takamine , Takayuki Nakagawa , Yoshiharu Kazama , Yoshiaki Kinoshita , Shunsuke Miyamoto
发明人： Yoshio Takamine , Takayuki Nakagawa , Yoshiharu Kazama , Yoshiaki Kinoshita , Shunsuke Miyamoto
IPC分类号： G06F17/16 , G06F15/78 , G06F15/347
CPC分类号： G06F15/8084
摘要： In response to the execution of a single loading instruction, the front half and the rear half of a designated vector may be stored in respective vector registers in a single processor operation. For this purpose, a data distribution circuit is interposed between a group of vector registers and a vector data storage for feeding the vector data read out from the storage to a first vector processor designated by an instruction without shifting and for shifting the respective components of the read-out vector data and feeding the shifted components to a second vector register designated by the instruction.
摘要翻译：响应于单个加载指令的执行，指定向量的前半部分和后半部分可以在单个处理器操作中存储在相应的向量寄存器中。为此，在一组向量寄存器和向量数据存储器之间插入数据分配电路，用于将从存储器读出的向量数据馈送到由指令指定的第一向量处理器，而不需要移位，并且用于将读出向量数据并将移位的分量馈送到由指令指定的第二向量寄存器。

2. 发明授权

US4899273A Circuit simulation method with clock event suppression for debugging LSI circuits 失效
标题翻译：用于调试LSI电路的时钟事件抑制的电路仿真方法
公开(公告)号：US4899273A
公开(公告)日：1990-02-06
申请号：US940539
申请日：1986-12-10
申请人： Koichiro Omoda , Shunsuke Miyamoto , Takayuki Nakagawa , Yoshio Takamine , Shigeo Nagashima , Masayuki Miyoshi , Yoshiharu Kazama , Yoshiaki Kinoshita
发明人： Koichiro Omoda , Shunsuke Miyamoto , Takayuki Nakagawa , Yoshio Takamine , Shigeo Nagashima , Masayuki Miyoshi , Yoshiharu Kazama , Yoshiaki Kinoshita
IPC分类号： G06F17/16 , G01R31/317 , G01R31/3173 , G06F17/50 , G06F19/00
CPC分类号： G06F17/5022 , G01R31/31705 , G01R31/3173
摘要： A computer implemented logic simulation method, for inspecting logical operations of large scale logic circuits, computes a variation of an output of at least one latch in a clock synchronized logic circuit. The clock-synchronized logic circuit contains a combination logic circuit and a plurality of logic gates. Each of the logic gates have at least one input signal and several other inputs connected to clocking signal sources of different phases. The latch is activated by the rise or fall of the clock signals for holding the output from the combination logic circuit. The method thus implements sampling instants of the output for ascertaining the logical operations of the large scale circuits.
摘要翻译：一种用于检查大规模逻辑电路的逻辑运算的计算机实现的逻辑模拟方法，计算时钟同步逻辑电路中至少一个锁存器的输出的变化。时钟同步逻辑电路包含组合逻辑电路和多个逻辑门。每个逻辑门具有至少一个输入信号和几个其他输入，其连接到不同相位的时钟信号源。锁存器由用于保持组合逻辑电路的输出的时钟信号的上升或下降而被激活。因此，该方法实现了输出的采样时刻，以确定大规模电路的逻辑运算。

3. 发明授权

US5051941A Method and apparatus for logical simulation 失效
标题翻译：逻辑仿真的方法和装置
公开(公告)号：US5051941A
公开(公告)日：1991-09-24
申请号：US478511
申请日：1990-02-12
申请人： Yoshio Takamine , Shunsuke Miyamoto , Takayuki Nakagawa , Yoshiharu Kazama , Yoshiaki Kinoshita
发明人： Yoshio Takamine , Shunsuke Miyamoto , Takayuki Nakagawa , Yoshiharu Kazama , Yoshiaki Kinoshita
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： A method of logic simulation for simulating operation of a logic circuit by using basic signal values corresponding to states of output signals of elements of the logic circuit to be simulated and expanded signal values including the basic signal values. The logic circuit to be simulated is divided into a portion to be simulated by using the basic signal values and the expanded signal values and a portion to be simulated by using the basic signal values without using the expanded signal values. The elements for which definition of calculation method for output signal values for the input signal values including the expanded signal values is not easy are included in the latter portion, and other elements are included in the former portion. A virtual signal conversion element for converting the expanded signal into the basic signal is provided at a position where a signal is sent from the former portion to the latter portion so that the expanded signal value outputted from the element of the former portion is converted into the basic signal value before it is sent to the element of the latter portion.
摘要翻译：一种逻辑仿真方法，用于通过使用与要被仿真的逻辑电路的元件的输出信号的状态对应的基本信号值和包括基本信号值的扩展信号值来模拟逻辑电路的操作。要模拟的逻辑电路通过使用基本信号值和扩展信号值以及通过使用基本信号值而不使用扩展信号值而要被仿真的部分来划分为要被模拟的部分。对于包括扩展信号值的输入信号值的输出信号值的计算方法的定义不容易的元件包括在后一部分中，并且其它元件包括在前一部分中。将扩展信号转换为基本信号的虚拟信号转换元件设置在信号从前一部分发送到后一部分的位置，使得从前一部分的元件输出的扩展信号值被转换为基本信号值被发送到后一部分的元素之前。

4. 发明授权

US4773006A Vector operation designator 失效
标题翻译：矢量操作指示器
公开(公告)号：US4773006A
公开(公告)日：1988-09-20
申请号：US813007
申请日：1985-12-24
申请人： Yoshiaki Kinoshita , Yoshiharu Kazama , Shunsuke Miyamoto , Koichiro Omoda , Takayuki Nakagawa
发明人： Yoshiaki Kinoshita , Yoshiharu Kazama , Shunsuke Miyamoto , Koichiro Omoda , Takayuki Nakagawa
IPC分类号： G06F17/16 , G06F15/78 , G06F7/48 , G06F3/00
CPC分类号： G06F15/8053
摘要： In a vector processor for performing an operation on first and second vectors for each vector element, an operation code is set for each vector element of at least one of the first and second vectors to designate the type of an operation to be executed on the vector element, and the operation is carried out on the first and second vectors for each vector element based on the operation code.
摘要翻译：在用于对每个向量元素执行对第一和第二向量的操作的向量处理器中，为第一和第二向量中的至少一个矢量的每个矢量元素设置操作码，以指定要在矢量上执行的操作的类型元素，并且基于操作代码对每个向量元素的第一和第二向量执行操作。

5. 发明授权

US4933839A Vector processor 失效
标题翻译：矢量处理器
公开(公告)号：US4933839A
公开(公告)日：1990-06-12
申请号：US79047
申请日：1987-07-29
申请人： Yoshiaki Kinoshita , Yoshiharu Kazama , Yoshio Takamine
发明人： Yoshiaki Kinoshita , Yoshiharu Kazama , Yoshio Takamine
IPC分类号： G06F7/00 , G06F7/02 , G06F7/76 , G06F15/78 , G06F17/16
CPC分类号： G06F15/8053 , G06F7/02
摘要： A vector processor has a discriminator for determining in one machine cycle of an operation unit whether a bit pattern of elements of vector data meets a predetermined condition or not. An output of a register having a predetermined value loaded only into bits to be extracted from the vector data and each of the elements of the vector data are ANDed or ORed so that the bit pattern is determined. The operation and determination are sequentially carried out in one machine cycle.
摘要翻译：矢量处理器具有用于在操作单元的一个机器周期中确定矢量数据的元素的位模式是否满足预定条件的鉴别器。具有预定值的寄存器的输出仅被加载到从矢量数据提取的比特中，并且向量数据的每个元素进行“或”运算，以便确定比特模式。操作和确定在一个机器周期中依次进行。

6. 发明授权

US4897801A Display terminal equipment with concurrently operable plural input devices 失效
标题翻译：具有可同时操作的多个输入装置的显示终端设备
公开(公告)号：US4897801A
公开(公告)日：1990-01-30
申请号：US85768
申请日：1987-08-17
申请人： Yoshiharu Kazama , Motonobu Nagafuji
发明人： Yoshiharu Kazama , Motonobu Nagafuji
IPC分类号： G06F3/048 , G06F3/023 , G06F3/14 , G09G5/14
CPC分类号： G09G5/14 , G06F3/0489
摘要： In a display terminal equipment, a display device and a plurality of input devices are connected to a controller. Each input device is operated by an operator for inputting information. The controller controls the information entered from a different input device to be displayed on a different display area of the display device. It becomes possible for a plurality of operators to share a single display device and a single display terminal equipment while handling his or her own input device at the same time.
摘要翻译：在显示终端设备中，显示设备和多个输入设备连接到控制器。每个输入设备由操作者操作以输入信息。控制器控制从不同输入设备输入的信息，以显示在显示设备的不同显示区域上。在同时处理他或她自己的输入设备的同时，多个操作者可以共享单个显示设备和单个显示终端设备。

7. 发明授权

US4995037A Adjustment method and apparatus of a computer 失效
标题翻译：计算机的调整方法和装置
公开(公告)号：US4995037A
公开(公告)日：1991-02-19
申请号：US192521
申请日：1988-05-11
申请人： Toyohisa Imada , Yoshiharu Kazama
发明人： Toyohisa Imada , Yoshiharu Kazama
IPC分类号： G06F11/22 , G06F11/26
CPC分类号： G06F11/2273 , G06F11/261
摘要： A method and apparatus for providing data for adjusting an electronic computer having a main storage unit, in a system including a service processor connected to the electronic computer to maintain the same, and an external storage unit for storing data of internal registers of the electronic computer, which are read out by the service processor. An adjusting program is executed by the electronic computer until a logical failure is detected in the electronic computer to be adjusted. Once the logical failure is detected, execution is stopped at an instruction an arbitrary number of instruction before the instruction on which the failure was detected. Thereafter, the electronic computer is caused to re-execute the adjusting program. Data of internal registers and the main storage unit of the electronic computer is stored in the eternal storage unit through the service processor when the electronic computer stops execution of the adjusting program. A previously adjusted electronic computer is loaded with the data of the external storage unit and is caused to execute a simulation of the electronic computer using a similation model of the electronic computer to determine the state of the internal registers of the electronic computer in the model.
摘要翻译：一种用于提供用于调整具有主存储单元的电子计算机的数据的方法和装置，包括连接到电子计算机以维持其的服务处理器的系统以及用于存储电子计算机的内部寄存器的数据的外部存储单元，由服务处理器读出。由电子计算机执行调整程序，直到检测到电子计算机中的逻辑故障被调整为止。一旦检测到逻辑故障，则在检测到故障的指令之前，在任意数量的指令的指令处停止执行。此后，使电子计算机重新执行调整程序。当电子计算机停止执行调整程序时，内部寄存器和电子计算机的主存储单元的数据通过服务处理器存储在永久存储单元中。先前调整的电子计算机装载有外部存储单元的数据，并且使用电子计算机的模拟模型来执行电子计算机的模拟，以确定模型中的电子计算机的内部寄存器的状态。

8. 发明授权

US4922445A Logic circuit simulation method 失效
标题翻译：逻辑电路仿真方法
公开(公告)号：US4922445A
公开(公告)日：1990-05-01
申请号：US128584
申请日：1987-12-04
申请人： Yoshito Mizoue , Yoshiharu Kazama
发明人： Yoshito Mizoue , Yoshiharu Kazama
IPC分类号： G06F11/25 , G06F17/50
CPC分类号： G06F17/5022
摘要： A logic circuit simulation method for simulating a logic circuit including a plurality of logic blocks, in which after having simulated the whole simulation object logic circuit, signal variation information of an arbitrary logic block is taken out from the simulation result, the information thus taken out is given to the logic blocks, and a renewed simulation is executed for every logic block.
摘要翻译：一种用于模拟包括多个逻辑块的逻辑电路的逻辑电路仿真方法，其中在仿真整个仿真对象逻辑电路之后，从仿真结果中取出任意逻辑块的信号变化信息，从而取出信息被给予逻辑块，并且对于每个逻辑块执行更新的仿真。

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