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1. 发明授权

US06384593B1 Semiconductor device testing apparatus 失效
标题翻译：半导体器件测试仪器
公开(公告)号：US06384593B1
公开(公告)日：2002-05-07
申请号：US09596062
申请日：2000-06-16
申请人： Yoshihito Kobayashi , Tsuyoshi Yamashita , Hiroto Nakamura , Shin Nemoto , Yoshiyuki Masuo , Akihiko Ito
发明人： Yoshihito Kobayashi , Tsuyoshi Yamashita , Hiroto Nakamura , Shin Nemoto , Yoshiyuki Masuo , Akihiko Ito
IPC分类号： G01R3128
CPC分类号： G01R31/2868
摘要： A semiconductor device testing apparatus having a reduced transverse width and compact in size is provided. Adjacent to a constant temperature chamber containing therein a vertical transport means is located a test chamber which is in turn adjoined by a temperature-stress removing chamber likewise containing therein a vertical transport means, so that the constant temperature chamber and the test chamber are arranged transversely in a line, while the temperature-stress removing chamber is located in front of the test chamber when viewed in front view of the apparatus. Further, a loader section is located in front of the constant temperature chamber, and an unloader section is located above the temperature-stress removing chamber. With this arrangement, the transverse width of the testing apparatus may be reduced to about two test tray lengths.
摘要翻译：提供了具有减小的横向宽度并且尺寸紧凑的半导体器件测试装置。在其中容纳有垂直输送装置的恒温室附近设有试验室，该试验室又由同样含有垂直输送装置的温度应力消除室邻接，使得恒温室和试验室横向布置在该装置的正视图中观察时，温度应力消除室位于测试室的前方。此外，装载部位于恒温室前方，卸载部位于温度应力消除室的上方。通过这种布置，测试装置的横向宽度可以减小到大约两个测试托盘长度。

2. 发明授权

US6104183A Semiconductor device testing apparatus 失效
标题翻译：半导体器件测试仪器
公开(公告)号：US6104183A
公开(公告)日：2000-08-15
申请号：US809243
申请日：1997-05-28
申请人： Yoshihito Kobayashi , Tsuyoshi Yamashita , Hiroto Nakamura , Shin Nemoto , Yoshiyuki Masuo , Akihiko Ito
发明人： Yoshihito Kobayashi , Tsuyoshi Yamashita , Hiroto Nakamura , Shin Nemoto , Yoshiyuki Masuo , Akihiko Ito
IPC分类号： G01R31/26 , G01R31/28 , H01L21/677
CPC分类号： G01R31/2868
摘要： A semiconductor device testing apparatus having a reduced transverse width and compact in size is provided. Adjacent to a constant temperature chamber 101 containing therein a vertical transport means is located a test chamber 102 which is in turn adjoined by a temperature-stress removing chamber 103 likewise containing therein a vertical transport means, so that the constant temperature chamber 101, the test chamber 102 and the temperature-stress removing chamber 103 are arranged transversely in a line. Further, a loader section 300 is located in front of the constant temperature chamber, and an unloader section 400 is located in front of the test chamber and the temperature-stress removing chamber. With this arrangement, the transverse width of the testing apparatus may be reduced to about three test tray lengths.
摘要翻译： PCT No.PCT / JP96 / 02067 Sec。 371日期1997年5月28日 102（e）日期1997年5月28日PCT提交1996年7月24日PCT公布。出版物WO97 / 05495 日期：1997年2月13日提供了具有减小的横向宽度和尺寸紧凑的半导体器件测试装置。在其中容纳有垂直传送装置的恒温室101附近设置有测试室102，测试室102又由同样包含垂直传送装置的温度应力消除室103邻接，使得恒温室101，测试室102和温度应力消除室103横向排列成一行。此外，装载部300位于恒温室前方，卸载部400位于试验室前方和温度应力消除室。通过这种布置，测试装置的横向宽度可以减小到约三个测试托盘长度。

3. 发明授权

US06459259B1 Tester for semiconductor devices and test tray used for the same 失效
标题翻译：用于半导体器件和测试托盘的测试仪用于相同
公开(公告)号：US06459259B1
公开(公告)日：2002-10-01
申请号：US09254084
申请日：1999-02-26
申请人： Akihiko Ito , Yoshihito Kobayashi , Yoshiyuki Masuo , Tsuyoshi Yamashita
发明人： Akihiko Ito , Yoshihito Kobayashi , Yoshiyuki Masuo , Tsuyoshi Yamashita
IPC分类号： B65G4300
CPC分类号： G01R31/2893 , G01R31/01 , G01R31/2851 , G01R31/2867
摘要： An IC tester which is capable of reducing the time required before completion of testing on all of ICs to be tested is provided. The depth (length in the Y-axis direction) of the constant temperature chamber 4 and the exit chamber 5 is expanded by a dimension corresponding approximately to one transverse width (length of the minor edge) of the rectangular test tray 3, and two generally parallel test tray transport paths or alternatively a widened test tray transport path broad enough to transport two test trays simultaneously with the two test trays juxtaposed in a direction transverse to the widened test tray transport path are provided in the section of test tray transport path extending from the soak chamber 41 in the constant temperature chamber 4 through the testing section 42 in the constant temperature chamber 4 to the exit chamber 5 so that two test trays may be simultaneously transported along the two test tray transport paths or the widened test tray transport path.
摘要翻译：提供了一种能够在所有要测试的IC上测试完成之前减少所需时间的IC测试器。恒温室4和出口室5的深度（Y轴方向的长度）以相当于矩形试验盘3的一个横向宽度（小边的长度）的尺寸扩大，平行的测试托盘传送路径或者可选地，加宽的测试托盘传送路径足够宽以与横向于加宽的测试托盘传送路径的方向并置的两个测试托盘同时传送两个测试托盘设置在从托盘传送路径延伸的部分恒温室4中的浸泡室41通过恒温室4中的检测部分42到出口室5，从而沿着两个试纸盘传送路径或加宽的试纸盘传送路径同时传送两个试纸盘。

4. 发明授权

US06856128B2 Semiconductor device testing apparatus and a test tray for use in the testing apparatus 有权
标题翻译：半导体器件测试装置和用于测试装置的测试托盘
公开(公告)号：US06856128B2
公开(公告)日：2005-02-15
申请号：US09964211
申请日：2001-09-25
申请人： Akihiko Ito , Yoshihito Kobayashi , Yoshiyuki Masuo , Tsuyoshi Yamashita
发明人： Akihiko Ito , Yoshihito Kobayashi , Yoshiyuki Masuo , Tsuyoshi Yamashita
IPC分类号： G01R31/01 , G01R31/28 , B65G43/00
CPC分类号： G01R31/2893 , G01R31/01 , G01R31/2851 , G01R31/2867
摘要： An IC tester which is capable of reducing the time required before completion of testing on all of ICs to be tested is provided. The depth (length in the Y-axis direction) of the constant temperature chamber 4 and the exit chamber 5 is expanded by a dimension corresponding approximately to one transverse width (length of the minor edge) of the rectangular test tray 3, and two generally parallel test tray transport paths or alternatively a widened test tray transport path broad enough to transport two test trays simultaneously with the two test trays juxtaposed in a direction transverse to the widened test tray transport path are provided in the section of test tray transport path extending from the soak chamber 41 in the constant temperature chamber 4 through the testing section 42 in the constant temperature chamber 4 to the exit chamber 5 so that two test trays may be simultaneously transported along the two test tray transport paths or the widened test tray transport path.
摘要翻译：提供了一种能够在所有要测试的IC上测试完成之前减少所需时间的IC测试器。恒温室4和出口室5的深度（Y轴方向的长度）以相当于矩形试验盘3的一个横向宽度（小边的长度）的尺寸扩大，平行的测试托盘传送路径或者可选地，加宽的测试托盘传送路径足够宽以与横向于加宽的测试托盘传送路径的方向并置的两个测试托盘同时传送两个测试托盘设置在从托盘传送路径延伸的部分恒温室4中的浸泡室41通过恒温室4中的检测部分42到出口室5，从而沿着两个试纸盘传送路径或加宽的试纸盘传送路径同时传送两个试纸盘。

5. 发明授权

US06445203B1 Electric device testing apparatus 失效
标题翻译：电器测试仪器
公开(公告)号：US06445203B1
公开(公告)日：2002-09-03
申请号：US09456408
申请日：1999-12-08
申请人： Tsuyoshi Yamashita , Yoshihito Kobayashi , Toshiyuki Kiyokawa , Hiroto Nakamura , Noriyuki Igarashi , Kenichi Shimada
发明人： Tsuyoshi Yamashita , Yoshihito Kobayashi , Toshiyuki Kiyokawa , Hiroto Nakamura , Noriyuki Igarashi , Kenichi Shimada
IPC分类号： G01R3102
CPC分类号： G01R31/2874 , G01R31/2806 , G01R31/2856 , G01R31/2863
摘要： An electric device testing apparatus comprises a connection terminal to which an IC chip to be tested is removably connected, a pusher for pushing the IC chip in the direction of the connection terminal in order to connect the IC chip to the connection terminal, and temperature adjusted air supply for blowing a temperature adjusted air to around the IC chip during a test on the IC chip via a through hole formed on the pushed.
摘要翻译：一种电气设备测试装置，包括：被测试的IC芯片可拆卸地连接到的连接端子，用于沿着连接端子的方向推动IC芯片的推动器，以将IC芯片连接到连接端子，并且温度调节用于在通过形成在所述推动件上的通孔对IC芯片进行测试期间将温度调节的空气吹送到IC芯片周围。

6. 发明授权

US06384360B1 IC pickup, IC carrier and IC testing apparatus using the same 有权
标题翻译： IC卡，IC载体和IC测试装置
公开(公告)号：US06384360B1
公开(公告)日：2002-05-07
申请号：US09330151
申请日：1999-06-11
申请人： Yoshiyuki Masuo , Yoshihito Kobayashi
发明人： Yoshiyuki Masuo , Yoshihito Kobayashi
IPC分类号： B25J1506
CPC分类号： H05K13/0452 , H05K13/0409
摘要： A pad 1051, air cylinder 1052, cylinder control valve 1053, vacuum generator 1054, feed valve 1055, break valve 1056, and pressure sensor 1057 are assembled together to form an IC pickup 105d.
摘要翻译：垫1051，气缸1052，气缸控制阀1053，真空发生器1054，进给阀1055，断开阀1056和压力传感器1057组装在一起以形成IC拾取器105d。

7. 发明授权

US5625287A Test tray positioning stopper mechanism for automatic handler 失效
标题翻译：测试盘定位止动机构，用于自动处理
公开(公告)号：US5625287A
公开(公告)日：1997-04-29
申请号：US410821
申请日：1995-03-27
申请人： Hiroto Nakamura , Makoto Sagawa , Yoshihito Kobayashi
发明人： Hiroto Nakamura , Makoto Sagawa , Yoshihito Kobayashi
IPC分类号： G01R31/26 , B23Q7/14 , B23Q16/00 , B65G47/88 , G01R31/02 , G01R31/28
CPC分类号： B23Q7/1447 , B23Q16/001 , G01R31/2851 , G01R31/2893
摘要： An automatic handler for an IC test system is disclosed which is capable of reducing a time for transferring IC devices to be tested from a supply area to a test head area and from the test head area to a discharge area. The automatic handler includes a test tray for loading the IC devices to be tested in which the IC devices to be tested are aligned in the test tray with a shorter distance with one another than a distance between test contactors in the test head area, a pair of positioning stoppers provided in the test head area along a moving direction of the test tray in which the positioning stoppers are spaced by the distance equal to the distance of the IC devices to be tested in the test tray. In the automatic handler, the distance of the contactors is adjusted to an integer multiple of the distance of the IC devices to be tested in the test tray. One of the positioning stoppers contacts the test tray to determine a first position for testing the IC devices in a first line in the test tray, and then the test tray is transferred until other positioning stoppers contacts the test tray in a second position for testing the IC devices in a second line in the test tray. The test tray is then transferred to the discharge area. Another aspect of the automatic handler is provided with a groove on the test tray to increase a number of test position for the test tray. The groove includes an end surface which engages with the positioning stoppers.
摘要翻译：公开了一种用于IC测试系统的自动处理器，其能够减少从供应区域到测试头区域以及从测试头区域到放电区域传送要测试的IC设备的时间。自动处理机包括用于加载要测试的IC器件的测试托盘，其中待测试的IC器件在测试托架中彼此相距距离短于测试头区域中的测试接触器之间的距离，一对沿着测试盘的移动方向设置在测试头区域中的定位止动件，其中定位止动件间隔距离等于待测试的IC器件在测试托盘中的距离。在自动处理机中，将接触器的距离调整为测试盘中要测试的IC器件的距离的整数倍。其中一个定位止动器接触测试托盘，以确定测试托盘中第一行中IC器件的第一位置，然后传输测试托盘，直到其他定位止动器在第二个位置接触测试托盘，以便测试 IC器件位于测试托盘的第二行。然后将测试托盘转移到排放区域。自动处理机的另一方面在测试托盘上设置有凹槽以增加测试托盘的测试位置的数量。凹槽包括与定位止动件接合的端面。

8. 发明授权

US06433294B1 Semiconductor device testing apparatus and semiconductor device testing system having a plurality of semiconductor device testing apparatus 失效
标题翻译：具有多个半导体器件测试装置的半导体器件测试装置和半导体器件测试系统
公开(公告)号：US06433294B1
公开(公告)日：2002-08-13
申请号：US09505634
申请日：2000-02-16
申请人： Shin Nemoto , Yoshihito Kobayashi , Hiroo Nakamura , Takeshi Onishi , Hiroki Ikeda
发明人： Shin Nemoto , Yoshihito Kobayashi , Hiroo Nakamura , Takeshi Onishi , Hiroki Ikeda
IPC分类号： B07C5344
CPC分类号： G01R31/31907 , G01R31/2834 , G01R31/2887 , G01R31/31912
摘要： A semiconductor device testing system is provided which can efficiently utilize a plurality of semiconductor device testing apparatus. There are provided a host computer 2 for controlling a plurality of semiconductor device testing apparatus 1A, 1B, and 1C, and a dedicated classifying machine 3. Storage information memory means 4 for storing storage information of each semiconductor device such as a number assigned to each tested semiconductor device, the test results of each semiconductor device, and the like is provided in the host computer 2. Without sorting the tested devices or with the sorting operation of the tested devices into only two categories in the handler part 11 of each testing apparatus, the tested devices are transferred from the test tray to a general-purpose tray, and during this transfer operation, the storage information of each device is stored in the storage information memory means. When all the tests are completed, the storage information of each device stored in the storage information memory means is transmitted to the dedicated classifying machine by which the tested devices are sorted out.
摘要翻译：提供一种可有效利用多个半导体器件测试装置的半导体器件测试系统。设置有用于控制多个半导体器件测试装置1A，1B和1C的主计算机2和专用分类机3.存储信息存储装置4，用于存储每个半导体装置的存储信息，例如分配给每个半导体装置的号码测试半导体器件，每个半导体器件的测试结果等被提供在主计算机2中。在每个测试装置的处理器部分11中，不对所测试的器件进行分类或将被测试器件的分类操作分为仅两个类别被测试的设备从测试托盘传送到通用托盘，并且在该传送操作期间，每个设备的存储信息被存储在存储信息存储器装置中。当所有测试完成时，存储在存储信息存储器装置中的每个设备的存储信息被发送到专门的分类机，通过该分类机对被测试的设备进行整理。

9. 发明授权

US6066822A Semiconductor device testing apparatus and semiconductor device testing system having a plurality of semiconductor device testing apparatus 失效
标题翻译：具有多个半导体器件测试装置的半导体器件测试装置和半导体器件测试系统
公开(公告)号：US6066822A
公开(公告)日：2000-05-23
申请号：US809702
申请日：1997-03-27
申请人： Shin Nemoto , Yoshihito Kobayashi , Hiroo Nakamura , Takeshi Onishi , Hiroki Ikeda
发明人： Shin Nemoto , Yoshihito Kobayashi , Hiroo Nakamura , Takeshi Onishi , Hiroki Ikeda
IPC分类号： G01R31/26 , G01R31/28 , G01R31/319 , B07C5/344
CPC分类号： G01R31/31907 , G01R31/2834 , G01R31/2887 , G01R31/31912
摘要： A semiconductor device testing system is provided efficiently utilizes a plurality of semiconductor device testing apparatus. More particularly, a host computer controls a plurality of semiconductor device testing apparatuses and a dedicated classifying machine. A storage information memory stores storage information of each semiconductor device such as a number assigned to each tested semiconductor device such as a number assigned to each tested semiconductor device, the test results of each semiconductor device, and is provided in the host computer. Without sorting the tested devices or with the sorting operation of the tested devices into only two categories in a handler part of each testing apparatus, the tested devices are transferred from the test tray to a general-purpose tray, and during this transfer operation, the storage information of each device is stored in the storage information memory. When all of the tests are completed, the storage information of each device stored in the storage information memory is transmitted to the dedicated classifying machine by which the tested devices are sorted out.
摘要翻译： PCT No.PCT / JP96 / 02130 Sec。 371日期：1997年5月27日 102（e）日期1997年5月27日PCT提交1996年7月29日PCT公布。出版物WO97 / 05496 日期1997年2月13日提供半导体器件测试系统有效地利用多个半导体器件测试装置。更具体地，主计算机控制多个半导体器件测试装置和专用分选机。存储信息存储器存储每个半导体器件的存储信息，例如分配给每个测试的半导体器件的数量，例如分配给每个测试的半导体器件的数量，每个半导体器件的测试结果，并且设置在主计算机中。在每个测试设备的处理器部分中，如果不对被测试的设备进行分类或将被测试设备的分类操作分成两类，则测试设备从测试托盘传送到通用托盘，并且在该传送操作期间，每个设备的存储信息被存储在存储信息存储器中。当所有测试完成时，存储在存储信息存储器中的每个设备的存储信息被发送到专用分类机，通过该专用分类机对被测试的设备进行整理。

10. 发明授权

US5973493A Test tray positioning stopper mechanism for automatic handler 失效
标题翻译：测试盘定位止动机构，用于自动处理
公开(公告)号：US5973493A
公开(公告)日：1999-10-26
申请号：US725377
申请日：1996-10-03
申请人： Hiroto Nakamura , Makoto Sagawa , Yoshihito Kobayashi
发明人： Hiroto Nakamura , Makoto Sagawa , Yoshihito Kobayashi
IPC分类号： G01R31/26 , B23Q7/14 , B23Q16/00 , B65G47/88 , G01R31/02 , G01R31/28
CPC分类号： B23Q7/1447 , B23Q16/001 , G01R31/2851 , G01R31/2893
摘要： A mechanism for positioning IC devices to be tested aligned in a test tray of an automatic handler for an IC test system capable of reducing a time for transferring the test tray from a supply area to a test head area which has a plurality of test contactors and from a test head area to a discharge area is disclosed. The mechanism includes a stopper which determines the first stop position of the test tray when said test tray contacts with the outer surface of the test tray and the second stop position of the test tray when said stopper contacts with the end surface of a groove being provided with on its side portion of the test tray to receive and engage with the projection of the stopper. The distance between the adjacent test contactors is adjusted to be equal to two times or integer multiple of the distance between the adjacent IC devices to be tested aligned in the test tray and the distance between the first position and the second position is adjusted to be equal to the distance between the adjacent IC devices to be tested so that minimizing the index time for transferring the test tray becomes possible.
摘要翻译：一种用于将待测试的IC器件定位在用于IC测试系统的自动处理器的测试盘中的机构，其能够减少用于将测试托盘从供应区域传送到具有多个测试接触器的测试头区域的时间，以及从测试头区域到放电区域被公开。所述机构包括：当所述止动件与所述槽的端面接触时，所述止动件确定所述测试托盘与所述测试托盘的外表面和所述测试托盘的第二停止位置接触时所述测试托盘的第一停止位置其在其测试托盘的侧部接收并接合止动器的突起。将相邻的测试接触器之间的距离调整为等于测试托盘中待测试的相邻IC器件之间距离的两倍或整数倍，并将第一位置与第二位置之间的距离调整为相等到待测试的相邻IC器件之间的距离，使得最小化传送测试托盘的索引时间成为可能。

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