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    • 1. 发明授权
    • Light emitting diode array and production method of the light emitting
diode
    • 发光二极管阵列及发光二极管的制作方法
    • US5406095A
    • 1995-04-11
    • US112669
    • 1993-08-26
    • Yoshihisa KoyamaTaku KatayamaKatsuhiko MoritaMasashi YoshimuraToshiki YoshidaManabu Endo
    • Yoshihisa KoyamaTaku KatayamaKatsuhiko MoritaMasashi YoshimuraToshiki YoshidaManabu Endo
    • H01L27/15H01L33/00
    • H01L27/153
    • An LED (light emitting diode) array of the present invention has a plurality of light emitting diodes aligned in row on a substrate crystal. Each of the light emitting diodes has a double hetero-structure formed by causing a light emitting layer to be interposed between p-type and n-type semi-conductive layers and is isolated with isolating mesa grooves. A reflecting layer is provided between the substrate crystal and one of the p-type and n-type semi-conductive layers. The reflecting layer comprises a plurality of semi-conductive layers having at least different refractive indexes of 2 or more than 2-kinds, each of the semi-conductive layers made of semiconductor having the same polarity as that of the substrate crystal and having a wider forbidden band width than that of the light emitting layer. Further, the isolating mesa grooves are provided by a wet etching using an etching liquid of H.sub.3 PO.sub.4 .multidot.H.sub.2 O.sub.2 having volume ratio of H.sub.3 PO.sub.4 : H.sub.2 O.sub.2 =1.about.5:1, thus, the LED array having a high integration and a high light emitting output can be successfully produced.
    • 本发明的LED(发光二极管)阵列具有在衬底晶体上排成行的多个发光二极管。 每个发光二极管具有通过使发光层插入在p型和n型半导体层之间而形成的双异质结构,并且通过隔离台面凹槽隔离。 在衬底晶体和p型和n型半导体层中的一个之间提供反射层。 反射层包括多个半导体层,其折射率至少为2种以上,2种以上,半导体层由与半导体基板晶体相同极性的半导体层构成, 禁带宽度比发光层宽。 此外,通过使用体积比为H 3 PO 4 :H 2 O 2 = 1的DIFFERENCE 5:1的H 3 PO 4·H 2 O 2的蚀刻液的湿式蚀刻来提供隔离台面凹槽,因此可以成功地具有高积分和高发光输出的LED阵列 生产。
    • 6. 发明授权
    • Semiconductor integrated circuit device
    • 半导体集成电路器件
    • US5440521A
    • 1995-08-08
    • US109071
    • 1993-08-19
    • Manabu TsunozakiKyoko IshiiKoichi NozakiHiroshi YoshiokaYoshihisa KoyamaShinji UdoHidetomo AoyagiSinichi MiyatakeMakoto MorinoAkihiko Hoshida
    • Manabu TsunozakiKyoko IshiiKoichi NozakiHiroshi YoshiokaYoshihisa KoyamaShinji UdoHidetomo AoyagiSinichi MiyatakeMakoto MorinoAkihiko Hoshida
    • G11C11/401G11C5/02H01L27/108H01L27/10
    • H01L27/10805G11C5/025
    • A semiconductor integrated circuit device constituted by a plurality of sets each of which having a pair of memory mats and each memory mat having a plurality of memory cells arranged in a matrix and a sense amplifier, I/O lines for transmitting signals provided by the sense amplifiers, selecting circuitry for selecting either a condition for sending out the signals provided by the sense amplifiers on the I/O lines or a condition for not sending out the same on the I/O lines, and Y-selection lines for transmitting the selection signals. A decoder connected with selection is disposed substantially at the middle of the Y-selection lines. X- and Y-address buffers are disposed close to each other nearer to the center of the chip than X- and Y-redundant circuits. A reference voltage generating circuit is disposed nearer to the edge of the chip than an output buffer circuit. A relief selecting circuit of each memory mat is formed adjacent to a redundant line selecting circuits included in the same memory mat. At least some of wiring lines connected to each sense amplifier are formed in a wiring layer in which Y-selection lines are formed. The Y-selection lines are extended in gaps between the sense amplifiers.
    • 一种半导体集成电路器件,由多个组合构成,每组具有一对存储器阵列,每个存储器阵列具有以矩阵形式排列的多个存储单元,以及一个读出放大器,用于发送由该感测器提供的信号的I / O线 放大器,用于选择用于发送由I / O线上的读出放大器提供的信号的条件的选择电路或用于在I / O线上不发送其的条件,以及用于发送选择的Y选择线 信号。 连接有选择的解码器基本上设置在Y选择线的中间。 X和Y地址缓冲器被布置成比X和Y冗余电路更靠近芯片的中心。 参考电压产生电路设置成比输出缓冲电路更靠近芯片的边缘。 每个存储器垫的浮雕选择电路与包括在同一存储器垫中的冗余线选择电路相邻地形成。 连接到每个读出放大器的至少一些布线形成在其中形成Y选择线的布线层中。 Y选择线在读出放大器之间的间隙中扩展。