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1. 发明授权

US08462564B1 Flash memory programming power reduction 有权
标题翻译：闪存编程功耗降低
公开(公告)号：US08462564B1
公开(公告)日：2013-06-11
申请号：US13090981
申请日：2011-04-20
申请人： Yonggang Wu , Guowei Wang , Nian Yang , Sachit Chandra , Aaron Lee
发明人： Yonggang Wu , Guowei Wang , Nian Yang , Sachit Chandra , Aaron Lee
IPC分类号： G11C7/12 , G11C8/08 , G11C8/12 , G11C16/12
CPC分类号： G11C16/12 , G11C5/145 , G11C8/08
摘要： A non-volatile memory device includes an array of non-volatile memory cells. When programming the memory cells, a voltage supply source is used that includes multiple independent charge pumps. The independent charge pumps supply the programming voltage to different ones of bit lines in the array of memory cells. Using multiple charge pumps tends to reduce output voltage fluctuations and thereby reduce power loss.
摘要翻译：非易失性存储器件包括非易失性存储器单元阵列。当对存储器单元进行编程时，使用包括多个独立电荷泵的电压源。独立电荷泵将编程电压提供给存储器单元阵列中的不同位线。使用多个电荷泵倾向于降低输出电压波动，从而降低功率损耗。

2. 发明授权

US07196938B1 Charge-sharing technique during flash memory programming 有权
标题翻译：闪存编程中的电荷共享技术
公开(公告)号：US07196938B1
公开(公告)日：2007-03-27
申请号：US11229530
申请日：2005-09-20
申请人： Yonggang Wu , Guowei Wang , Nian Yang , Aaron Lee
发明人： Yonggang Wu , Guowei Wang , Nian Yang , Aaron Lee
IPC分类号： G11C16/04
CPC分类号： G11C16/12
摘要： A non-volatile memory cell array, such as a Flash NOR array, is programmed by applying voltages to bit lines that connect to memory cells in the memory cell array. A first bit line corresponding to a first memory cell in the memory array may be turned on to perform a first programming operation for the first memory cell and second bit line corresponding to a second memory cell in the memory array may be turned on to perform a second programming operation that is configured to complete after the first programming operation. The turning on/off of the first and second bit lines may be overlapped to share charge between the first and second bit lines. This overlapping can reduce wasted power and decrease programming pulse overshoot problems.
摘要翻译：诸如闪存NOR阵列的非易失性存储单元阵列通过将电压施加到连接到存储单元阵列中的存储单元的位线来编程。对应于存储器阵列中的第一存储器单元的第一位线可以被接通以对第一存储器单元执行第一编程操作，并且可以打开与存储器阵列中的第二存储器单元相对应的第二位线来执行第二编程操作被配置为在第一编程操作之后完成。第一和第二位线的导通/截止可以重叠以在第一和第二位线之间共享电荷。这种重叠可以减少浪费的功率并减少编程脉冲过冲问题。

3. 发明授权

US07352626B1 Voltage regulator with less overshoot and faster settling time 有权
标题翻译：电压调节器具有较少的过冲和更快的建立时间
公开(公告)号：US07352626B1
公开(公告)日：2008-04-01
申请号：US11212614
申请日：2005-08-29
申请人： Yonggang Wu , Guowei Wang , Nian Yang , Aaron Lee
发明人： Yonggang Wu , Guowei Wang , Nian Yang , Aaron Lee
IPC分类号： G11C11/34 , G11C7/00
CPC分类号： G11C5/14
摘要： A voltage regulator may include an operational-amplifier section, a capacitor connected to an output of the operational-amplifier section, and a switch configured to connect the capacitor to a voltage supply. The switch is configured to charge the capacitor before activating the operational-amplifier section. The capacitor is configured to store charge to supplement current being supplied from the operational-amplifier section. The voltage regulator may be used to supply power to non-volatile memory cells.
摘要翻译：电压调节器可以包括运算放大器部分，连接到运算放大器部分的输出的电容器和被配置为将电容器连接到电压源的开关。开关被配置为在激活运算放大器部分之前对电容器充电。电容器被配置为存储电荷以补充从运算放大器部分提供的电流。电压调节器可以用于向非易失性存储单元供电。

4. 发明授权

US07957204B1 Flash memory programming power reduction 有权
标题翻译：闪存编程功耗降低
公开(公告)号：US07957204B1
公开(公告)日：2011-06-07
申请号：US11229667
申请日：2005-09-20
申请人： Yonggang Wu , Guowei Wang , Nian Yang , Sachit Chandra , Aaron Lee
发明人： Yonggang Wu , Guowei Wang , Nian Yang , Sachit Chandra , Aaron Lee
IPC分类号： G11C7/12 , G11C8/08 , G11C8/12 , G11C16/12
CPC分类号： G11C16/12 , G11C5/145 , G11C8/08
摘要： A non-volatile memory device includes an array of non-volatile memory cells. When programming the memory cells, a voltage supply source is used that includes multiple independent charge pumps. The independent charge pumps supply the programming voltage to different ones of bit lines in the array of memory cells. Using multiple charge pumps tends to reduce output voltage fluctuations and thereby reduce power loss.
摘要翻译：非易失性存储器件包括非易失性存储器单元阵列。当对存储器单元进行编程时，使用包括多个独立电荷泵的电压源。独立电荷泵将编程电压提供给存储器单元阵列中的不同位线。使用多个电荷泵倾向于降低输出电压波动，从而降低功率损耗。

5. 发明申请

US20080130371A1 METHOD AND APPARATUS FOR HIGH VOLTAGE OPERATION FOR A HIGH PERFORMANCE SEMICONDUCTOR MEMORY DEVICE 有权
公开(公告)号：US20080130371A1
公开(公告)日：2008-06-05
申请号：US11950811
申请日：2007-12-05
申请人： Nian Yang , Boon-Aik Ang , Yonggang Wu , Guowei Wang , Fan Wan Lai
发明人： Nian Yang , Boon-Aik Ang , Yonggang Wu , Guowei Wang , Fan Wan Lai
IPC分类号： G11C16/12 , G11C16/28
CPC分类号： G11C7/1039 , G11C8/08 , G11C16/0475 , G11C16/0491 , G11C16/08 , G11C16/30 , G11C2207/2245
摘要： A method and apparatus are provided for high performance, high voltage memory operations on selected memory cells (200) of a semiconductor memory device (100). A high voltage generator (106) during program or erase operations provides a continuous high voltage level (702) on selected word lines (502) and maintains a continuous high voltage level supply to a bit line decoder (120) which sequentially provides the high voltage level (706) to a first portion of bit lines (504) and discharges (708) those bit lines (504) before providing the high voltage level to a second portion (710). For additional improvements to program operations, the high voltage generator (106) decouples high voltages provided to the word lines (502) and the bit lines (504) by providing a current flow control device (1208) therebetween and provides a boosting voltage at a time (1104) to overcome a voltage level drop (1102) resulting from a capacitor load associated with selected bit lines (504) and/or the bit line decoder (120) precharges (1716) a second portion of the bit lines (504) while providing a high voltage level to a first portion to program (1706) a first portion of memory cells (200). For improvements to read operations, whether dynamic reference cells (2002) are blank is determined by providing non-identically regulated high voltage levels from a first voltage source (2112) to the dynamic reference cells (2002) and from a second voltage source (2104) to static reference cells (2004) and, if the dynamic reference cells (2002) are not blank, reads selected memory cells (200) by providing identically regulated high voltage levels to the selected memory cells (200), the dynamic reference cells (2002) and the static reference cells (2004).

6. 发明授权

US07345916B2 Method and apparatus for high voltage operation for a high performance semiconductor memory device 有权
公开(公告)号：US07345916B2
公开(公告)日：2008-03-18
申请号：US11423638
申请日：2006-06-12
申请人： Nian Yang , Boon-Aik Ang , Yonggang Wu , Guowei Wang , Fan Wan Lai
发明人： Nian Yang , Boon-Aik Ang , Yonggang Wu , Guowei Wang , Fan Wan Lai
IPC分类号： G11C16/04 , G11C16/06 , G11C5/14 , G11C7/00
CPC分类号： G11C7/1039 , G11C8/08 , G11C16/0475 , G11C16/0491 , G11C16/08 , G11C16/30 , G11C2207/2245
摘要： A method and apparatus are provided for high performance, high voltage memory operations on selected memory cells (200) of a semiconductor memory device (100). A high voltage generator (106) during program or erase operations provides a continuous high voltage level (702) on selected word lines (502) and maintains a continuous high voltage level supply to a bit line decoder (120) which sequentially provides the high voltage level (706) to a first portion of bit lines (504) and discharges (708) those bit lines (504) before providing the high voltage level to a second portion (710).For additional improvements to program operations, the high voltage generator (106) decouples high voltages provided to the word lines (502) and the bit lines (504) by providing a current flow control device (1208) therebetween and provides a boosting voltage at a time (1104) to overcome a voltage level drop (1102) resulting from a capacitor load associated with selected bit lines (504) and/or the bit line decoder (120) precharges (1716) a second portion of the bit lines (504) while providing a high voltage level to a first portion to program (1706) a first portion of memory cells (200).For improvements to read operations, whether dynamic reference cells (2002) are blank is determined by providing non-identically regulated high voltage levels from a first voltage source (2112) to the dynamic reference cells (2002) and from a second voltage source (2104) to static reference cells (2004) and, if the dynamic reference cells (2002) are not blank, reads selected memory cells (200) by providing identically regulated high voltage levels to the selected memory cells (200), the dynamic reference cells (2002) and the static reference cells (2004).

7. 发明申请

US20070291550A1 METHOD AND APPARATUS FOR HIGH VOLTAGE OPERATION FOR A HIGH PERFORMANCE SEMICONDUCTOR MEMORY DEVICE 有权
公开(公告)号：US20070291550A1
公开(公告)日：2007-12-20
申请号：US11423638
申请日：2006-06-12
申请人： Nian Yang , Boon-Aik Ang , Yonggang Wu , Guowei Wang , Fan Wan Lai
发明人： Nian Yang , Boon-Aik Ang , Yonggang Wu , Guowei Wang , Fan Wan Lai
IPC分类号： G11C11/34 , G11C16/04 , G11C8/00 , G11C7/00 , G11C16/06
CPC分类号： G11C7/1039 , G11C8/08 , G11C16/0475 , G11C16/0491 , G11C16/08 , G11C16/30 , G11C2207/2245
摘要： A method and apparatus are provided for high performance, high voltage memory operations on selected memory cells (200) of a semiconductor memory device (100). A high voltage generator (106) during program or erase operations provides a continuous high voltage level (702) on selected word lines (502) and maintains a continuous high voltage level supply to a bit line decoder (120) which sequentially provides the high voltage level (706) to a first portion of bit lines (504) and discharges (708) those bit lines (504) before providing the high voltage level to a second portion (710).For additional improvements to program operations, the high voltage generator (106) decouples high voltages provided to the word lines (502) and the bit lines (504) by providing a current flow control device (1208) therebetween and provides a boosting voltage at a time (1104) to overcome a voltage level drop (1102) resulting from a capacitor load associated with selected bit lines (504) and/or the bit line decoder (120) precharges (1716) a second portion of the bit lines (504) while providing a high voltage level to a first portion to program (1706) a first portion of memory cells (200).For improvements to read operations, whether dynamic reference cells (2002) are blank is determined by providing non-identically regulated high voltage levels from a first voltage source (2112) to the dynamic reference cells (2002) and from a second voltage source (2104) to static reference cells (2004) and, if the dynamic reference cells (2002) are not blank, reads selected memory cells (200) by providing identically regulated high voltage levels to the selected memory cells (200), the dynamic reference cells (2002) and the static reference cells (2004).

8. 发明授权

US07613044B2 Method and apparatus for high voltage operation for a high performance semiconductor memory device 有权
标题翻译：用于高性能半导体存储器件的高电压操作的方法和装置
公开(公告)号：US07613044B2
公开(公告)日：2009-11-03
申请号：US11950811
申请日：2007-12-05
申请人： Nian Yang , Boon-Aik Ang , Yonggang Wu , Guowei Wang , Fan Wan Lai
发明人： Nian Yang , Boon-Aik Ang , Yonggang Wu , Guowei Wang , Fan Wan Lai
IPC分类号： G11C11/34 , G11C16/04 , G11C16/06 , G11C7/10
CPC分类号： G11C7/1039 , G11C8/08 , G11C16/0475 , G11C16/0491 , G11C16/08 , G11C16/30 , G11C2207/2245
摘要： A method and apparatus are provided for high performance, high voltage memory operations on selected memory cells (200) of a semiconductor memory device (100). A high voltage generator (106) during program or erase operations provides a continuous high voltage level (702) on selected word lines (502) and maintains a continuous high voltage level supply to a bit line decoder (120) which sequentially provides the high voltage level (706) to a first portion of bit lines (504) and discharges (708) those bit lines (504) before providing the high voltage level to a second portion (710). For additional improvements to program operations, the high voltage generator (106) decouples high voltages provided to the word lines (502) and the bit lines (504) by providing a current flow control device (1208) therebetween and provides a boosting voltage at a time (1104) to overcome a voltage level drop (1102) resulting from a capacitor load associated with selected bit lines (504) and/or the bit line decoder (120) precharges (1716) a second portion of the bit lines (504) while providing a high voltage level to a first portion to program (1706) a first portion of memory cells (200). For improvements to read operations, whether dynamic reference cells (2002) are blank is determined by providing non-identically regulated high voltage levels from a first voltage source (2112) to the dynamic reference cells (2002) and from a second voltage source (2104) to static reference cells (2004) and, if the dynamic reference cells (2002) are not blank, reads selected memory cells (200) by providing identically regulated high voltage levels to the selected memory cells (200), the dynamic reference cells (2002) and the static reference cells (2004).
摘要翻译：提供了一种用于在半导体存储器件（100）的选定存储单元（200）上进行高性能，高电压存储器操作的方法和装置。在编程或擦除操作期间，高电压发生器（106）在所选择的字线（502）上提供连续的高电压电平（702），并且向位线解码器（120）保持连续的高电压电平供应，位线解码器（120）依次提供高电压电平（706）到位线（504）的第一部分，并且在将高电压电平提供给第二部分（710）之前对那些位线（504）进行放电（708）。为了对编程操作进一步改进，高电压发生器（106）通过在其间提供电流控制装置（1208）来解耦提供给字线（502）和位线（504）的高电压，并在时间（1104）以克服由与所选位线（504）和/或位线解码器（120）相关联的电容器负载导致的电压电平下降（1102），所述位线（504）的第二部分预充电（1716）同时向第一部分提供高电压电平以对存储单元（200）的第一部分进行编程（1706）。为了改进读取操作，动态参考单元（2002）是空白的是通过从第一电压源（2112）到动态参考单元（2002）和从第二电压源（2104）提供非相同调节的高电压电平来确定的）到静态参考单元（2004），并且如果动态参考单元（2002）不为空白，则通过向所选择的存储单元（200），动态参考单元（200）提供相同调节的高电压电平来读取所选存储单元（200） 2002）和静态参考单元（2004）。

9. 发明申请

US20080151639A1 FLASH MEMORY DEVICE WITH EXTERNAL HIGH VOLTAGE SUPPLY 有权
标题翻译：具有外部高压电源的闪存存储器件
公开(公告)号：US20080151639A1
公开(公告)日：2008-06-26
申请号：US11613383
申请日：2006-12-20
申请人： Nian Yang , Yonggang Wu , Aaron Lee , Wei Daisy Cai
发明人： Nian Yang , Yonggang Wu , Aaron Lee , Wei Daisy Cai
IPC分类号： G11C16/32
CPC分类号： G11C16/12
摘要： A semiconductor memory device (104) selectably connectable to an external high voltage power supply (122) is provided. The semiconductor memory device (104) includes a switch (314), a detector (316) and a timing device (318). The switch (314) is connected to external voltage supply signals and selectably couples the external voltage supply signals to memory cells (305) of the semiconductor memory device (104) for memory operations thereof. The external voltage supply signals including a high voltage signal (412) provided from the external high voltage power supply (122) and an operational voltage signal Vcc (402). The detector (316) is connected to the external voltage supply signals for generating a timer activation signal (404) in response to detecting an operational voltage power-on period. The timing device (318) signals the switch (314) to decouple the high voltage signal (412) and the operational voltage signal (402) from the memory cells (305) in response to the timer activation signal (404) and to recouple the high voltage signal (412) and the operational voltage signal (402) to the memory cells (305) a time delay interval thereafter. The time delay interval is determined in response to the high voltage signal (412).
摘要翻译：提供可选择地连接到外部高压电源（122）的半导体存储器件（104）。半导体存储器件（104）包括开关（314），检测器（316）和定时装置（318）。开关（314）连接到外部电压源信号，并且可选择地将外部电压供应信号耦合到半导体存储器件（104）的存储单元（305），用于存储器操作。包括从外部高压电源（122）提供的高电压信号（412）的外部电压供给信号和操作电压信号Vcc（402）。检测器（316）连接到外部电压源信号，以响应于检测到工作电压通电周期而产生定时器激活信号（404）。定时装置（318）响应于定时器启动信号（404），向开关314通知高压信号412和操作电压信号402与存储单元305的耦合，高电压信号（412）和操作电压信号（402）到其后的时间延迟区间。响应于高电压信号确定时间延迟间隔（412）。

10. 发明授权

US07626882B2 Flash memory device with external high voltage supply 有权
标题翻译：具有外部高压电源的闪存设备
公开(公告)号：US07626882B2
公开(公告)日：2009-12-01
申请号：US11613383
申请日：2006-12-20
申请人： Nian Yang , Yonggang Wu , Aaron Lee , Wei Daisy Cai
发明人： Nian Yang , Yonggang Wu , Aaron Lee , Wei Daisy Cai
IPC分类号： G11C5/14
CPC分类号： G11C16/12
摘要： A semiconductor memory device (104) selectably connectable to an external high voltage power supply (122) is provided. The semiconductor memory device (104) includes a switch (314), a detector (316) and a timing device (318). The switch (314) is connected to external voltage supply signals and selectably couples the external voltage supply signals to memory cells (305) of the semiconductor memory device (104) for memory operations thereof. The external voltage supply signals including a high voltage signal (412) provided from the external high voltage power supply (122) and an operational voltage signal Vcc (402). The detector (316) is connected to the external voltage supply signals for generating a timer activation signal (404) in response to detecting an operational voltage power-on period. The timing device (318) signals the switch (314) to decouple the high voltage signal (412) and the operational voltage signal (402) from the memory cells (305) in response to the timer activation signal (404) and to recouple the high voltage signal (412) and the operational voltage signal (402) to the memory cells (305) a time delay interval thereafter. The time delay interval is determined in response to the high voltage signal (412).
摘要翻译：提供可选择地连接到外部高压电源（122）的半导体存储器件（104）。半导体存储器件（104）包括开关（314），检测器（316）和定时装置（318）。开关（314）连接到外部电压源信号，并且可选择地将外部电压供应信号耦合到半导体存储器件（104）的存储单元（305），用于存储器操作。包括从外部高压电源（122）提供的高电压信号（412）的外部电压供给信号和操作电压信号Vcc（402）。检测器（316）连接到外部电压源信号，以响应于检测到工作电压通电周期而产生定时器激活信号（404）。定时装置（318）响应于定时器启动信号（404），向开关314通知高压信号412和操作电压信号402与存储单元305的耦合，高电压信号（412）和操作电压信号（402）到其后的时间延迟区间。响应于高电压信号确定时间延迟间隔（412）。

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