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1. 发明申请

US20080130371A1 METHOD AND APPARATUS FOR HIGH VOLTAGE OPERATION FOR A HIGH PERFORMANCE SEMICONDUCTOR MEMORY DEVICE 有权
公开(公告)号：US20080130371A1
公开(公告)日：2008-06-05
申请号：US11950811
申请日：2007-12-05
申请人： Nian Yang , Boon-Aik Ang , Yonggang Wu , Guowei Wang , Fan Wan Lai
发明人： Nian Yang , Boon-Aik Ang , Yonggang Wu , Guowei Wang , Fan Wan Lai
IPC分类号： G11C16/12 , G11C16/28
CPC分类号： G11C7/1039 , G11C8/08 , G11C16/0475 , G11C16/0491 , G11C16/08 , G11C16/30 , G11C2207/2245
摘要： A method and apparatus are provided for high performance, high voltage memory operations on selected memory cells (200) of a semiconductor memory device (100). A high voltage generator (106) during program or erase operations provides a continuous high voltage level (702) on selected word lines (502) and maintains a continuous high voltage level supply to a bit line decoder (120) which sequentially provides the high voltage level (706) to a first portion of bit lines (504) and discharges (708) those bit lines (504) before providing the high voltage level to a second portion (710). For additional improvements to program operations, the high voltage generator (106) decouples high voltages provided to the word lines (502) and the bit lines (504) by providing a current flow control device (1208) therebetween and provides a boosting voltage at a time (1104) to overcome a voltage level drop (1102) resulting from a capacitor load associated with selected bit lines (504) and/or the bit line decoder (120) precharges (1716) a second portion of the bit lines (504) while providing a high voltage level to a first portion to program (1706) a first portion of memory cells (200). For improvements to read operations, whether dynamic reference cells (2002) are blank is determined by providing non-identically regulated high voltage levels from a first voltage source (2112) to the dynamic reference cells (2002) and from a second voltage source (2104) to static reference cells (2004) and, if the dynamic reference cells (2002) are not blank, reads selected memory cells (200) by providing identically regulated high voltage levels to the selected memory cells (200), the dynamic reference cells (2002) and the static reference cells (2004).

2. 发明授权

US07345916B2 Method and apparatus for high voltage operation for a high performance semiconductor memory device 有权
公开(公告)号：US07345916B2
公开(公告)日：2008-03-18
申请号：US11423638
申请日：2006-06-12
申请人： Nian Yang , Boon-Aik Ang , Yonggang Wu , Guowei Wang , Fan Wan Lai
发明人： Nian Yang , Boon-Aik Ang , Yonggang Wu , Guowei Wang , Fan Wan Lai
IPC分类号： G11C16/04 , G11C16/06 , G11C5/14 , G11C7/00
CPC分类号： G11C7/1039 , G11C8/08 , G11C16/0475 , G11C16/0491 , G11C16/08 , G11C16/30 , G11C2207/2245
摘要： A method and apparatus are provided for high performance, high voltage memory operations on selected memory cells (200) of a semiconductor memory device (100). A high voltage generator (106) during program or erase operations provides a continuous high voltage level (702) on selected word lines (502) and maintains a continuous high voltage level supply to a bit line decoder (120) which sequentially provides the high voltage level (706) to a first portion of bit lines (504) and discharges (708) those bit lines (504) before providing the high voltage level to a second portion (710).For additional improvements to program operations, the high voltage generator (106) decouples high voltages provided to the word lines (502) and the bit lines (504) by providing a current flow control device (1208) therebetween and provides a boosting voltage at a time (1104) to overcome a voltage level drop (1102) resulting from a capacitor load associated with selected bit lines (504) and/or the bit line decoder (120) precharges (1716) a second portion of the bit lines (504) while providing a high voltage level to a first portion to program (1706) a first portion of memory cells (200).For improvements to read operations, whether dynamic reference cells (2002) are blank is determined by providing non-identically regulated high voltage levels from a first voltage source (2112) to the dynamic reference cells (2002) and from a second voltage source (2104) to static reference cells (2004) and, if the dynamic reference cells (2002) are not blank, reads selected memory cells (200) by providing identically regulated high voltage levels to the selected memory cells (200), the dynamic reference cells (2002) and the static reference cells (2004).

3. 发明申请

US20070291550A1 METHOD AND APPARATUS FOR HIGH VOLTAGE OPERATION FOR A HIGH PERFORMANCE SEMICONDUCTOR MEMORY DEVICE 有权
公开(公告)号：US20070291550A1
公开(公告)日：2007-12-20
申请号：US11423638
申请日：2006-06-12
申请人： Nian Yang , Boon-Aik Ang , Yonggang Wu , Guowei Wang , Fan Wan Lai
发明人： Nian Yang , Boon-Aik Ang , Yonggang Wu , Guowei Wang , Fan Wan Lai
IPC分类号： G11C11/34 , G11C16/04 , G11C8/00 , G11C7/00 , G11C16/06
CPC分类号： G11C7/1039 , G11C8/08 , G11C16/0475 , G11C16/0491 , G11C16/08 , G11C16/30 , G11C2207/2245
摘要： A method and apparatus are provided for high performance, high voltage memory operations on selected memory cells (200) of a semiconductor memory device (100). A high voltage generator (106) during program or erase operations provides a continuous high voltage level (702) on selected word lines (502) and maintains a continuous high voltage level supply to a bit line decoder (120) which sequentially provides the high voltage level (706) to a first portion of bit lines (504) and discharges (708) those bit lines (504) before providing the high voltage level to a second portion (710).For additional improvements to program operations, the high voltage generator (106) decouples high voltages provided to the word lines (502) and the bit lines (504) by providing a current flow control device (1208) therebetween and provides a boosting voltage at a time (1104) to overcome a voltage level drop (1102) resulting from a capacitor load associated with selected bit lines (504) and/or the bit line decoder (120) precharges (1716) a second portion of the bit lines (504) while providing a high voltage level to a first portion to program (1706) a first portion of memory cells (200).For improvements to read operations, whether dynamic reference cells (2002) are blank is determined by providing non-identically regulated high voltage levels from a first voltage source (2112) to the dynamic reference cells (2002) and from a second voltage source (2104) to static reference cells (2004) and, if the dynamic reference cells (2002) are not blank, reads selected memory cells (200) by providing identically regulated high voltage levels to the selected memory cells (200), the dynamic reference cells (2002) and the static reference cells (2004).

4. 发明授权

US07613044B2 Method and apparatus for high voltage operation for a high performance semiconductor memory device 有权
标题翻译：用于高性能半导体存储器件的高电压操作的方法和装置
公开(公告)号：US07613044B2
公开(公告)日：2009-11-03
申请号：US11950811
申请日：2007-12-05
申请人： Nian Yang , Boon-Aik Ang , Yonggang Wu , Guowei Wang , Fan Wan Lai
发明人： Nian Yang , Boon-Aik Ang , Yonggang Wu , Guowei Wang , Fan Wan Lai
IPC分类号： G11C11/34 , G11C16/04 , G11C16/06 , G11C7/10
CPC分类号： G11C7/1039 , G11C8/08 , G11C16/0475 , G11C16/0491 , G11C16/08 , G11C16/30 , G11C2207/2245
摘要： A method and apparatus are provided for high performance, high voltage memory operations on selected memory cells (200) of a semiconductor memory device (100). A high voltage generator (106) during program or erase operations provides a continuous high voltage level (702) on selected word lines (502) and maintains a continuous high voltage level supply to a bit line decoder (120) which sequentially provides the high voltage level (706) to a first portion of bit lines (504) and discharges (708) those bit lines (504) before providing the high voltage level to a second portion (710). For additional improvements to program operations, the high voltage generator (106) decouples high voltages provided to the word lines (502) and the bit lines (504) by providing a current flow control device (1208) therebetween and provides a boosting voltage at a time (1104) to overcome a voltage level drop (1102) resulting from a capacitor load associated with selected bit lines (504) and/or the bit line decoder (120) precharges (1716) a second portion of the bit lines (504) while providing a high voltage level to a first portion to program (1706) a first portion of memory cells (200). For improvements to read operations, whether dynamic reference cells (2002) are blank is determined by providing non-identically regulated high voltage levels from a first voltage source (2112) to the dynamic reference cells (2002) and from a second voltage source (2104) to static reference cells (2004) and, if the dynamic reference cells (2002) are not blank, reads selected memory cells (200) by providing identically regulated high voltage levels to the selected memory cells (200), the dynamic reference cells (2002) and the static reference cells (2004).
摘要翻译：提供了一种用于在半导体存储器件（100）的选定存储单元（200）上进行高性能，高电压存储器操作的方法和装置。在编程或擦除操作期间，高电压发生器（106）在所选择的字线（502）上提供连续的高电压电平（702），并且向位线解码器（120）保持连续的高电压电平供应，位线解码器（120）依次提供高电压电平（706）到位线（504）的第一部分，并且在将高电压电平提供给第二部分（710）之前对那些位线（504）进行放电（708）。为了对编程操作进一步改进，高电压发生器（106）通过在其间提供电流控制装置（1208）来解耦提供给字线（502）和位线（504）的高电压，并在时间（1104）以克服由与所选位线（504）和/或位线解码器（120）相关联的电容器负载导致的电压电平下降（1102），所述位线（504）的第二部分预充电（1716）同时向第一部分提供高电压电平以对存储单元（200）的第一部分进行编程（1706）。为了改进读取操作，动态参考单元（2002）是空白的是通过从第一电压源（2112）到动态参考单元（2002）和从第二电压源（2104）提供非相同调节的高电压电平来确定的）到静态参考单元（2004），并且如果动态参考单元（2002）不为空白，则通过向所选择的存储单元（200），动态参考单元（200）提供相同调节的高电压电平来读取所选存储单元（200） 2002）和静态参考单元（2004）。

5. 发明申请

US20070286006A1 METHOD AND APPARATUS FOR DRAIN PUMP OPERATION 有权
标题翻译：排水泵运行方法与装置
公开(公告)号：US20070286006A1
公开(公告)日：2007-12-13
申请号：US11423645
申请日：2006-06-12
申请人： Yonggang Wu , Nian Yang , Boon-Aik Ang
发明人： Yonggang Wu , Nian Yang , Boon-Aik Ang
IPC分类号： G11C5/14
CPC分类号： G11C5/145
摘要： A method and apparatus are provided for improved noise reduction from switching on and off drain pumps (202) in a high voltage generator. The drain pumps (202) are divided into groups (204) and activation of the groups (204) of drain pumps (202) is staggered (304, 310). In addition, when drain pumps are switched on and off for power conservation or to maintain a steady state high voltage level, the groups (204) of drain pumps (202) are switched on and off in response to various predetermined high voltage levels (410, 412, 414, 416), with different voltage levels for different groups (204) of drain pumps (202).
摘要翻译：提供了一种方法和装置，用于从高压发生器中的接通和关闭排放泵（202）的开关中减少噪音。排水泵（202）被分成组（204），并且排水泵（202）的组（204）的活动是交错的（304,310）。此外，当排水泵被接通和关闭以进行节能或保持稳定状态的高电压电平时，排水泵（202）的组（204）响应于各种预定的高电压电平（410）被接通和断开，412,414,416），具有用于不同组（204）排水泵（202）的不同电压电平。

6. 发明申请

US20080122413A1 METHOD AND APPARATUS FOR VERSATILE HIGH VOLTAGE LEVEL DETECTION WITH RELATIVE NOISE IMMUNITY 审中-公开
标题翻译：用于具有相对噪声免疫力的多电平高电平检测方法和装置
公开(公告)号：US20080122413A1
公开(公告)日：2008-05-29
申请号：US11423643
申请日：2006-06-12
申请人： Boon-Aik Ang , Nian Yang , Yonggang Wu
发明人： Boon-Aik Ang , Nian Yang , Yonggang Wu
IPC分类号： G05F1/10 , G01R19/00
CPC分类号： G11C5/143 , G01R19/16552
摘要： A method and apparatus are provided for versatile high voltage level detection. A semiconductor device (100) is provided which includes a high voltage generating circuit (202) for generating a high voltage supply signal having a high voltage level and a voltage level detector (204) coupled to the output of the high voltage generating circuit (202) and including a current source (402) for generating a current to increase the voltage margin of the voltage level detector (204), the voltage level detector (204) generating a voltage control signal in response to the current and the high voltage level detected.
摘要翻译：提供了用于通用的高电压电平检测的方法和装置。提供一种半导体器件（100），其包括用于产生具有高电压电平的高电压电源信号的高电压产生电路（202）和耦合到高电压发生电路（202）的输出的电压电平检测器（204）），并且包括用于产生电流以增加电压电平检测器（204）的电压余量的电流源（402），电压电平检测器（204）响应于检测到的电流和高电压产生电压控制信号。

7. 发明授权

US07355904B2 Method and apparatus for drain pump operation 有权
标题翻译：排水泵运行方法和装置
公开(公告)号：US07355904B2
公开(公告)日：2008-04-08
申请号：US11423645
申请日：2006-06-12
申请人： Yonggang Wu , Nian Yang , Boon-Aik Ang
发明人： Yonggang Wu , Nian Yang , Boon-Aik Ang
IPC分类号： G11C7/00
CPC分类号： G11C5/145
摘要： A method and apparatus are provided for improved noise reduction from switching on and off drain pumps (202) in a high voltage generator. The drain pumps (202) are divided into groups (204) and activation of the groups (204) of drain pumps (202) is staggered (304, 310). In addition, when drain pumps are switched on and off for power conservation or to maintain a steady state high voltage level, the groups (204) of drain pumps (202) are switched on and off in response to various predetermined high voltage levels (410, 412, 414, 416), with different voltage levels for different groups (204) of drain pumps (202).
摘要翻译：提供了一种方法和装置，用于从高压发生器中的接通和关闭排放泵（202）的开启和关闭状态改进降噪。排水泵（202）被分成组（204），并且排水泵（202）的组（204）的活动是交错的（304,310）。此外，当排水泵被接通和关闭以进行节能或保持稳定状态的高电压电平时，排水泵（202）的组（204）响应于各种预定的高电压电平（410）被接通和断开，412,414,416），具有用于不同组（204）排水泵（202）的不同电压电平。

8. 发明申请

US20070284609A1 METHOD AND APPARATUS FOR DRAIN PUMP POWER CONSERVATION 审中-公开
标题翻译：排水泵功率保存方法与装置
公开(公告)号：US20070284609A1
公开(公告)日：2007-12-13
申请号：US11423649
申请日：2006-06-12
申请人： Boon-Aik Ang , Nian Yang , Yonggang Wu
发明人： Boon-Aik Ang , Nian Yang , Yonggang Wu
IPC分类号： H01L29/74
CPC分类号： G11C16/30 , G11C5/145 , H02M3/07
摘要： A method and apparatus are provided for improved power conservation in a semiconductor device (100) which includes a high voltage generating circuit (200) such as a drain pump. The operation frequency of the drain pump (200) is controlled in response to the high voltage level detected at the output thereof. In addition, highly efficient operation of the drain pump (200) can be achieved by enabling and disabling the drain pump (200) in response to the high voltage level to provide an output signal at a relatively constant high voltage level. The drain pump (200) is enabled in response to a high voltage detector (202, 402, 502) detecting a high voltage level lower than a first predetermined voltage level and is disabled in response to detecting a voltage level higher than a second predetermined voltage level, the second predetermined voltage level being higher than the first predetermined voltage level.
摘要翻译：提供了一种用于在包括诸如排水泵的高电压产生电路（200）的半导体器件（100）中改善功率节省的方法和装置。排水泵（200）的运转频率根据其输出端检测到的高电压电平进行控制。此外，可以通过响应于高电压电平启用和禁用排水泵（200）来实现排水泵（200）的高效率操作，以在相对恒定的高电压电平提供输出信号。响应于检测到低于第一预定电压电平的高电压电平的高电压检测器（202,402,502）响应于检测到高于第二预定电压的电压电平而禁用排水泵（200）电平，第二预定电压电平高于第一预定电压电平。

9. 发明授权

US07848167B2 Apparatus and method for generating wide-range regulated supply voltages for a flash memory 有权
标题翻译：用于产生用于闪速存储器的宽范围稳压电源电压的装置和方法
公开(公告)号：US07848167B2
公开(公告)日：2010-12-07
申请号：US12255622
申请日：2008-10-21
申请人： Soo-yong Park , Boon-Aik Ang , Steve Choi
发明人： Soo-yong Park , Boon-Aik Ang , Steve Choi
IPC分类号： G11C7/02 , G11C7/10 , G11C7/06
CPC分类号： G11C5/147 , G05F1/56 , G11C8/10 , G11C16/30
摘要： A voltage regulator is provided. The voltage regulator provides an output voltage that is proportional to a digital multi-bit select signal. The voltage regulator includes a coarse voltage regulator and a fine voltage regulator. The coarse voltage regulator provides a coarse output voltage based on an output of a voltage divider selected based on the most significant bits of the select signal. The fine voltage regulator provides the output voltage from the coarse output voltage. The output of the fine voltage regulator is adjusted by adjusting the output of an adjustable current source that is provided to a resistor that is coupled between the output and one of the inputs of the fine voltage regulator.
摘要翻译：提供电压调节器。电压调节器提供与数字多位选择信号成比例的输出电压。电压调节器包括粗调电压调节器和精密电压调节器。粗电压调节器基于基于选择信号的最高有效位选择的分压器的输出提供粗略的输出电压。精细电压调节器提供粗输出电压的输出电压。微调电压调节器的输出通过调节可调电流源的输出来调节，该可调电流源提供给耦合在输出端和精密电压调节器的一个输入端之间的电阻器。

10. 发明申请

US20050270217A1 VARIABLE ACCURACY PIPELINE ADC FOR WLAN COMMUNICATIONS DEVICES 有权
标题翻译：用于WLAN通信设备的可变精度管道ADC
公开(公告)号：US20050270217A1
公开(公告)日：2005-12-08
申请号：US11011510
申请日：2004-12-14
申请人： Meei-Ling Chiang , Boon-Aik Ang
发明人： Meei-Ling Chiang , Boon-Aik Ang
IPC分类号： H03M1/00 , H03M1/06 , H03M1/16 , H03M1/18 , H03M1/38 , H03M1/44
CPC分类号： H03M1/007 , H03M1/0695 , H03M1/167 , H03M1/44
摘要： A pipeline ADC (Analog to Digital Converter) unit is provided that has a first and a second multi-stage portion. The first multi-stage portion has a first plurality of converter stages for converting a first analog signal to a first digital signal having a first digital resolution. The second portion has a second plurality of converter stages to convert a second analog signal to a second digital signal having a second digital resolution. The second plurality includes the first plurality. The pipeline ADC unit selectively uses either the first plurality of stages alone, or the second plurality. The pipeline ADC unit may be used in a WLAN (Wireless Local Area Network) communication device.
摘要翻译：提供了具有第一和第二多级部分的流水线ADC（模数转换器）单元。第一多级部分具有用于将第一模拟信号转换为具有第一数字分辨率的第一数字信号的第一多个转换器级。第二部分具有第二多个转换器级，以将第二模拟信号转换成具有第二数字分辨率的第二数字信号。第二多个包括第一多个。流水线ADC单元选择性地使用单独的第一多个级或第二级。流水线ADC单元可用于WLAN（无线局域网）通信设备中。

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