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1. 发明授权

US07957204B1 Flash memory programming power reduction 有权
标题翻译：闪存编程功耗降低
公开(公告)号：US07957204B1
公开(公告)日：2011-06-07
申请号：US11229667
申请日：2005-09-20
申请人： Yonggang Wu , Guowei Wang , Nian Yang , Sachit Chandra , Aaron Lee
发明人： Yonggang Wu , Guowei Wang , Nian Yang , Sachit Chandra , Aaron Lee
IPC分类号： G11C7/12 , G11C8/08 , G11C8/12 , G11C16/12
CPC分类号： G11C16/12 , G11C5/145 , G11C8/08
摘要： A non-volatile memory device includes an array of non-volatile memory cells. When programming the memory cells, a voltage supply source is used that includes multiple independent charge pumps. The independent charge pumps supply the programming voltage to different ones of bit lines in the array of memory cells. Using multiple charge pumps tends to reduce output voltage fluctuations and thereby reduce power loss.
摘要翻译：非易失性存储器件包括非易失性存储器单元阵列。当对存储器单元进行编程时，使用包括多个独立电荷泵的电压源。独立电荷泵将编程电压提供给存储器单元阵列中的不同位线。使用多个电荷泵倾向于降低输出电压波动，从而降低功率损耗。

2. 发明授权

US08462564B1 Flash memory programming power reduction 有权
标题翻译：闪存编程功耗降低
公开(公告)号：US08462564B1
公开(公告)日：2013-06-11
申请号：US13090981
申请日：2011-04-20
申请人： Yonggang Wu , Guowei Wang , Nian Yang , Sachit Chandra , Aaron Lee
发明人： Yonggang Wu , Guowei Wang , Nian Yang , Sachit Chandra , Aaron Lee
IPC分类号： G11C7/12 , G11C8/08 , G11C8/12 , G11C16/12
CPC分类号： G11C16/12 , G11C5/145 , G11C8/08
摘要： A non-volatile memory device includes an array of non-volatile memory cells. When programming the memory cells, a voltage supply source is used that includes multiple independent charge pumps. The independent charge pumps supply the programming voltage to different ones of bit lines in the array of memory cells. Using multiple charge pumps tends to reduce output voltage fluctuations and thereby reduce power loss.
摘要翻译：非易失性存储器件包括非易失性存储器单元阵列。当对存储器单元进行编程时，使用包括多个独立电荷泵的电压源。独立电荷泵将编程电压提供给存储器单元阵列中的不同位线。使用多个电荷泵倾向于降低输出电压波动，从而降低功率损耗。

3. 发明授权

US07443732B2 High performance flash memory device capable of high density data storage 有权
标题翻译：高性能闪存设备能够进行高密度数据存储
公开(公告)号：US07443732B2
公开(公告)日：2008-10-28
申请号：US11229527
申请日：2005-09-20
申请人： Tiao-Hua Kuo , Nancy Leong , Nian Yang , Guowei Wang , Aaron Lee , Sachit Chandra , Michael A. VanBuskirk , Johnny Chen , Darlene Hamilton , Binh Quang Le
发明人： Tiao-Hua Kuo , Nancy Leong , Nian Yang , Guowei Wang , Aaron Lee , Sachit Chandra , Michael A. VanBuskirk , Johnny Chen , Darlene Hamilton , Binh Quang Le
IPC分类号： G11C11/34
CPC分类号： G11C5/147 , G11C16/12
摘要： A method is provided for programming a nonvolatile memory array including an array of memory cells, where each memory cell including a substrate, a control gate, a charge storage element, a source region and a drain region. The method includes receiving a programming window containing a predetermined number of bits that are to be programmed in the array and determining which of the predetermined number of bits are to be programmed in the memory array. The predetermined number of bits are simultaneously programmed to corresponding memory cells in the array. A programming state of the predetermined number of bits in the array is simultaneously verified.
摘要翻译：提供了一种用于对包括存储器单元阵列的非易失性存储器阵列进行编程的方法，其中每个存储单元包括衬底，控制栅极，电荷存储元件，源极区域和漏极区域。该方法包括接收包含要在阵列中被编程的预定数量的位的编程窗口，并且确定在存储器阵列中哪个预定位数被编程。预定数量的位同时被编程到阵列中的对应存储器单元。同时验证阵列中预定位数的编程状态。

4. 发明申请

US20070064464A1 High performance flash memory device capable of high density data storage 有权
标题翻译：高性能闪存设备能够进行高密度数据存储
公开(公告)号：US20070064464A1
公开(公告)日：2007-03-22
申请号：US11229527
申请日：2005-09-20
申请人： Tiao-Hua Kuo , Nancy Leong , Nian Yang , Guowei Wang , Aaron Lee , Sachit Chandra , Michael VanBuskirk , Johnny Chen , Darlene Hamilton , Binh Le
发明人： Tiao-Hua Kuo , Nancy Leong , Nian Yang , Guowei Wang , Aaron Lee , Sachit Chandra , Michael VanBuskirk , Johnny Chen , Darlene Hamilton , Binh Le
IPC分类号： G11C17/00
CPC分类号： G11C5/147 , G11C16/12
摘要： A method is provided for programming a nonvolatile memory array including an array of memory cells, where each memory cell including a substrate, a control gate, a charge storage element, a source region and a drain region. The method includes receiving a programming window containing a predetermined number of bits that are to be programmed in the array and determining which of the predetermined number of bits are to be programmed in the memory array. The predetermined number of bits are simultaneously programmed to corresponding memory cells in the array. A programming state of the predetermined number of bits in the array is simultaneously verified.
摘要翻译：提供了一种用于对包括存储器单元阵列的非易失性存储器阵列进行编程的方法，其中每个存储单元包括衬底，控制栅极，电荷存储元件，源极区域和漏极区域。该方法包括接收包含要在阵列中被编程的预定数量的位的编程窗口，并且确定在存储器阵列中哪个预定位数被编程。预定数量的位同时被编程到阵列中的对应存储器单元。同时验证阵列中预定位数的编程状态。

5. 发明授权

US08358543B1 Flash memory programming with data dependent control of source lines 有权
标题翻译：闪存编程与数据相关的源行控制
公开(公告)号：US08358543B1
公开(公告)日：2013-01-22
申请号：US11229529
申请日：2005-09-20
申请人： Guowei Wang , Sachit Chandra , Nian Yang
发明人： Guowei Wang , Sachit Chandra , Nian Yang
IPC分类号： G11C16/00 , G11C16/04 , G11C16/06
CPC分类号： G11C16/0483 , G11C16/06 , G11C16/12
摘要： Techniques for programming a non-volatile memory device, such as a Flash memory, include floating source lines of memory cells based on a data pattern that is being programmed to the memory device. The source lines to float are selected such that a distance between drain bit lines and source bit lines of different memory cells in a row is maximized. In this manner, leakage current between these drain bit lines and source bit lines can be decreased.
摘要翻译：用于对诸如闪存之类的非易失性存储器件进行编程的技术包括基于正被编程到存储器件的数据模式的存储器单元的浮动源线。选择浮置的源极线使得排列位线和行中的不同存储器单元的源位线之间的距离最大化。以这种方式，可以减小这些漏极位线和源极线之间的漏电流。

6. 发明授权

US07453724B2 Flash memory device having improved program rate 有权
标题翻译：闪存设备具有改进的编程速率
公开(公告)号：US07453724B2
公开(公告)日：2008-11-18
申请号：US11931992
申请日：2007-10-31
申请人： Aaron Lee , Hounien Chen , Sachit Chandra , Nancy Leong , Guowei Wang
发明人： Aaron Lee , Hounien Chen , Sachit Chandra , Nancy Leong , Guowei Wang
IPC分类号： G11C11/34 , G11C16/06
CPC分类号： G11C16/0475 , G11C16/3454 , G11C16/3459
摘要： A method is provided for programming a nonvolatile memory device including an array of memory cells, where each memory cell including a substrate, a control gate, a charge storage element, a source region and a drain region. The method includes receiving a programming window that identifies a plurality of memory cells in the array. A first group of memory cells to be programmed is identified from the plurality of memory cells in the programming window. The first group of memory cells is programmed and a programming state of the first group of memory cells is verified.
摘要翻译：提供了一种用于对包括存储器单元阵列的非易失性存储器件进行编程的方法，其中每个存储器单元包括衬底，控制栅极，电荷存储元件，源极区域和漏极区域。该方法包括接收标识阵列中的多个存储单元的编程窗口。在编程窗口中从多个存储器单元识别要编程的第一组存储器单元。第一组存储器单元被编程，并且验证第一组存储器单元的编程状态。

7. 发明授权

US07307878B1 Flash memory device having improved program rate 有权
标题翻译：闪存设备具有改进的编程速率
公开(公告)号：US07307878B1
公开(公告)日：2007-12-11
申请号：US11212850
申请日：2005-08-29
申请人： Aaron Lee , Hounien Chen , Sachit Chandra , Nancy Leong , Guowei Wang
发明人： Aaron Lee , Hounien Chen , Sachit Chandra , Nancy Leong , Guowei Wang
IPC分类号： G11C11/34 , G11C16/06
CPC分类号： G11C16/0475 , G11C16/3454 , G11C16/3459
摘要： A method is provided for programming a nonvolatile memory device including an array of memory cells, where each memory cell including a substrate, a control gate, a charge storage element, a source region and a drain region. The method includes receiving a programming window that identifies a plurality of memory cells in the array. A first group of memory cells to be programmed is identified from the plurality of memory cells in the programming window. The first group of memory cells is programmed and a programming state of the first group of memory cells is verified.
摘要翻译：提供了一种用于对包括存储器单元阵列的非易失性存储器件进行编程的方法，其中每个存储器单元包括衬底，控制栅极，电荷存储元件，源极区域和漏极区域。该方法包括接收标识阵列中的多个存储单元的编程窗口。在编程窗口中从多个存储器单元识别要编程的第一组存储器单元。第一组存储器单元被编程，并且验证第一组存储器单元的编程状态。

8. 发明申请

US20070064480A1 Multi-bit flash memory device having improved program rate 有权
标题翻译：具有改进的程序速率的多位闪存设备
公开(公告)号：US20070064480A1
公开(公告)日：2007-03-22
申请号：US11229519
申请日：2005-09-20
申请人： Tiao-Hua Kuo , Nancy Leong , Hounien Chen , Sachit Chandra , Nian Yang
发明人： Tiao-Hua Kuo , Nancy Leong , Hounien Chen , Sachit Chandra , Nian Yang
IPC分类号： G11C16/04
CPC分类号： G11C16/0491 , G11C16/0475 , G11C16/10
摘要： A method is provided for programming a nonvolatile memory array including an array of memory cells, where each memory cell including a substrate, a control gate, a charge storage element having at least two charge storage areas for storing at least two independent charges, a source region and a drain region. The method includes designating at least one memory cell as a high-speed memory cell and pre-conditioning the high-speed memory cells by placing a first of the at least two charge storage areas into a programmed state, and subsequently enabling the programming on the second area with much higher rate.
摘要翻译：提供了一种用于对包括存储器单元阵列的非易失性存储器阵列进行编程的方法，其中每个存储器单元包括衬底，控制栅极，具有用于存储至少两个独立电荷的至少两个电荷存储区域的电荷存储元件，源区域和漏极区域。该方法包括将至少一个存储器单元指定为高速存储单元，并且通过将至少两个电荷存储区域中的第一个置于编程状态来预处理高速存储器单元，并且随后使能在第二个地区的利率要高得多。

9. 发明授权

US07679972B2 High reliable and low power static random access memory 有权
标题翻译：高可靠性和低功耗静态随机存取存储器
公开(公告)号：US07679972B2
公开(公告)日：2010-03-16
申请号：US11942526
申请日：2007-11-19
申请人： Jinsook Kim , Nian Yang , Hung-Jen Lin , Sachit Chandra
发明人： Jinsook Kim , Nian Yang , Hung-Jen Lin , Sachit Chandra
IPC分类号： G11C7/10
CPC分类号： G11C7/02 , G11C7/12 , G11C16/24
摘要： Systems and/or methods that accessing data to/from a memory are presented. A memory component can employ an optimized buffer component that can provide a single precharge control signal to facilitate precharging a bitline(s), a y-decoder component(s), an input/output line(s), and/or other lines or components associated with a buffer cell(s) in the optimized buffer component to facilitate optimized timing control associated with execution of operations to facilitate reducing errors that can be caused by charge sharing problems. The optimized buffer component can include an x-decoder component that can employ a JIT power component that can facilitate enabling a wordline associated with a buffer cell(s) only for the length of time access to the buffer cell is desired to read data therefrom or write data thereto to facilitate minimizing the access time and thereby minimize power consumption and/or thermal loading.
摘要翻译：提供了访问/从存储器访问数据的系统和/或方法。存储器组件可以使用优化的缓冲器组件，其可以提供单个预充电控制信号，以便于对位线，y解码器组件，输入/输出线和/或其他线路进行预充电，或者与优化的缓冲器组件中的缓冲器单元相关联的组件，以促进与执行操作相关联的优化的定时控制，以便于减少可能由电荷共享问题引起的错误。优化的缓冲器组件可以包括可以使用JIT功率组件的x解码器组件，该组件可以有助于实现与缓冲器单元相关联的字线，仅在长度时间内访问缓冲器单元才能从其读取数据，向其写入数据以便于最小化访问时间，从而最小化功耗和/或热负载。

10. 发明申请

US20090129172A1 HIGH RELIABLE AND LOW POWER STATIC RANDOM ACCESS MEMORY 有权
标题翻译：高可靠和低功率静态随机存取存储器
公开(公告)号：US20090129172A1
公开(公告)日：2009-05-21
申请号：US11942526
申请日：2007-11-19
申请人： Jinsook Kim , Nian Yang , Hung-Jen Lin , Sachit Chandra
发明人： Jinsook Kim , Nian Yang , Hung-Jen Lin , Sachit Chandra
IPC分类号： G11C7/10
CPC分类号： G11C7/02 , G11C7/12 , G11C16/24
摘要： Systems and/or methods that accessing data to/from a memory are presented. A memory component can employ an optimized buffer component that can provide a single precharge control signal to facilitate precharging a bitline(s), a y-decoder component(s), an input/output line(s), and/or other lines or components associated with a buffer cell(s) in the optimized buffer component to facilitate optimized timing control associated with execution of operations to facilitate reducing errors that can be caused by charge sharing problems. The optimized buffer component can include an x-decoder component that can employ a JIT power component that can facilitate enabling a wordline associated with a buffer cell(s) only for the length of time access to the buffer cell is desired to read data therefrom or write data thereto to facilitate minimizing the access time and thereby minimize power consumption and/or thermal loading.
摘要翻译：提供了访问/从存储器访问数据的系统和/或方法。存储器组件可以使用优化的缓冲器组件，其可以提供单个预充电控制信号，以便于对位线，y解码器组件，输入/输出线和/或其他线路进行预充电，或者与优化的缓冲器组件中的缓冲器单元相关联的组件，以促进与执行操作相关联的优化的定时控制，以便于减少可能由电荷共享问题引起的错误。优化的缓冲器组件可以包括可以使用JIT功率组件的x解码器组件，该组件可以有助于实现与缓冲器单元相关联的字线，仅在长度时间内访问缓冲器单元才能从其读取数据，向其写入数据以便于最小化访问时间，从而最小化功耗和/或热负载。

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