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1. 发明申请

US20110127530A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 有权
标题翻译：半导体集成电路设备
公开(公告)号：US20110127530A1
公开(公告)日：2011-06-02
申请号：US13025011
申请日：2011-02-10
申请人： YONG-HOON SON , Si-young Choi , Jong-wook Lee
发明人： YONG-HOON SON , Si-young Choi , Jong-wook Lee
IPC分类号： H01L29/772
CPC分类号： H01L29/785 , H01L29/66795
摘要： A method of fabricating a semiconductor integrated circuit includes forming a first dielectric layer on a semiconductor substrate, patterning the first dielectric layer to form a first patterned dielectric layer, forming a non-single crystal seed layer on the first patterned dielectric layer, removing a portion of the seed layer to form a patterned seed layer, forming a second dielectric layer on the first patterned dielectric layer and the patterned seed layer, removing portions of the second dielectric layer to form a second patterned dielectric layer, irradiating the patterned seed layer to single-crystallize the patterned seed layer, removing portions of the first patterned dielectric layer and the second patterned dielectric layer such that the single-crystallized seed layer protrudes in the vertical direction with respect to the first and/or the second patterned dielectric layer, and forming a gate electrode in contact with the single-crystal active pattern.
摘要翻译：一种制造半导体集成电路的方法包括在半导体衬底上形成第一电介质层，图案化第一电介质层以形成第一图案化电介质层，在第一图案化电介质层上形成非单晶种子层，的种子层以形成图案化种子层，在第一图案化介电层和图案化种子层上形成第二介电层，去除第二介电层的部分以形成第二图案化电介质层，将图案化种子层照射到单个将图案化种子层结晶，去除第一图案化电介质层和第二图案化电介质层的部分，使得单结晶种子层相对于第一和/或第二图案化电介质层在垂直方向上突出，并且形成与单晶活性图案接触的栅电极。

2. 发明申请

US20120097950A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND A METHOD OF FABRICATING THE SAME 有权
标题翻译：半导体集成电路装置及其制造方法
公开(公告)号：US20120097950A1
公开(公告)日：2012-04-26
申请号：US13343967
申请日：2012-01-05
申请人： Yong-hoon SON , Si-young Choi , Jong-wook Lee
发明人： Yong-hoon SON , Si-young Choi , Jong-wook Lee
IPC分类号： H01L29/786 , H01L21/28
CPC分类号： H01L29/785 , H01L29/66795
摘要： A method of fabricating a semiconductor integrated circuit includes forming a first dielectric layer on a semiconductor substrate, patterning the first dielectric layer to form a first patterned dielectric layer, forming a non-single crystal seed layer on the first patterned dielectric layer, removing a portion of the seed layer to form a patterned seed layer, forming a second dielectric layer on the first patterned dielectric layer and the patterned seed layer, removing portions of the second dielectric layer to form a second patterned dielectric layer, irradiating the patterned seed layer to single-crystallize the patterned seed layer, removing portions of the first patterned dielectric layer and the second patterned dielectric layer such that the single-crystallized seed layer protrudes in the vertical direction with respect to the first and/or the second patterned dielectric layer, and forming a gate electrode in contact with the single-crystal active pattern.
摘要翻译：一种制造半导体集成电路的方法包括在半导体衬底上形成第一电介质层，图案化第一电介质层以形成第一图案化电介质层，在第一图案化电介质层上形成非单晶种子层，的种子层以形成图案化种子层，在第一图案化介电层和图案化种子层上形成第二介电层，去除第二介电层的部分以形成第二图案化电介质层，将图案化种子层照射到单个将图案化种子层结晶，去除第一图案化电介质层和第二图案化电介质层的部分，使得单结晶种子层相对于第一和/或第二图案化电介质层在垂直方向上突出，并且形成与单晶活性图案接触的栅电极。

3. 发明授权

US08373165B2 Semiconductor integrated circuit device and a method of fabricating the same 有权
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US08373165B2
公开(公告)日：2013-02-12
申请号：US13343967
申请日：2012-01-05
申请人： Yong-hoon Son , Si-young Choi , Jong-wook Lee
发明人： Yong-hoon Son , Si-young Choi , Jong-wook Lee
IPC分类号： H01L29/04
CPC分类号： H01L29/785 , H01L29/66795
摘要： A method of fabricating a semiconductor integrated circuit includes forming a first dielectric layer on a semiconductor substrate, patterning the first dielectric layer to form a first patterned dielectric layer, forming a non-single crystal seed layer on the first patterned dielectric layer, removing a portion of the seed layer to form a patterned seed layer, forming a second dielectric layer on the first patterned dielectric layer and the patterned seed layer, removing portions of the second dielectric layer to form a second patterned dielectric layer, irradiating the patterned seed layer to single-crystallize the patterned seed layer, removing portions of the first patterned dielectric layer and the second patterned dielectric layer such that the single-crystallized seed layer protrudes in the vertical direction with respect to the first and/or the second patterned dielectric layer, and forming a gate electrode in contact with the single-crystal active pattern.
摘要翻译：一种制造半导体集成电路的方法包括在半导体衬底上形成第一电介质层，图案化第一电介质层以形成第一图案化电介质层，在第一图案化电介质层上形成非单晶种子层，的种子层以形成图案化种子层，在第一图案化介电层和图案化种子层上形成第二介电层，去除第二介电层的部分以形成第二图案化电介质层，将图案化种子层照射到单个将图案化种子层结晶，去除第一图案化电介质层和第二图案化电介质层的部分，使得单结晶种子层相对于第一和/或第二图案化电介质层在垂直方向上突出，并且形成与单晶活性图案接触的栅电极。

4. 发明授权

US07888246B2 Semiconductor integrated circuit device and a method of fabricating the same 有权
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US07888246B2
公开(公告)日：2011-02-15
申请号：US12073315
申请日：2008-03-04
申请人： Yong-hoon Son , Si-young Choi , Jong-wook Lee
发明人： Yong-hoon Son , Si-young Choi , Jong-wook Lee
IPC分类号： H01L21/36
CPC分类号： H01L29/785 , H01L29/66795
摘要： A method of fabricating a semiconductor integrated circuit includes forming a first dielectric layer on a semiconductor substrate, patterning the first dielectric layer to form a first patterned dielectric layer, forming a non-single crystal seed layer on the first patterned dielectric layer, removing a portion of the seed layer to form a patterned seed layer, forming a second dielectric layer on the first patterned dielectric layer and the patterned seed layer, removing portions of the second dielectric layer to form a second patterned dielectric layer, irradiating the patterned seed layer to single-crystallize the patterned seed layer, removing portions of the first patterned dielectric layer and the second patterned dielectric layer such that the single-crystallized seed layer protrudes in the vertical direction with respect to the first and/or the second patterned dielectric layer, and forming a gate electrode in contact with the single-crystal active pattern.
摘要翻译：一种制造半导体集成电路的方法包括在半导体衬底上形成第一电介质层，图案化第一电介质层以形成第一图案化电介质层，在第一图案化电介质层上形成非单晶种子层，的种子层以形成图案化种子层，在第一图案化介电层和图案化种子层上形成第二介电层，去除第二介电层的部分以形成第二图案化电介质层，将图案化种子层照射到单个将图案化种子层结晶，去除第一图案化电介质层和第二图案化电介质层的部分，使得单结晶种子层相对于第一和/或第二图案化电介质层在垂直方向上突出，并且形成与单晶活性图案接触的栅电极。

5. 发明授权

US08101509B2 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US08101509B2
公开(公告)日：2012-01-24
申请号：US13025011
申请日：2011-02-10
申请人： Yong-hoon Son , Si-young Choi , Jong-wook Lee
发明人： Yong-hoon Son , Si-young Choi , Jong-wook Lee
IPC分类号： H01L21/20
CPC分类号： H01L29/785 , H01L29/66795
摘要： A method of fabricating a semiconductor integrated circuit includes forming a first dielectric layer on a semiconductor substrate, patterning the first dielectric layer to form a first patterned dielectric layer, forming a non-single crystal seed layer on the first patterned dielectric layer, removing a portion of the seed layer to form a patterned seed layer, forming a second dielectric layer on the first patterned dielectric layer and the patterned seed layer, removing portions of the second dielectric layer to form a second patterned dielectric layer, irradiating the patterned seed layer to single-crystallize the patterned seed layer, removing portions of the first patterned dielectric layer and the second patterned dielectric layer such that the single-crystallized seed layer protrudes in the vertical direction with respect to the first and/or the second patterned dielectric layer, and forming a gate electrode in contact with the single-crystal active pattern.
摘要翻译：一种制造半导体集成电路的方法包括在半导体衬底上形成第一电介质层，图案化第一电介质层以形成第一图案化电介质层，在第一图案化电介质层上形成非单晶种子层，的种子层以形成图案化种子层，在第一图案化介电层和图案化种子层上形成第二介电层，去除第二介电层的部分以形成第二图案化电介质层，将图案化种子层照射到单个将图案化种子层结晶，去除第一图案化电介质层和第二图案化电介质层的部分，使得单结晶种子层相对于第一和/或第二图案化电介质层在垂直方向上突出，并且形成与单晶活性图案接触的栅电极。

6. 发明申请

US20080217616A1 Semiconductor integrated circuit device and a method of fabricating the same 有权
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US20080217616A1
公开(公告)日：2008-09-11
申请号：US12073315
申请日：2008-03-04
申请人： Yong-hoon Son , Si-young Choi , Jong-wook Lee
发明人： Yong-hoon Son , Si-young Choi , Jong-wook Lee
IPC分类号： H01L29/04 , H01L29/78 , H01L21/336
CPC分类号： H01L29/785 , H01L29/66795
摘要： A method of fabricating a semiconductor integrated circuit includes forming a first dielectric layer on a semiconductor substrate, patterning the first dielectric layer to form a first patterned dielectric layer, forming a non-single crystal seed layer on the first patterned dielectric layer, removing a portion of the seed layer to form a patterned seed layer, forming a second dielectric layer on the first patterned dielectric layer and the patterned seed layer, removing portions of the second dielectric layer to form a second patterned dielectric layer, irradiating the patterned seed layer to single-crystallize the patterned seed layer, removing portions of the first patterned dielectric layer and the second patterned dielectric layer such that the single-crystallized seed layer protrudes in the vertical direction with respect to the first and/or the second patterned dielectric layer, and forming a gate electrode in contact with the single-crystal active pattern.
摘要翻译：一种制造半导体集成电路的方法包括在半导体衬底上形成第一电介质层，图案化第一电介质层以形成第一图案化电介质层，在第一图案化电介质层上形成非单晶种子层，的种子层以形成图案化种子层，在第一图案化介电层和图案化种子层上形成第二介电层，去除第二介电层的部分以形成第二图案化电介质层，将图案化种子层照射到单个将图案化种子层结晶，去除第一图案化电介质层和第二图案化电介质层的部分，使得单结晶种子层相对于第一和/或第二图案化电介质层在垂直方向上突出，并且形成与单晶活性图案接触的栅电极。

7. 发明授权

US07081391B2 Integrated circuit devices having buried insulation layers and methods of forming the same 失效
标题翻译：具有掩埋绝缘层的集成电路器件及其形成方法
公开(公告)号：US07081391B2
公开(公告)日：2006-07-25
申请号：US10722193
申请日：2003-11-26
申请人： Byeong-chan Lee , Si-young Choi , Jong-ryeol Yoo , Yong-hoon Son , In-soo Jung , Deok-hyung Lee
发明人： Byeong-chan Lee , Si-young Choi , Jong-ryeol Yoo , Yong-hoon Son , In-soo Jung , Deok-hyung Lee
IPC分类号： H01L21/336
CPC分类号： H01L27/10873 , H01L21/823425 , H01L21/823481 , H01L27/10888
摘要： An integrated circuit device includes a gate electrode formed on an active region of an integrated circuit device and on a field isolation layer adjacent to the active region. A source region and a drain region are in the active region on alternate sides of the gate electrode. At least one buried insulation layer is beneath the drain region or the source region.
摘要翻译：集成电路器件包括形成在集成电路器件的有源区上的栅电极和与有源区相邻的场隔离层。源极区域和漏极区域在栅电极的交替侧上的有源区域中。至少一个掩埋绝缘层位于漏极区域或源极区域之下。

8. 发明申请

US20050179073A1 Integrated circuit devices having buried insulation layers and methods of forming the same 失效
标题翻译：具有掩埋绝缘层的集成电路器件及其形成方法
公开(公告)号：US20050179073A1
公开(公告)日：2005-08-18
申请号：US10722193
申请日：2003-11-26
申请人： Byeong-chan Lee , Si-young Choi , Jong-ryeol Yoo , Yong-hoon Son , In-soo Jung , Deok-hyung Lee
发明人： Byeong-chan Lee , Si-young Choi , Jong-ryeol Yoo , Yong-hoon Son , In-soo Jung , Deok-hyung Lee
IPC分类号： H01L21/8234 , H01L21/8242 , H01L29/76
CPC分类号： H01L27/10873 , H01L21/823425 , H01L21/823481 , H01L27/10888
摘要： An integrated circuit device includes a gate electrode formed on an active region of an integrated circuit device and on a field isolation layer adjacent to the active region. A source region and a drain region are in the active region on alternate sides of the gate electrode. At least one buried insulation layer is beneath the drain region or the source region.
摘要翻译：集成电路器件包括形成在集成电路器件的有源区上的栅电极和与有源区相邻的场隔离层。源极区域和漏极区域在栅电极的交替侧上的有源区域中。至少一个掩埋绝缘层位于漏极区域或源极区域之下。

9. 发明申请

US20060226455A1 Integrated circuit devices having buried insulation layers and methods of forming the same 审中-公开
公开(公告)号：US20060226455A1
公开(公告)日：2006-10-12
申请号：US11450725
申请日：2006-06-09
申请人： Byeong-chan Lee , Si-young Choi , Jong-ryeol Yoo , Yong-hoon Son , In-soo Jung , Deok-hyung Lee
发明人： Byeong-chan Lee , Si-young Choi , Jong-ryeol Yoo , Yong-hoon Son , In-soo Jung , Deok-hyung Lee
IPC分类号： H01L29/76
CPC分类号： H01L27/10873 , H01L21/823425 , H01L21/823481 , H01L27/10888
摘要： An integrated circuit device includes a gate electrode formed on an active region of an integrated circuit device and on a field isolation layer adjacent to the active region. A source region and a drain region are in the active region on alternate sides of the gate electrode. At least one buried insulation layer is beneath the drain region or the source region.

10. 发明授权

US08273620B2 Semiconductor integrated circuit device and related fabrication method 有权
标题翻译：半导体集成电路器件及相关制造方法
公开(公告)号：US08273620B2
公开(公告)日：2012-09-25
申请号：US12793809
申请日：2010-06-04
申请人： Jin-bum Kim , Young-pil Kim , Si-young Choi , Byeong-chan Lee , Jong-wook Lee
发明人： Jin-bum Kim , Young-pil Kim , Si-young Choi , Byeong-chan Lee , Jong-wook Lee
IPC分类号： H01L21/8234
CPC分类号： H01L21/823418 , H01L21/823456 , H01L27/105 , H01L27/1052
摘要： Embodiments of the invention provide a semiconductor integrated circuit device and a method for fabricating the device. The semiconductor device includes a semiconductor substrate having a cell region and a peripheral region, a cell active region formed in the cell region, and a peripheral active region formed in the peripheral region, wherein the cell active region and the peripheral active region are defined by isolation regions. The semiconductor device further includes a first gate stack formed on the cell active region, a second gate stack formed on the peripheral active region, a cell epitaxial layer formed on an exposed portion of the cell active region, and a peripheral epitaxial layer formed on an exposed portion of the peripheral active region, wherein the height of the peripheral epitaxial layer is greater than the height of the cell epitaxial layer.
摘要翻译：本发明的实施例提供一种半导体集成电路器件及其制造方法。半导体器件包括具有单元区域和周边区域的半导体衬底，形成在单元区域中的单元有源区域和形成在周边区域中的外围有源区域，其中，电池有源区域和外围有源区域由隔离区。半导体器件还包括形成在单元有源区上的第一栅极堆叠，形成在外围有源区上的第二栅极堆叠，形成在电池有源区域的暴露部分上的电池外延层和形成在电池有源区上的外围外延层所述周边有源区的暴露部分，其中所述外围外延层的高度大于所述电池外延层的高度。

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