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1. 发明申请

US20120097950A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND A METHOD OF FABRICATING THE SAME 有权
标题翻译：半导体集成电路装置及其制造方法
公开(公告)号：US20120097950A1
公开(公告)日：2012-04-26
申请号：US13343967
申请日：2012-01-05
申请人： Yong-hoon SON , Si-young Choi , Jong-wook Lee
发明人： Yong-hoon SON , Si-young Choi , Jong-wook Lee
IPC分类号： H01L29/786 , H01L21/28
CPC分类号： H01L29/785 , H01L29/66795
摘要： A method of fabricating a semiconductor integrated circuit includes forming a first dielectric layer on a semiconductor substrate, patterning the first dielectric layer to form a first patterned dielectric layer, forming a non-single crystal seed layer on the first patterned dielectric layer, removing a portion of the seed layer to form a patterned seed layer, forming a second dielectric layer on the first patterned dielectric layer and the patterned seed layer, removing portions of the second dielectric layer to form a second patterned dielectric layer, irradiating the patterned seed layer to single-crystallize the patterned seed layer, removing portions of the first patterned dielectric layer and the second patterned dielectric layer such that the single-crystallized seed layer protrudes in the vertical direction with respect to the first and/or the second patterned dielectric layer, and forming a gate electrode in contact with the single-crystal active pattern.
摘要翻译：一种制造半导体集成电路的方法包括在半导体衬底上形成第一电介质层，图案化第一电介质层以形成第一图案化电介质层，在第一图案化电介质层上形成非单晶种子层，的种子层以形成图案化种子层，在第一图案化介电层和图案化种子层上形成第二介电层，去除第二介电层的部分以形成第二图案化电介质层，将图案化种子层照射到单个将图案化种子层结晶，去除第一图案化电介质层和第二图案化电介质层的部分，使得单结晶种子层相对于第一和/或第二图案化电介质层在垂直方向上突出，并且形成与单晶活性图案接触的栅电极。

2. 发明申请

US20110127530A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 有权
标题翻译：半导体集成电路设备
公开(公告)号：US20110127530A1
公开(公告)日：2011-06-02
申请号：US13025011
申请日：2011-02-10
申请人： YONG-HOON SON , Si-young Choi , Jong-wook Lee
发明人： YONG-HOON SON , Si-young Choi , Jong-wook Lee
IPC分类号： H01L29/772
CPC分类号： H01L29/785 , H01L29/66795
摘要： A method of fabricating a semiconductor integrated circuit includes forming a first dielectric layer on a semiconductor substrate, patterning the first dielectric layer to form a first patterned dielectric layer, forming a non-single crystal seed layer on the first patterned dielectric layer, removing a portion of the seed layer to form a patterned seed layer, forming a second dielectric layer on the first patterned dielectric layer and the patterned seed layer, removing portions of the second dielectric layer to form a second patterned dielectric layer, irradiating the patterned seed layer to single-crystallize the patterned seed layer, removing portions of the first patterned dielectric layer and the second patterned dielectric layer such that the single-crystallized seed layer protrudes in the vertical direction with respect to the first and/or the second patterned dielectric layer, and forming a gate electrode in contact with the single-crystal active pattern.
摘要翻译：一种制造半导体集成电路的方法包括在半导体衬底上形成第一电介质层，图案化第一电介质层以形成第一图案化电介质层，在第一图案化电介质层上形成非单晶种子层，的种子层以形成图案化种子层，在第一图案化介电层和图案化种子层上形成第二介电层，去除第二介电层的部分以形成第二图案化电介质层，将图案化种子层照射到单个将图案化种子层结晶，去除第一图案化电介质层和第二图案化电介质层的部分，使得单结晶种子层相对于第一和/或第二图案化电介质层在垂直方向上突出，并且形成与单晶活性图案接触的栅电极。

3. 发明授权

US08101509B2 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US08101509B2
公开(公告)日：2012-01-24
申请号：US13025011
申请日：2011-02-10
申请人： Yong-hoon Son , Si-young Choi , Jong-wook Lee
发明人： Yong-hoon Son , Si-young Choi , Jong-wook Lee
IPC分类号： H01L21/20
CPC分类号： H01L29/785 , H01L29/66795
摘要： A method of fabricating a semiconductor integrated circuit includes forming a first dielectric layer on a semiconductor substrate, patterning the first dielectric layer to form a first patterned dielectric layer, forming a non-single crystal seed layer on the first patterned dielectric layer, removing a portion of the seed layer to form a patterned seed layer, forming a second dielectric layer on the first patterned dielectric layer and the patterned seed layer, removing portions of the second dielectric layer to form a second patterned dielectric layer, irradiating the patterned seed layer to single-crystallize the patterned seed layer, removing portions of the first patterned dielectric layer and the second patterned dielectric layer such that the single-crystallized seed layer protrudes in the vertical direction with respect to the first and/or the second patterned dielectric layer, and forming a gate electrode in contact with the single-crystal active pattern.
摘要翻译：一种制造半导体集成电路的方法包括在半导体衬底上形成第一电介质层，图案化第一电介质层以形成第一图案化电介质层，在第一图案化电介质层上形成非单晶种子层，的种子层以形成图案化种子层，在第一图案化介电层和图案化种子层上形成第二介电层，去除第二介电层的部分以形成第二图案化电介质层，将图案化种子层照射到单个将图案化种子层结晶，去除第一图案化电介质层和第二图案化电介质层的部分，使得单结晶种子层相对于第一和/或第二图案化电介质层在垂直方向上突出，并且形成与单晶活性图案接触的栅电极。

4. 发明申请

US20080217616A1 Semiconductor integrated circuit device and a method of fabricating the same 有权
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US20080217616A1
公开(公告)日：2008-09-11
申请号：US12073315
申请日：2008-03-04
申请人： Yong-hoon Son , Si-young Choi , Jong-wook Lee
发明人： Yong-hoon Son , Si-young Choi , Jong-wook Lee
IPC分类号： H01L29/04 , H01L29/78 , H01L21/336
CPC分类号： H01L29/785 , H01L29/66795
摘要： A method of fabricating a semiconductor integrated circuit includes forming a first dielectric layer on a semiconductor substrate, patterning the first dielectric layer to form a first patterned dielectric layer, forming a non-single crystal seed layer on the first patterned dielectric layer, removing a portion of the seed layer to form a patterned seed layer, forming a second dielectric layer on the first patterned dielectric layer and the patterned seed layer, removing portions of the second dielectric layer to form a second patterned dielectric layer, irradiating the patterned seed layer to single-crystallize the patterned seed layer, removing portions of the first patterned dielectric layer and the second patterned dielectric layer such that the single-crystallized seed layer protrudes in the vertical direction with respect to the first and/or the second patterned dielectric layer, and forming a gate electrode in contact with the single-crystal active pattern.
摘要翻译：一种制造半导体集成电路的方法包括在半导体衬底上形成第一电介质层，图案化第一电介质层以形成第一图案化电介质层，在第一图案化电介质层上形成非单晶种子层，的种子层以形成图案化种子层，在第一图案化介电层和图案化种子层上形成第二介电层，去除第二介电层的部分以形成第二图案化电介质层，将图案化种子层照射到单个将图案化种子层结晶，去除第一图案化电介质层和第二图案化电介质层的部分，使得单结晶种子层相对于第一和/或第二图案化电介质层在垂直方向上突出，并且形成与单晶活性图案接触的栅电极。

5. 发明授权

US08373165B2 Semiconductor integrated circuit device and a method of fabricating the same 有权
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US08373165B2
公开(公告)日：2013-02-12
申请号：US13343967
申请日：2012-01-05
申请人： Yong-hoon Son , Si-young Choi , Jong-wook Lee
发明人： Yong-hoon Son , Si-young Choi , Jong-wook Lee
IPC分类号： H01L29/04
CPC分类号： H01L29/785 , H01L29/66795
摘要： A method of fabricating a semiconductor integrated circuit includes forming a first dielectric layer on a semiconductor substrate, patterning the first dielectric layer to form a first patterned dielectric layer, forming a non-single crystal seed layer on the first patterned dielectric layer, removing a portion of the seed layer to form a patterned seed layer, forming a second dielectric layer on the first patterned dielectric layer and the patterned seed layer, removing portions of the second dielectric layer to form a second patterned dielectric layer, irradiating the patterned seed layer to single-crystallize the patterned seed layer, removing portions of the first patterned dielectric layer and the second patterned dielectric layer such that the single-crystallized seed layer protrudes in the vertical direction with respect to the first and/or the second patterned dielectric layer, and forming a gate electrode in contact with the single-crystal active pattern.
摘要翻译：一种制造半导体集成电路的方法包括在半导体衬底上形成第一电介质层，图案化第一电介质层以形成第一图案化电介质层，在第一图案化电介质层上形成非单晶种子层，的种子层以形成图案化种子层，在第一图案化介电层和图案化种子层上形成第二介电层，去除第二介电层的部分以形成第二图案化电介质层，将图案化种子层照射到单个将图案化种子层结晶，去除第一图案化电介质层和第二图案化电介质层的部分，使得单结晶种子层相对于第一和/或第二图案化电介质层在垂直方向上突出，并且形成与单晶活性图案接触的栅电极。

6. 发明授权

US07888246B2 Semiconductor integrated circuit device and a method of fabricating the same 有权
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US07888246B2
公开(公告)日：2011-02-15
申请号：US12073315
申请日：2008-03-04
申请人： Yong-hoon Son , Si-young Choi , Jong-wook Lee
发明人： Yong-hoon Son , Si-young Choi , Jong-wook Lee
IPC分类号： H01L21/36
CPC分类号： H01L29/785 , H01L29/66795
摘要： A method of fabricating a semiconductor integrated circuit includes forming a first dielectric layer on a semiconductor substrate, patterning the first dielectric layer to form a first patterned dielectric layer, forming a non-single crystal seed layer on the first patterned dielectric layer, removing a portion of the seed layer to form a patterned seed layer, forming a second dielectric layer on the first patterned dielectric layer and the patterned seed layer, removing portions of the second dielectric layer to form a second patterned dielectric layer, irradiating the patterned seed layer to single-crystallize the patterned seed layer, removing portions of the first patterned dielectric layer and the second patterned dielectric layer such that the single-crystallized seed layer protrudes in the vertical direction with respect to the first and/or the second patterned dielectric layer, and forming a gate electrode in contact with the single-crystal active pattern.
摘要翻译：一种制造半导体集成电路的方法包括在半导体衬底上形成第一电介质层，图案化第一电介质层以形成第一图案化电介质层，在第一图案化电介质层上形成非单晶种子层，的种子层以形成图案化种子层，在第一图案化介电层和图案化种子层上形成第二介电层，去除第二介电层的部分以形成第二图案化电介质层，将图案化种子层照射到单个将图案化种子层结晶，去除第一图案化电介质层和第二图案化电介质层的部分，使得单结晶种子层相对于第一和/或第二图案化电介质层在垂直方向上突出，并且形成与单晶活性图案接触的栅电极。

7. 发明授权

US08273620B2 Semiconductor integrated circuit device and related fabrication method 有权
标题翻译：半导体集成电路器件及相关制造方法
公开(公告)号：US08273620B2
公开(公告)日：2012-09-25
申请号：US12793809
申请日：2010-06-04
申请人： Jin-bum Kim , Young-pil Kim , Si-young Choi , Byeong-chan Lee , Jong-wook Lee
发明人： Jin-bum Kim , Young-pil Kim , Si-young Choi , Byeong-chan Lee , Jong-wook Lee
IPC分类号： H01L21/8234
CPC分类号： H01L21/823418 , H01L21/823456 , H01L27/105 , H01L27/1052
摘要： Embodiments of the invention provide a semiconductor integrated circuit device and a method for fabricating the device. The semiconductor device includes a semiconductor substrate having a cell region and a peripheral region, a cell active region formed in the cell region, and a peripheral active region formed in the peripheral region, wherein the cell active region and the peripheral active region are defined by isolation regions. The semiconductor device further includes a first gate stack formed on the cell active region, a second gate stack formed on the peripheral active region, a cell epitaxial layer formed on an exposed portion of the cell active region, and a peripheral epitaxial layer formed on an exposed portion of the peripheral active region, wherein the height of the peripheral epitaxial layer is greater than the height of the cell epitaxial layer.
摘要翻译：本发明的实施例提供一种半导体集成电路器件及其制造方法。半导体器件包括具有单元区域和周边区域的半导体衬底，形成在单元区域中的单元有源区域和形成在周边区域中的外围有源区域，其中，电池有源区域和外围有源区域由隔离区。半导体器件还包括形成在单元有源区上的第一栅极堆叠，形成在外围有源区上的第二栅极堆叠，形成在电池有源区域的暴露部分上的电池外延层和形成在电池有源区上的外围外延层所述周边有源区的暴露部分，其中所述外围外延层的高度大于所述电池外延层的高度。

8. 发明授权

US07755133B2 Semiconductor integrated circuit device and related fabrication method 有权
标题翻译：半导体集成电路器件及相关制造方法
公开(公告)号：US07755133B2
公开(公告)日：2010-07-13
申请号：US11855529
申请日：2007-09-14
申请人： Jin-bum Kim , Young-pil Kim , Si-young Choi , Byeong-chan Lee , Jong-wook Lee
发明人： Jin-bum Kim , Young-pil Kim , Si-young Choi , Byeong-chan Lee , Jong-wook Lee
IPC分类号： H01L29/788
CPC分类号： H01L21/823418 , H01L21/823456 , H01L27/105 , H01L27/1052
摘要： Embodiments of the invention provide a semiconductor integrated circuit device and a method for fabricating the device. The semiconductor device includes a semiconductor substrate having a cell region and a peripheral region, a cell active region formed in the cell region, and a peripheral active region formed in the peripheral region, wherein the cell active region and the peripheral active region are defined by isolation regions. The semiconductor device further includes a first gate stack formed on the cell active region, a second gate stack formed on the peripheral active region, a cell epitaxial layer formed on an exposed portion of the cell active region, and a peripheral epitaxial layer formed on an exposed portion of the peripheral active region, wherein the height of the peripheral epitaxial layer is greater than the height of the cell epitaxial layer.
摘要翻译：本发明的实施例提供一种半导体集成电路器件及其制造方法。半导体器件包括具有单元区域和周边区域的半导体衬底，形成在单元区域中的单元有源区域和形成在周边区域中的外围有源区域，其中，电池有源区域和外围有源区域由隔离区。半导体器件还包括形成在单元有源区上的第一栅极堆叠，形成在外围有源区上的第二栅极堆叠，形成在电池有源区域的暴露部分上的电池外延层和形成在电池有源区上的外围外延层所述周边有源区的暴露部分，其中所述外围外延层的高度大于所述电池外延层的高度。

9. 发明申请

US20100068868A1 Wafer temporary bonding method using silicon direct bonding 有权
标题翻译：晶圆临时接合方法采用硅直接接合
公开(公告)号：US20100068868A1
公开(公告)日：2010-03-18
申请号：US12585537
申请日：2009-09-17
申请人： Jung-ho Kim , Dae-lok Bae , Jong-wook Lee , Seung-woo Choi , Pil-kyu Kang
发明人： Jung-ho Kim , Dae-lok Bae , Jong-wook Lee , Seung-woo Choi , Pil-kyu Kang
IPC分类号： H01L21/762
CPC分类号： H01L21/6835 , H01L24/83 , H01L24/94 , H01L25/50 , H01L2221/6835 , H01L2221/68359 , H01L2224/83 , H01L2924/01005 , H01L2924/01006 , H01L2924/01021 , H01L2924/01033 , H01L2924/01047 , H01L2924/10253 , H01L2924/00
摘要： A wafer temporary bonding method using silicon direct bonding (SDB) may include preparing a carrier wafer and a device wafer, adjusting roughness of a surface of the carrier wafer, and combining the carrier wafer and the device wafer using the SDB. Because the method uses SDB, instead of an adhesive layer, for a temporary bonding process, a module or process to generate and remove an adhesive is unnecessary. Also, a defect in a subsequent process, for example, a back-grinding process, due to irregularity of the adhesive may be prevented.
摘要翻译：使用硅直接接合（SDB）的晶片临时接合方法可以包括制备载体晶片和器件晶片，调整载体晶片的表面的粗糙度，以及使用SDB组合载体晶片和器件晶片。因为该方法使用SDB而不是粘合剂层用于临时粘接过程，所以不需要用于产生和去除粘合剂的模块或工艺。此外，可以防止由于粘合剂的不规则性而导致的后续工艺中的缺陷，例如后磨削工艺。

10. 发明申请

US20060292783A1 CMOS transistor and method of manufacturing the same 有权
标题翻译： CMOS晶体管及其制造方法
公开(公告)号：US20060292783A1
公开(公告)日：2006-12-28
申请号：US11363176
申请日：2006-02-28
申请人： Young-eun Lee , Seong-ghil Lee , Yu-gyun Shin , Jong-wook Lee , Young-pil Kim
发明人： Young-eun Lee , Seong-ghil Lee , Yu-gyun Shin , Jong-wook Lee , Young-pil Kim
IPC分类号： H01L21/8238 , H01L29/80
CPC分类号： H01L21/823814 , H01L21/823807 , H01L21/823842 , H01L21/823864 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7848
摘要： A CMOS transistor structure and related method of manufacture are disclosed in which a first conductivity type MOS transistor comprises an enhancer and a second conductivity type MOS transistor comprises a second spacer formed of the same material as the enhancer. The second conductivity type MOS transistor also comprises a source/drain region formed in relation to an epitaxial layer formed in a recess region.
摘要翻译：公开了一种CMOS晶体管结构及相关的制造方法，其中第一导电型MOS晶体管包括增强器，第二导电类型MOS晶体管包括由与增强器相同的材料形成的第二间隔物。第二导电型MOS晶体管还包括相对于形成在凹陷区域中的外延层形成的源极/漏极区域。

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