专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08846514B2 Thin film transistor array panel and manufacturing method thereof 有权
标题翻译：薄膜晶体管阵列面板及其制造方法
公开(公告)号：US08846514B2
公开(公告)日：2014-09-30
申请号：US13559931
申请日：2012-07-27
申请人： Sang Ho Park , Yoon Ho Khang , Se Hwan Yu , Yong Su Lee , Chong Sup Chang , Myoung Geun Cha , Hyun Jae Na
发明人： Sang Ho Park , Yoon Ho Khang , Se Hwan Yu , Yong Su Lee , Chong Sup Chang , Myoung Geun Cha , Hyun Jae Na
IPC分类号： H01L29/786 , H01L21/28 , H01L27/12
CPC分类号： H01L27/124 , H01L27/1214 , H01L29/41758 , H01L29/458 , H01L29/78642 , H01L29/78669 , H01L29/78678
摘要： A thin film transistor array panel according to an exemplary embodiment of the present disclosure includes: an insulating substrate; a gate electrode disposed on the insulating substrate; a gate insulating layer disposed on the gate electrode; a semiconductor disposed on the gate insulating layer; a source electrode and a drain electrode disposed on the semiconductor; an ohmic contact layer disposed at an interface between at least one of the source and drain electrodes and the semiconductor. Surface heights of the source and drain electrodes different, while surface heights of the semiconductor and the ohmic contact layer are the same. The ohmic contact layer is made of a silicide of a metal used for the source and drain electrodes.
摘要翻译：根据本公开的示例性实施例的薄膜晶体管阵列面板包括：绝缘基板; 设置在所述绝缘基板上的栅电极; 设置在栅电极上的栅极绝缘层; 设置在所述栅极绝缘层上的半导体; 设置在半导体上的源电极和漏电极; 欧姆接触层设置在源电极和漏电极中的至少一个与半导体之间的界面处。源极和漏极的表面高度不同，而半导体和欧姆接触层的表面高度相同。欧姆接触层由用于源极和漏极的金属的硅化物制成。

2. 发明授权

US08653515B2 Thin film transistor and thin film transistor array panel 有权
标题翻译：薄膜晶体管和薄膜晶体管阵列面板
公开(公告)号：US08653515B2
公开(公告)日：2014-02-18
申请号：US13367076
申请日：2012-02-06
申请人： Yong-Su Lee , Yoon Ho Khang , Se Hwan Yu , Chong Sup Chang
发明人： Yong-Su Lee , Yoon Ho Khang , Se Hwan Yu , Chong Sup Chang
IPC分类号： H01L29/10
CPC分类号： H01L29/458 , H01L29/45 , H01L29/78618 , H01L29/7869
摘要： Provided is a thin film transistor and thin film transistor panel array. The thin film transistor includes: a substrate; a gate electrode disposed on the substrate; a semiconductor layer disposed on the substrate and partially overlapping with the gate electrode; a source electrode and a drain electrode spaced apart from each other with respect to a channel region of the semiconductor layer; an insulating layer disposed between the gate electrode and the semiconductor layer; and a barrier layer disposed between the semiconductor layer and the source electrode and between the semiconductor layer and the drain electrode, in which the barrier layer comprises graphene. An ohmic contact is provided based on the type of material used for the semiconductor layer.
摘要翻译：提供了一种薄膜晶体管和薄膜晶体管阵列阵列。薄膜晶体管包括：基板; 设置在所述基板上的栅电极; 设置在所述基板上并与所述栅电极部分重叠的半导体层; 源电极和漏电极相对于半导体层的沟道区彼此分开; 设置在所述栅电极和所述半导体层之间的绝缘层; 以及设置在所述半导体层和所述源电极之间以及所述半导体层和所述漏电极之间的阻挡层，其中所述阻挡层包括石墨烯。基于用于半导体层的材料的类型提供欧姆接触。

3. 发明授权

US08614781B2 Liquid crystal display and manufacturing method thereof having particular capping layer 有权
标题翻译：具有特定盖层的液晶显示器及其制造方法
公开(公告)号：US08614781B2
公开(公告)日：2013-12-24
申请号：US13409910
申请日：2012-03-01
申请人： Su-Hyoung Kang , Yoon Ho Khang , Se Hwan Yu , Yong Su Lee , Chong Sup Chang
发明人： Su-Hyoung Kang , Yoon Ho Khang , Se Hwan Yu , Yong Su Lee , Chong Sup Chang
IPC分类号： G02F1/1339 , G02F1/1333 , G02F1/1335
CPC分类号： G02F1/133377 , G02F1/1339 , G02F1/1341
摘要： A liquid crystal display is provided. The liquid crystal display includes a substrate. A thin film transistor is disposed on the substrate. A passivation layer is disposed on the thin film transistor. A pixel electrode is disposed on the passivation layer. A minute space layer is disposed on the pixel electrode and includes a liquid crystal injection hole. A first overcoat is disposed on the minute space layer. A common electrode is disposed on the first overcoat. A capping layer covers the liquid crystal injection hole. The capping layer includes graphene.
摘要翻译：提供液晶显示器。液晶显示器包括基板。薄膜晶体管设置在基板上。钝化层设置在薄膜晶体管上。像素电极设置在钝化层上。在像素电极上设置有微小的空间层，并且包括液晶注入孔。第一外涂层设置在微小空间层上。公共电极设置在第一外涂层上。盖层覆盖液晶注入孔。封盖层包括石墨烯。

4. 发明授权

US09252226B2 Thin film transistor array panel and manufacturing method thereof 有权
标题翻译：薄膜晶体管阵列面板及其制造方法
公开(公告)号：US09252226B2
公开(公告)日：2016-02-02
申请号：US13367061
申请日：2012-02-06
申请人： Do-Hyun Kim , Yoon Ho Khang , Dong-Hoon Lee , Sang Ho Park , Se Hwan Yu , Cheol Kyu Kim , Yong-Su Lee , Sung Haeng Cho , Chong Sup Chang , Dong Jo Kim , Jung Kyu Lee
发明人： Do-Hyun Kim , Yoon Ho Khang , Dong-Hoon Lee , Sang Ho Park , Se Hwan Yu , Cheol Kyu Kim , Yong-Su Lee , Sung Haeng Cho , Chong Sup Chang , Dong Jo Kim , Jung Kyu Lee
IPC分类号： H01L29/786 , H01L29/45 , H01L27/12
CPC分类号： H01L27/124 , H01L27/1225 , H01L27/1237 , H01L27/1262 , H01L27/127 , H01L27/1288 , H01L29/45 , H01L29/7869
摘要： Provided is a thin film transistor array panel. The thin film transistor array panel according to exemplary embodiments of the present invention includes: a gate wiring layer disposed on a substrate; an oxide semiconductor layer disposed on the gate wiring layer; and a data wiring layer disposed on the oxide semiconductor layer, in which the data wiring layer includes a main wiring layer including copper and a capping layer disposed on the main wiring layer and including a copper alloy.
摘要翻译：提供了一种薄膜晶体管阵列面板。根据本发明的示例性实施例的薄膜晶体管阵列面板包括：设置在基板上的栅极布线层; 设置在所述栅极布线层上的氧化物半导体层; 以及数据布线层，其设置在所述氧化物半导体层上，所述数据布线层包括包含铜的主布线层和设置在所述主布线层上并包括铜合金的覆盖层。

5. 发明授权

US08664654B2 Thin film transistor and thin film transistor array panel including the same 有权
标题翻译：薄膜晶体管和薄膜晶体管阵列面板包括它们
公开(公告)号：US08664654B2
公开(公告)日：2014-03-04
申请号：US13553418
申请日：2012-07-19
申请人： Yong Su Lee , Yoon Ho Khang , Dong Jo Kim , Hyun Jae Na , Sang Ho Park , Se Hwan Yu , Chong Sup Chang
发明人： Yong Su Lee , Yoon Ho Khang , Dong Jo Kim , Hyun Jae Na , Sang Ho Park , Se Hwan Yu , Chong Sup Chang
IPC分类号： H01L29/12
CPC分类号： H01L29/7869 , H01L21/0262 , H01L21/385 , H01L21/441 , H01L27/1214 , H01L27/1225 , H01L27/1259 , H01L27/1288 , H01L29/41733 , H01L29/66969 , H01L29/786 , H01L29/78633 , H01L29/78696
摘要： A thin film transistor, a thin film transistor array panel including the same, and a method of manufacturing the same are provided, wherein the thin film transistor includes a channel region including an oxide semiconductor, a source region and a drain region connected to the channel region and facing each other at both sides with respect to the channel region, an insulating layer positioned on the channel region, and a gate electrode positioned on the insulating layer, wherein an edge boundary of the gate electrode and an edge boundary of the channel region are substantially aligned.
摘要翻译：提供一种薄膜晶体管，包括该薄膜晶体管的薄膜晶体管阵列面板及其制造方法，其中薄膜晶体管包括沟道区，该沟道区包括氧化物半导体，源极区和连接到沟道的漏极区区域，并且相对于沟道区域在两侧面对，位于沟道区域上的绝缘层和位于绝缘层上的栅电极，其中栅电极的边缘边界和沟道区域的边缘边界基本对齐。

6. 发明申请

US20130256652A1 THIN FILM TRANSISTOR, THIN FILM TRANSISTOR ARRAY PANEL INCLUDING THE SAME, AND METHOD OF MANUFACTURING THE SAME 有权
公开(公告)号：US20130256652A1
公开(公告)日：2013-10-03
申请号：US13553418
申请日：2012-07-19
申请人： Yong Su LEE , Yoon Ho Khang , Dong Jo Kim , Hyun Jae Na , Sang Ho Park , Se Hwan Yu , Chong Sup Chang
发明人： Yong Su LEE , Yoon Ho Khang , Dong Jo Kim , Hyun Jae Na , Sang Ho Park , Se Hwan Yu , Chong Sup Chang
IPC分类号： H01L29/786 , H01L21/36
CPC分类号： H01L29/7869 , H01L21/0262 , H01L21/385 , H01L21/441 , H01L27/1214 , H01L27/1225 , H01L27/1259 , H01L27/1288 , H01L29/41733 , H01L29/66969 , H01L29/786 , H01L29/78633 , H01L29/78696
摘要： A thin film transistor, a thin film transistor array panel including the same, and a method of manufacturing the same are provided, wherein the thin film transistor includes a channel region including an oxide semiconductor, a source region and a drain region connected to the channel region and facing each other at both sides with respect to the channel region, an insulating layer positioned on the channel region, and a gate electrode positioned on the insulating layer, wherein an edge boundary of the gate electrode and an edge boundary of the channel region are substantially aligned.

7. 发明申请

US20130093985A1 LIQUID CRYSTAL DISPLAY AND MANUFACTURING METHOD THEREOF 有权
标题翻译：液晶显示及其制造方法
公开(公告)号：US20130093985A1
公开(公告)日：2013-04-18
申请号：US13409910
申请日：2012-03-01
申请人： SU-HYOUNG KANG , Yoon Ho Khang , Se Hwan Yu , Yong Su Lee , Chong Sup Chang
发明人： SU-HYOUNG KANG , Yoon Ho Khang , Se Hwan Yu , Yong Su Lee , Chong Sup Chang
IPC分类号： G02F1/1335 , H01L33/08 , G02F1/1333 , B82Y99/00
CPC分类号： G02F1/133377 , G02F1/1339 , G02F1/1341
摘要： A liquid crystal display is provided. The liquid crystal display includes a substrate. A thin film transistor is disposed on the substrate. A passivation layer is disposed on the thin film transistor. A pixel electrode is disposed on the passivation layer. A minute space layer is disposed on the pixel electrode and includes a liquid crystal injection hole. A first overcoat is disposed on the minute space layer. A common electrode is disposed on the first overcoat. A capping layer covers the liquid crystal injection hole. The capping layer includes graphene.
摘要翻译：提供液晶显示器。液晶显示器包括基板。薄膜晶体管设置在基板上。钝化层设置在薄膜晶体管上。像素电极设置在钝化层上。在像素电极上设置有微小的空间层，并且包括液晶注入孔。第一外涂层设置在微小空间层上。公共电极设置在第一外涂层上。盖层覆盖液晶注入孔。封盖层包括石墨烯。

8. 发明申请

US20130092942A1 THIN FILM TRANSISTOR ARRAY PANEL AND MANUFACTURING METHOD THEREOF 有权
标题翻译：薄膜晶体管阵列及其制造方法
公开(公告)号：US20130092942A1
公开(公告)日：2013-04-18
申请号：US13559931
申请日：2012-07-27
申请人： SANG HO PARK , Yoon Ho Khang , Se Hwan Yu , Yong Su Lee , Chong Sup Chang , Myoung Geun Cha , Hyun Jae Na
发明人： SANG HO PARK , Yoon Ho Khang , Se Hwan Yu , Yong Su Lee , Chong Sup Chang , Myoung Geun Cha , Hyun Jae Na
IPC分类号： H01L29/786 , H01L21/28 , H01L21/336 , H01L29/16
CPC分类号： H01L27/124 , H01L27/1214 , H01L29/41758 , H01L29/458 , H01L29/78642 , H01L29/78669 , H01L29/78678
摘要： A thin film transistor array panel according to an exemplary embodiment of the present disclosure includes: an insulating substrate; a gate electrode disposed on the insulating substrate; a gate insulating layer disposed on the gate electrode; a semiconductor disposed on the gate insulating layer; a source electrode and a drain electrode disposed on the semiconductor; an ohmic contact layer disposed at an interface between at least one of the source and drain electrodes and the semiconductor. Surface heights of the source and drain electrodes different, while surface heights of the semiconductor and the ohmic contact layer are the same. The ohmic contact layer is made of a silicide of a metal used for the source and drain electrodes.
摘要翻译：根据本公开的示例性实施例的薄膜晶体管阵列面板包括：绝缘基板; 设置在所述绝缘基板上的栅电极; 设置在栅电极上的栅极绝缘层; 设置在所述栅极绝缘层上的半导体; 设置在半导体上的源电极和漏电极; 欧姆接触层设置在源电极和漏电极中的至少一个与半导体之间的界面处。源极和漏极的表面高度不同，而半导体和欧姆接触层的表面高度相同。欧姆接触层由用于源极和漏极的金属的硅化物制成。

9. 发明授权

US08618538B2 Thin film transistor array panel and manufacturing method thereof 有权
标题翻译：薄膜晶体管阵列面板及其制造方法
公开(公告)号：US08618538B2
公开(公告)日：2013-12-31
申请号：US13099108
申请日：2011-05-02
申请人： Yoon Ho Khang , Se Hwan Yu , Chong Sup Chang , Sang Ho Park , Su-Hyoung Kang
发明人： Yoon Ho Khang , Se Hwan Yu , Chong Sup Chang , Sang Ho Park , Su-Hyoung Kang
IPC分类号： H01L29/12 , H01L29/45 , H01L29/786 , H01L21/336
CPC分类号： H01L27/1225 , H01L29/7869
摘要： A thin film transistor array panel is provided that includes: a gate electrode that is disposed on an insulating substrate; a gate insulating layer that is disposed on the gate electrode; an oxide semiconductor that is disposed on the gate insulating layer; a blocking layer that is disposed on the oxide semiconductor; a source electrode and a drain electrode that are disposed on the blocking layer; a passivation layer that is disposed on the source electrode and drain electrode; and a pixel electrode that is disposed on the passivation layer. The blocking layer includes a first portion that is covered by the source electrode and drain electrode and a second portion that is not covered by the source electrode and drain electrode, and the first portion and the second portion include different materials.
摘要翻译：提供薄膜晶体管阵列面板，其包括：设置在绝缘基板上的栅电极; 栅极绝缘层，设置在栅电极上; 设置在所述栅极绝缘层上的氧化物半导体; 设置在所述氧化物半导体上的阻挡层; 设置在所述阻挡层上的源电极和漏电极; 钝化层，其设置在所述源电极和所述漏电极上; 以及设置在钝化层上的像素电极。阻挡层包括由源电极和漏电极覆盖的第一部分和未被源电极和漏电极覆盖的第二部分，并且第一部分和第二部分包括不同的材料。

10. 发明申请

US20130098869A1 Method for Forming Minute Pattern and Method for Forming Minute Pattern Mask 有权
标题翻译：形成分钟图案的方法和形成分钟图案掩模的方法
公开(公告)号：US20130098869A1
公开(公告)日：2013-04-25
申请号：US13431516
申请日：2012-03-27
申请人： Se-Hwan Yu , Ji Seon Lee , Yoon Ho Khang , Kahp Yang Suh , Hyoung Sick Um , Jae Jun Chae , Sung Hun Lee
发明人： Se-Hwan Yu , Ji Seon Lee , Yoon Ho Khang , Kahp Yang Suh , Hyoung Sick Um , Jae Jun Chae , Sung Hun Lee
IPC分类号： B44C1/22
CPC分类号： G03F7/0002 , B82Y10/00 , B82Y40/00
摘要： A method for forming a minute pattern mask includes forming an etching target layer on a substrate. A convex pattern including a plurality of convex parts is formed on the etching target layer. A resin composition is coated on the convex pattern to form a resin layer including a first region neighboring the convex part and a second region positioned between the neighboring convex parts. The resin layer is ashed or etched to form the plurality of first resin patterns. The plurality of first resin patterns is processed to form a minute pattern mask including a plurality of second resin patterns. The etching target layer is etched using the plurality of second resin patterns as an etch mask to form a minute pattern.
摘要翻译：形成微图案掩模的方法包括在基板上形成蚀刻目标层。在蚀刻目标层上形成包括多个凸部的凸形图案。将树脂组合物涂覆在凸形图案上以形成包括邻近凸部的第一区域和位于相邻凸部之间的第二区域的树脂层。树脂层被灰化或蚀刻以形成多个第一树脂图案。处理多个第一树脂图案以形成包括多个第二树脂图案的微小图案掩模。使用多个第二树脂图案作为蚀刻掩模蚀刻蚀刻目标层以形成微小图案。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式