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1. 发明授权

US5412262A Semiconductor integrated circuit device having plurality of supply potential lines connected thereto, and system employing the same 失效
标题翻译：具有与其连接的多个电源电位线的半导体集成电路器件及其系统
公开(公告)号：US5412262A
公开(公告)日：1995-05-02
申请号：US279626
申请日：1994-07-25
申请人： Yoji Nishio , Fumio Murabayashi , Kozaburo Kurita , Masahiro Iwamura
发明人： Yoji Nishio , Fumio Murabayashi , Kozaburo Kurita , Masahiro Iwamura
IPC分类号： H03K19/00 , H01L27/02 , H03K19/0175 , H03K19/0185 , H03K19/02
CPC分类号： H03K19/017527 , H03K19/018521 , H01L27/0214
摘要： In a system wherein a plurality of semiconductor integrated circuit devices are coexistent and wherein a plurality of supply potential lines are laid, the main power sources of a TTL interface LSI and an ECL interface LSI are shared so as to reduce the number of supply potential lines. Besides, in a case where an LSI, for example, BiCMOS LSI to interface with both the TTL and ECL interface LSI's has a device withstand voltage of about 3 V, it is permitted to interface with both the LSI's across the supply voltage .vertline.5 V.vertline. of the main power source of the TTL interface LSI and the supply voltage .vertline.2 V.vertline. of the power source of the emitter follower portion of the ECL interface LSI because the supply voltages have a difference of 3 V.
摘要翻译：在其中多个半导体集成电路器件共存并且其中布置多条电源线的系统中，TTL接口LSI和ECL接口LSI的主电源被共享，以便减少电源电位线的数量。此外，在与例如TTL和ECL接口LSI接口的BiCMOS LSI的LSI具有约3V的器件耐受电压的情况下，允许与两者的两端的电源电压| 5V | 的TTL接口LSI的主电源和电源电压| 2 V | 由于电源电压具有3V的差异，所以ECL接口LSI的射极跟随器部分的电源。

2. 发明授权

US5666072A Semiconductor integrated circuit device having bipolar transistor and field effect transistor 失效
标题翻译：具有双极晶体管和场效应晶体管的半导体集成电路器件
公开(公告)号：US5666072A
公开(公告)日：1997-09-09
申请号：US223527
申请日：1994-04-05
申请人： Fumio Murabayashi , Yoji Nishio , Shoichi Kotoku , Kozaburo Kurita , Kazuo Kato
发明人： Fumio Murabayashi , Yoji Nishio , Shoichi Kotoku , Kozaburo Kurita , Kazuo Kato
IPC分类号： H01L29/73 , H01L21/331 , H01L21/82 , H01L27/06 , H01L27/118 , H01L29/732 , H03K17/04 , H03K17/16 , H03K17/567 , H03K19/00 , H03K19/003 , H03K19/08 , H03K19/0944 , H03K19/01
CPC分类号： H01L27/0623 , H03K19/001 , H03K19/00353 , H03K19/09448
摘要： A semiconductor integrated circuit device having a plurality of logic circuits integrated on a semiconductor substrate is provided which can operate with a power source potential difference substantially less than 5 V. The logic circuit includes a bipolar transistor having a base and its collector-emitter current path coupled between a first power source terminal and an output terminal, together with at least one field effect transistor having its gate responsive to an input signal applied to an input terminal and its source-drain current path coupled between the first power source terminal and the base of the bipolar transistor. A semiconductor switch means is also provided which is responsive to the input signal applied to the input terminal for performing ON/OFF operations complementary to the ON/OFF operations of the bipolar transistor and which has a current path between its paired main terminals coupled between the output terminal and the second power source terminal. In order to improve the operating speed, a potential difference reducing element is provided having a current path between its paired main terminals coupled between the first power source terminal and the output terminal for reducing the potential difference, which is present between the first power source terminal and the output terminal based on the base-emitter forward voltage of the bipolar transistor when the bipolar transistor is ON.
摘要翻译：提供了具有集成在半导体衬底上的多个逻辑电路的半导体集成电路器件，其可以以基本上小于5V的电源电位差工作。逻辑电路包括具有基极和其集电极 - 发射极电流路径的双极晶体管耦合在第一电源端子和输出端子之间，以及至少一个具有栅极的场效应晶体管，其响应于施加到输入端子的输入信号及其耦合在第一电源端子和基极之间的源极 - 漏极电流路径的双极晶体管。还提供一种半导体开关装置，其响应于施加到输入端子的输入信号，用于执行与双极晶体管的导通/截止操作互补的ON / OFF操作，并且在其双绞主端子之间具有电流通路输出端子和第二电源端子。为了提高工作速度，提供了一个电位差降低元件，其具有耦合在第一电源端子和输出端子之间的成对主端子之间的电流路径，用于减小电位差，该电位差存在于第一电源端子以及当双极晶体管导通时基于双极晶体管的基极 - 发射极正向电压的输出端子。

3. 发明授权

US5313116A Semiconductor integrated circuit device having bipolar transistor and field effect transistor 失效
标题翻译：具有双极晶体管和场效应晶体管的半导体集成电路器件
公开(公告)号：US5313116A
公开(公告)日：1994-05-17
申请号：US765018
申请日：1991-09-24
申请人： Fumio Murabayashi , Yoji Nishio , Shoichi Kotoku , Kozaburo Kurita , Kazuo Kato
发明人： Fumio Murabayashi , Yoji Nishio , Shoichi Kotoku , Kozaburo Kurita , Kazuo Kato
IPC分类号： H01L29/73 , H01L21/331 , H01L21/82 , H01L27/06 , H01L27/118 , H01L29/732 , H03K17/04 , H03K17/16 , H03K17/567 , H03K19/00 , H03K19/003 , H03K19/08 , H03K19/0944 , H03K19/01
CPC分类号： H01L27/0623 , H03K19/001 , H03K19/00353 , H03K19/09448
摘要： A semiconductor integrated circuit device having a plurality of logic circuits integrated on a semiconductor substrate is provided which can operate with a power source potential difference substantially less than 5 V. The logic circuit includes a bipolar transistor having a base and its collector-emitter current path coupled between a first power source terminal and an output terminal, together with at least one field effect transistor having its gate responsive to an input signal applied to an input terminal and its source-drain current path coupled between the first power source terminal and the base of the bipolar transistor. A semiconductor switch means is also provided which is responsive to the input signal applied to the input terminal for performing ON/OFF operations complementary to the ON/OFF operations of the bipolar transistor and which has a current path between its paired main terminals coupled between the output terminal and the second power source terminal. In order to improve the operating speed, a potential difference reducing element is provided having a current path between its paired main terminals coupled between the first power source terminal and the output terminal for reducing the potential difference, which is present between the first power source terminal and the output terminal based on the base-emitter forward voltage of the bipolar transistor when the bipolar transistor is ON.
摘要翻译：提供了具有集成在半导体衬底上的多个逻辑电路的半导体集成电路器件，其可以以基本上小于5V的电源电位差工作。逻辑电路包括具有基极和其集电极 - 发射极电流路径的双极晶体管耦合在第一电源端子和输出端子之间，以及至少一个具有栅极的场效应晶体管，其响应于施加到输入端子的输入信号及其耦合在第一电源端子和基极之间的源极 - 漏极电流路径的双极晶体管。还提供一种半导体开关装置，其响应于施加到输入端子的输入信号，用于执行与双极晶体管的导通/截止操作互补的ON / OFF操作，并且在其双绞主端子之间具有电流通路输出端子和第二电源端子。为了提高工作速度，提供了一个电位差降低元件，其具有耦合在第一电源端子和输出端子之间的成对主端子之间的电流路径，用于减小电位差，该电位差存在于第一电源端子以及当双极晶体管导通时基于双极晶体管的基极 - 发射极正向电压的输出端子。

4. 发明授权

US5059821A Bi-CMOS driver with two CMOS predrivers having different switching thresholds 失效
标题翻译：具有两个具有不同开关阈值的CMOS预驱动器的双CMOS驱动器
公开(公告)号：US5059821A
公开(公告)日：1991-10-22
申请号：US649854
申请日：1991-02-01
申请人： Fumio Murabayashi , Yoji Nishio , Shoichi Kotoku , Kozaburo Kurita , Kazuo Kato
发明人： Fumio Murabayashi , Yoji Nishio , Shoichi Kotoku , Kozaburo Kurita , Kazuo Kato
IPC分类号： H01L29/73 , H01L21/331 , H01L21/82 , H01L27/06 , H01L27/118 , H01L29/732 , H03K17/04 , H03K17/16 , H03K17/567 , H03K19/00 , H03K19/003 , H03K19/08 , H03K19/0944
CPC分类号： H01L27/0623 , H03K19/001 , H03K19/00353 , H03K19/09448
摘要： A semiconductor integrated circuit device having a plurality of logic circuits integrated on a semiconductor substrate is provided which can operate with a power source potential difference substantially less than 5V. The logic circuit includes a bipolar transistor having a base and its collector-emitter current path coupled between a first power source terminal and an output terminal, together with at least one field effect transistor having its gate responsive to an input signal applied to an input terminal and its source-drain current path coupled between the first power source terminal and the base of the bipolar transistor. A semiconductor switch means is also provided which is responsive to the input signal applied to the input terminal for performing ON/OFF operations complementary to the ON/OFF operations of the bipolar transistor and which has a current path between its paired main terminals coupled between the output terminal and the second power source terminal. In order to improve the operating speed, a potential difference reducing element is provided having a current path between its paired main terminals coupled between the first power source terminal and the output terminal for reducing the potential difference, which is present between the first power source terminal and the output terminal based on the base-emitter forward voltage of the bipolar transistor when the bipolar transistor is ON.
摘要翻译：提供了具有集成在半导体衬底上的多个逻辑电路的半导体集成电路器件，其可以以基本上小于5V的电源电位差工作。逻辑电路包括双极晶体管，其具有耦合在第一电源端子和输出端子之间的基极和集电极 - 发射极电流路径，以及至少一个场效应晶体管，其栅极响应于施加到输入端子的输入信号并且其源极 - 漏极电流路径耦合在第一电源端子和双极晶体管的基极之间。还提供一种半导体开关装置，其响应于施加到输入端子的输入信号，用于执行与双极晶体管的导通/截止操作互补的ON / OFF操作，并且在其双绞主端子之间具有电流通路输出端子和第二电源端子。为了提高工作速度，提供了一个电位差降低元件，其具有耦合在第一电源端子和输出端子之间的成对主端子之间的电流路径，用于减小电位差，该电位差存在于第一电源端子以及当双极晶体管导通时基于双极晶体管的基极 - 发射极正向电压的输出端子。

5. 发明授权

US5001365A Logic circuit using bipolar and field effect transistor, including a delayed switching arrangement 失效
标题翻译：使用双极和场效应晶体管的逻辑电路，包括延迟的开关布置
公开(公告)号：US5001365A
公开(公告)日：1991-03-19
申请号：US325911
申请日：1989-03-20
申请人： Fumio Murabayashi , Yoji Nishio , Shoichi Kotoku , Kozaburo Kurita , Kazuo Kato
发明人： Fumio Murabayashi , Yoji Nishio , Shoichi Kotoku , Kozaburo Kurita , Kazuo Kato
IPC分类号： H01L29/73 , H01L21/331 , H01L21/82 , H01L27/06 , H01L27/118 , H01L29/732 , H03K17/04 , H03K17/16 , H03K17/567 , H03K19/00 , H03K19/003 , H03K19/08 , H03K19/0944
CPC分类号： H01L27/0623 , H03K19/001 , H03K19/00353 , H03K19/09448
摘要： A semiconductor integrated circuit device having a plurality of logic circuits integrated on a semiconductor substrate is provided which can operate with a power source potential difference substantially less than 5 V. The logic circuit includes a bipolar transistor having a base and its collector-emitter current path coupled between a first power source terminal and an output terminal, together with at least one field effect transistor having its gate responsive to an input signal applied to an input terminal and its source-drain current path coupled between the first power source terminal and the base of the bipolar transistor. A semiconductor switch means is also provided which is responsive to the input signal applied to the input terminal for performing ON/OFF operations complementary to the ON/OFF operations of the bipolar transistor and which has a current path between its paired main terminals coupled between the output terminal and the second power source terminal. In order to improve the operating speed, a potential difference reducing element is provided having a current path between its paired main terminals coupled between the first power source terminal and the output terminal for reducing the potential difference, which is present between the first power source terminal and the output terminal based on the base-emitter forward voltage of the bipolar transistor when the bipolar transistor is ON.
摘要翻译：提供了具有集成在半导体衬底上的多个逻辑电路的半导体集成电路器件，其可以以基本上小于5V的电源电位差工作。逻辑电路包括具有基极和其集电极 - 发射极电流路径的双极晶体管耦合在第一电源端子和输出端子之间，以及至少一个具有栅极的场效应晶体管，其响应于施加到输入端子的输入信号及其耦合在第一电源端子和基极之间的源极 - 漏极电流路径的双极晶体管。还提供半导体开关装置，其响应于施加到输入端子的输入信号，用于执行与双极晶体管的导通/截止操作互补的ON / OFF操作，并且在其双绞主端子之间具有电流通路输出端子和第二电源端子。为了提高工作速度，提供了一个电位差降低元件，其具有耦合在第一电源端子和输出端子之间的成对主端子之间的电流路径，用于减小电位差，该电位差存在于第一电源端子以及当双极晶体管导通时基于双极晶体管的基极 - 发射极正向电压的输出端子。

6. 发明授权

US5265045A Semiconductor integrated circuit device with built-in memory circuit group 失效
标题翻译：具有内置存储电路组的半导体集成电路器件
公开(公告)号：US5265045A
公开(公告)日：1993-11-23
申请号：US793315
申请日：1991-11-15
申请人： Yoji Nishio , Fumio Murabayashi , Shoichi Kotoku , Akira Uragami , Manabu Shibata , Yoshitatsu Kojima , Fumiaki Matsuzaki
发明人： Yoji Nishio , Fumio Murabayashi , Shoichi Kotoku , Akira Uragami , Manabu Shibata , Yoshitatsu Kojima , Fumiaki Matsuzaki
IPC分类号： G11C5/06 , G11C8/16 , G11C7/00 , G11C5/00 , G11C8/00
CPC分类号： G11C8/16 , G11C5/063
摘要： A semiconductor integrated circuit device with a built-in memory circuit group is disclosed, wherein wiring is started from a data terminal position near a data exchange portion of a memory circuit group to reduce the length of a wiring. Accordingly, an operation speed can be improved by the reduction of wiring capacitance and a ratio of unwired wirings can be reduced by reduction of an occupying ratio of wiring channels.
摘要翻译：公开了一种具有内置存储器电路组的半导体集成电路器件，其中从存储器电路组的数据交换部分附近的数据终端位置开始布线以减少布线的长度。因此，可以通过减少布线电容来提高操作速度，并且可以通过降低布线通道的占有率来减少退绕布线的比率。

7. 发明授权

US5677641A Gate circuit and semiconductor circuit to process low amplitude signals, memory, processor and information processing system manufactured by use of them 失效
标题翻译：门电路和半导体电路来处理使用它们制造的低振幅信号，存储器，处理器和信息处理系统
公开(公告)号：US5677641A
公开(公告)日：1997-10-14
申请号：US423378
申请日：1995-04-18
申请人： Yoji Nishio , Kosaku Hirose , Hideo Hara , Katsunori Koike , Kayoko Nemoto , Tatsumi Yamauchi , Fumio Murabayashi , Hiromichi Yamada
发明人： Yoji Nishio , Kosaku Hirose , Hideo Hara , Katsunori Koike , Kayoko Nemoto , Tatsumi Yamauchi , Fumio Murabayashi , Hiromichi Yamada
IPC分类号： G11C11/41 , H03K3/3565 , H03K19/0185 , H03K19/0948
CPC分类号： H03K3/3565 , H03K19/018521
摘要： The object of the present invention is to provide a semiconductor integrated circuit device wherein the input signal is made to have a low amplitude to shorten transition time of the input signal, said integrated circuit device operating at a low power consumption, without flowing of breakthrough current, despite entry of the input signal featuring low-amplitude operations, and said integrated circuit device comprising a gate circuit, memory and processor. When input signal is supplied through the NMOS pass transistor, said input signal is input to the gate of the first NMOS transistor, and at the same time, is input into the gate of the first PMOS transistor which performs complementary operation with said first NMOS transistor through the second NMOS transistor; said first PMOS gate is connected to the power supply potential through the second PMOS transistor, and the gate of the said second NMOS transistor is connected to the power supply potential; wherein the gate of the said second PMOS transistor gate is controlled by the signal which is connected with both the drain of the said first NMOS transistor and the drain of the said first PMOS transistor.
摘要翻译：本发明的目的是提供一种半导体集成电路器件，其中使得输入信号具有低幅度以缩短输入信号的转换时间，所述集成电路器件以低功耗工作，而不流过突破电流尽管输入具有低幅度操作的输入信号，并且所述集成电路器件包括门电路，存储器和处理器。当通过NMOS传输晶体管提供输入信号时，所述输入信号被输入到第一NMOS晶体管的栅极，并且同时被输入到与所述第一NMOS晶体管执行互补操作的第一PMOS晶体管的栅极通过第二NMOS晶体管; 所述第一PMOS栅极通过第二PMOS晶体管连接到电源电位，并且所述第二NMOS晶体管的栅极连接到电源电位; 其中所述第二PMOS晶体管栅极的栅极由与所述第一NMOS晶体管的漏极和所述第一PMOS晶体管的漏极连接的信号控制。

8. 发明授权

US06657459B2 Gate circuit and semiconductor circuit to process low amplitude signals, memory, processor and information processing system manufactured by use of them 失效
公开(公告)号：US06657459B2
公开(公告)日：2003-12-02
申请号：US10143762
申请日：2002-05-14
申请人： Yoji Nishio , Kosaku Hirose , Hideo Hara , Katsunori Koike , Kayoko Nemoto , Tatsumi Yamauchi , Fumio Murabayashi , Hiromichi Yamada
发明人： Yoji Nishio , Kosaku Hirose , Hideo Hara , Katsunori Koike , Kayoko Nemoto , Tatsumi Yamauchi , Fumio Murabayashi , Hiromichi Yamada
IPC分类号： H03K19096
CPC分类号： H03K3/3565 , H03K19/018521
摘要： A semiconductor integrated circuit device, responsive to an input signal having a low amplitude and short transition time, operates with low power consumption and prevents the flow of breakthrough current. In an example circuit thereof, the input signal is transmitted through an NMOS pass transistor to the gate of a first NMOS transistor and is applied, through a second NMOS transistor, to the gate of a first PMOS transistor, the first PMOS transistor performing complementary operation with the first NMOS transistor through the second NMOS transistor; the gate of the first PMOS transistor is connected to the power supply potential through the second PMOS transistor; the gate of the second NMOS transistor is connected to the power supply potential; and the gate of the second PMOS transistor is controlled by the signal at a common drain connection of the first NMOS and first PMOS transistors.

9. 发明授权

US5377136A Semiconductor integrated circuit device with built-in memory circuit group 失效
标题翻译：具有内置存储电路组的半导体集成电路器件
公开(公告)号：US5377136A
公开(公告)日：1994-12-27
申请号：US076874
申请日：1993-06-15
申请人： Yoji Nishio , Fumio Murabayashi , Shoichi Kotoku , Akira Uragami , Manabu Shibata , Yoshitatsu Kojima , Fumiaki Matsuzaki
发明人： Yoji Nishio , Fumio Murabayashi , Shoichi Kotoku , Akira Uragami , Manabu Shibata , Yoshitatsu Kojima , Fumiaki Matsuzaki
IPC分类号： G11C5/06 , G11C8/16
CPC分类号： G11C8/16 , G11C5/063
摘要： A semiconductor integrated circuit device with a built-in memory circuit group is disclosed, wherein wiring is started from a data terminal position near a data exchange portion of a memory circuit group to reduce the length of a wiring. Accordingly, an operation speed can be improved by the reduction of wiring capacitance and a ratio of unwired wirings can be reduced by reduction of an occupying ratio of wiring channels.
摘要翻译：公开了一种具有内置存储器电路组的半导体集成电路器件，其中从存储器电路组的数据交换部分附近的数据终端位置开始布线以减少布线的长度。因此，可以通过减少布线电容来提高操作速度，并且可以通过降低布线通道的占有率来减少退绕布线的比率。

10. 发明授权

US06462580B2 Gate circuit and semiconductor circuit to process low amplitude signals, memory, processor and information processing system manufactured by use of them 失效
标题翻译：门电路和半导体电路来处理使用它们制造的低振幅信号，存储器，处理器和信息处理系统
公开(公告)号：US06462580B2
公开(公告)日：2002-10-08
申请号：US09749474
申请日：2000-12-28
申请人： Yoji Nishio , Kosaku Hirose , Hideo Hara , Katsunori Koike , Kayoko Nemoto , Tatsumi Yamauchi , Fumio Murabayashi , Hiromichi Yamada
发明人： Yoji Nishio , Kosaku Hirose , Hideo Hara , Katsunori Koike , Kayoko Nemoto , Tatsumi Yamauchi , Fumio Murabayashi , Hiromichi Yamada
IPC分类号： H03K19096
CPC分类号： H03K3/3565 , H03K19/018521
摘要： The object of the present invention to provide a semiconductor integrated circuit device wherein the input signal is made to have a low amplitude to shorten transition time of the input signal, said integrated circuit device operating at a low power consumption, without flowing of breakthrough current, despite entry of the input signal featuring low-amplitude operations, and said integrated circuit device comprising a gate circuit, memory and processor. When input signal is supplied through the NMOS pass transistor, said input signal is input to the gate of the first NMOS transistor, and at the same time, is input into the gate of the first PMOS transistor which performs complementary operation with said first NMOS transistor through the second NMOS transistor; said first PMOS gate is connected to the power supply potential through the second PMOS transistor, and the gate of the said second NMOS transistor is connected to the power supply potential; wherein the gate of the said second PMOS transistor gate is controlled by the signal which is connected with both the drain of the said first NMOS transistor and the drain of the said first PMOS transistor.
摘要翻译：本发明的目的是提供一种半导体集成电路器件，其中使得输入信号具有低振幅以缩短输入信号的转换时间，所述集成电路器件以低功耗工作，而不流过突破电流，尽管输入具有低幅度操作的输入信号，并且所述集成电路器件包括门电路，存储器和处理器。当通过NMOS传输晶体管提供输入信号时，所述输入信号被输入到第一NMOS晶体管的栅极，并且同时被输入到与所述第一NMOS晶体管执行互补操作的第一PMOS晶体管的栅极通过第二NMOS晶体管; 所述第一PMOS栅极通过第二PMOS晶体管连接到电源电位，并且所述第二NMOS晶体管的栅极连接到电源电位; 其中所述第二PMOS晶体管栅极的栅极由与所述第一NMOS晶体管的漏极和所述第一PMOS晶体管的漏极连接的信号控制。

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