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1. 发明授权

US4532589A Digital data processor with two operation units 失效
标题翻译：具有两个操作单元的数字数据处理器
公开(公告)号：US4532589A
公开(公告)日：1985-07-30
申请号：US446002
申请日：1982-12-01
申请人： Yoichi Shintani , Kenichi Wada , Tsuguo Shimizu , Akira Yamaoka
发明人： Yoichi Shintani , Kenichi Wada , Tsuguo Shimizu , Akira Yamaoka
IPC分类号： G06F9/38 , G06F9/00
CPC分类号： G06F9/3889 , G06F9/3824 , G06F9/3836 , G06F9/3885
摘要： In a data processing apparatus executing a plurality of instructions in a pipeline mode by dividing each of the instructions into a plurality of stages, its operation circuit includes a first execution (E) unit capable of execution of operations required by all of the plural instructions and a second E unit capable of execution of operations required by part of the plural instructions only. A queue of data including decoded information of the instructions required for execution of operation stages are stored in a circuit to be selectively supplied by first and second circuits to the first and second E units, respectively. The first and second circuits sequentially select succeeding data in synchronism with the end of operations in the first and second E units respectively. As a result, when a stage of a succeeding instruction requires the result of operation of a preceding instruction being executed, that stage of the succeeding instruction is executed after the second E unit completes the operation of the preceding instruction, even when the first E unit is executing an instruction further preceding the preceding instruction.
摘要翻译：在通过将每个指令分成多个级来执行流水线模式的多个指令的数据处理装置中，其操作电路包括能够执行所有多个指令所需的操作的第一执行（E）单元，以及能够执行多个指令的一部分所需的操作的第二E单元。包括执行操作阶段所需指令的解码信息的数据队列被存储在电路中，以分别由第一和第二电路选择性地提供给第一和第二E单元。第一和第二电路分别顺序地选择与第一和第二E单元中的操作结束同步的后续数据。结果，当后续指令的阶段需要执行前一指令的操作结果时，即使在第一E单元完成了第二E单元完成前一指令的操作之后，执行后续指令的该阶段正在执行进一步在前面的指令之前的指令。

2. 发明授权

US4541047A Pipelined data processing system 失效
标题翻译：流水线数据处理系统
公开(公告)号：US4541047A
公开(公告)日：1985-09-10
申请号：US490166
申请日：1983-04-29
申请人： Kenichi Wada , Yooichi Shintani , Tsuguo Shimizu , Akira Yamaoka
发明人： Kenichi Wada , Yooichi Shintani , Tsuguo Shimizu , Akira Yamaoka
IPC分类号： G06F9/38 , G06F9/48
CPC分类号： G06F9/3863
摘要： A data processing system for executing an instruction in a plurality of stages in a pipeline mode comprises a main operation unit for operating all instructions to be executed by the data processing unit, a first group of general purpose registers for storing the operation results of the main operation unit, a pre-operation unit for operating a portion of instructions which frequently appear and which can be operated with a small number of circuit components, a second group of general purpose registers for storing the operation results of the pre-operation unit, and control means for storing the operation result of the pre-operation unit into the second general purpose register at least one operation stage earlier than the storing of the operation result of the main operation unit into the first general purpose register and storing the contents of the second general purpose registers into the first general purpose registers when an interruption occurs.
摘要翻译：一种用于在流水线模式中执行多级的指令的数据处理系统包括用于操作由数据处理单元执行的所有指令的主操作单元，用于存储主程序的操作结果的第一组通用寄存器操作单元，用于操作经常出现并且可以用少量电路组件操作的指令的一部分的预操作单元，用于存储预操作单元的操作结果的第二组通用寄存器，以及控制装置，用于将预操作单元的操作结果存储在第二通用寄存器中，比将主操作单元的操作结果存储到第一通用寄存器中的至少一个操作阶段存储第二通用寄存器的内容当发生中断时，通用寄存器进入第一个通用寄存器。

3. 发明授权

US4739470A Data processing system 失效
标题翻译：数据处理系统
公开(公告)号：US4739470A
公开(公告)日：1988-04-19
申请号：US489349
申请日：1983-04-28
申请人： Kenichi Wada , Yooichi Shintani , Tsuguo Shimizu , Akira Yamaoka
发明人： Kenichi Wada , Yooichi Shintani , Tsuguo Shimizu , Akira Yamaoka
IPC分类号： G06F9/38
CPC分类号： G06F9/3889 , G06F9/383
摘要： A data processing system for executing an instruction in a plurality of stages in a pipeline mode comprises a main operation unit capable of executing all instructions to be executed in the data processing system, a pre-operation unit capable of executing instructions which occurs at a high frequency and can be executed with a small number of circuit components, general purpose registers for storing operation results of the instructions, and a control unit for controlling the writing of the operation results by the main operation unit and the pre-operation unit into the general purpose registers.
摘要翻译：一种用于在流水线模式中执行多级指令的数据处理系统，包括能够执行在数据处理系统中执行的所有指令的主操作单元，能够执行高位指令的预操作单元并且可以用少量的电路部件执行，用于存储指令的操作结果的通用寄存器，以及用于控制主操作单元和预操作单元的操作结果写入一般的控制单元目的寄存器。

4. 发明授权

US4608671A Buffer storage including a swapping circuit 失效
标题翻译：缓冲存储器包括交换电路
公开(公告)号：US4608671A
公开(公告)日：1986-08-26
申请号：US490518
申请日：1983-05-02
申请人： Tsuguo Shimizu , Kenichi Wada , Yooichi Shintani , Akira Yamaoka
发明人： Tsuguo Shimizu , Kenichi Wada , Yooichi Shintani , Akira Yamaoka
IPC分类号： G06F12/08 , G06F12/12 , G11C8/00
CPC分类号： G06F12/128
摘要： In a buffer storage device where swapping of data is employed, plural candidates for replacement of data in a buffer are determined in response to any access to the buffer storage, and, when the replacement is required, one of the candidates is selected so that processing time for replacement can be minimum.
摘要翻译：在采用交换数据的缓冲存储装置中，响应于对缓冲存储器的任何访问来确定用于替换缓冲器中的数据的多个候选，并且当需要更换时，选择候选中的一个，使得处理更换时间可以是最少的。

5. 发明授权

US4833619A Automatic logic design system 失效
标题翻译：自动逻辑设计系统
公开(公告)号：US4833619A
公开(公告)日：1989-05-23
申请号：US945946
申请日：1986-12-24
申请人： Tsuguo Shimizu , Yoshio Takamine
发明人： Tsuguo Shimizu , Yoshio Takamine
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： Herein disclosed is an automatic design system for automatically generating a data structure, which is only implicitly expressed by a logic specification description, by deriving, in case a logic system has data structures of similar constructions, one data structure from the structure description and transfer behavior description of the other data structure.
摘要翻译：这里公开了一种自动设计系统，用于通过在逻辑系统具有类似结构的数据结构的情况下导出来自结构描述和传输行为的一个数据结构来自动生成仅由逻辑规范描述隐含地表达的数据结构其他数据结构的描述。

6. 发明授权

US5504690A Automatic logic designing method and system 失效
标题翻译：自动逻辑设计方法和系统
公开(公告)号：US5504690A
公开(公告)日：1996-04-02
申请号：US108044
申请日：1993-08-16
申请人： Naohiro Kageyama , Toru Shonai , Rikako Suzuki , Takashi Okada , Kazuhiko Iijima , Hiroyuki Nakajima , Chihei Miura , Tsuguo Shimizu
发明人： Naohiro Kageyama , Toru Shonai , Rikako Suzuki , Takashi Okada , Kazuhiko Iijima , Hiroyuki Nakajima , Chihei Miura , Tsuguo Shimizu
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： An automatic logic designing method and system in which a control table describing a condition and a behavior corresponding to the condition which express the specification of a computer is inputted and processed in a processor so that a logic circuit having no redundancy which can be easily seen by the designer is designed at a high speed. The control table is converted into the logic circuit whose function is expressed by a detailed Boolean expression. In an instance, selector logics are allocated in consideration of the polarity of the logic. A redundancy detection process or a redundancy logic elimination process is executed for the redundancy logics designated by a redundancy indicate file. A signal name which can be easily understood by the logic designer is formed. An implementing system includes an input control table file, a functional structure converting section of a conditional equation and a behavioral structure, a regular logic expanding processing section, and a redundancy logic elimination processing section, so that the logic circuit formed is outputted to a Boolean expression file.
摘要翻译：一种自动逻辑设计方法和系统，其中描述与表达计算机的规格的条件相对应的条件和行为的控制表在处理器中被输入和处理，使得不具有冗余的逻辑电路可以容易地被设计师是高速设计的。控制表转换为逻辑电路，其功能由详细的布尔表达式表示。在一种情况下，考虑到逻辑的极性来分配选择器逻辑。对由冗余指示文件指定的冗余逻辑执行冗余检测处理或冗余逻辑消除处理。可以形成由逻辑设计者容易理解的信号名称。实现系统包括输入控制表文件，条件方程式的功能结构转换部分和行为结构，规则逻辑扩展处理部分和冗余逻辑消除处理部分，使得形成的逻辑电路输出到布尔值表达文件。

7. 发明授权

US4441152A Data processing system having ring-like connected multiprocessors relative to key storage 失效
标题翻译：数据处理系统相对于密钥存储具有环状连接的多处理器
公开(公告)号：US4441152A
公开(公告)日：1984-04-03
申请号：US233447
申请日：1981-02-11
申请人： Tsuguo Matsuura , Shunichi Torii , Tsuguo Shimizu
发明人： Tsuguo Matsuura , Shunichi Torii , Tsuguo Shimizu
IPC分类号： G06F12/00 , G06F9/46 , G06F12/14 , G06F15/16 , G06F15/177 , G06F13/00
CPC分类号： G06F9/52 , G06F12/1466 , G06F15/16
摘要： A multiprocessor system includes a plurality of central processing units (CPUs), which have a main storage in common, and a key storage for storing therein control information for storage protection of, reference to, and change in the main storage. Each CPU is provided with the key storage, the CPUs are connected by interface lines so as to form a ring-like combination, a CPU in which a key access request is generated, carries out the key processing for its own key storage and supplies the interface line with an address, data and others which are contained in the key access request, and another CPU receives the address, data and others to perform the key processing for its own key storage. A signal for determining the priority among key access requests simultaneously generated in a plurality of central processing units circulates through the CPUs via the interface lines, one of the CPUs having generated the key access requests catches the priority determining signal to make its own key access request valid, and prevents the circulation of the priority determining signal for a time till the key processing based upon the valid request has been completed.
摘要翻译：多处理器系统包括具有共同的主存储器的多个中央处理单元（CPU）和用于存储用于主存储器的存储保护，参考和变化的控制信息的密钥存储器。每个CPU都配有密钥存储器，CPU通过接口线连接，形成环状组合，生成密钥访问请求的CPU执行自身密钥存储的密钥处理，并提供接口线，其包含在密钥访问请求中的地址，数据等，另一个CPU接收地址，数据等，以对其自己的密钥存储进行密钥处理。用于确定在多个中央处理单元中同时产生的密钥访问请求中的优先级的信号经由接口线通过CPU循环，生成密钥访问请求的一个CPU捕获优先级确定信号以使其自己的密钥访问请求有效，并且防止优先级确定信号的循环一段时间，直到基于有效请求的密钥处理已经完成。

8. 发明授权

US5287289A Logic synthesis method 失效
标题翻译：逻辑合成方法
公开(公告)号：US5287289A
公开(公告)日：1994-02-15
申请号：US682608
申请日：1991-04-09
申请人： Naohiro Kageyama , Chihei Miura , Tsuguo Shimizu
发明人： Naohiro Kageyama , Chihei Miura , Tsuguo Shimizu
IPC分类号： G06F17/50 , G06F15/60
CPC分类号： G06F17/505
摘要： A logic circuit the functions of which have been expressed by a Boolean expression is subdivided, and then each of the subdivided logic circuit portions corresponds to each of the Boolean expressions. A plurality of logic circuits whose functions are equal to each other, whose delay times and gate numbers are different from each other, are synthesized every subdivided circuit portions, and a restriction condition formula is formed by employing the synthesized logic circuit under a restriction condition of the delay time designated by a user. While a linear programming is applied under the restriction condition and the number of gates is used as an objective function, such a logic circuit that the objective function takes a stationary value (a minimum value in the present invention) is selected with respect to each of subdivided portions, whereby an overall logic circuit is constructed.
摘要翻译：其功能由布尔表达式表示的逻辑电路被细分，然后每个细分逻辑电路部分对应于每个布尔表达式。每个分割电路部分合成多个逻辑电路，其功能彼此相等，其延迟时间和门数彼此不同，并且在限制条件下通过采用合成逻辑电路形成限制条件公式由用户指定的延迟时间。虽然在限制条件下应用线性规划，并且使用门数作为目标函数，但是对于每一个，选择目标函数取平均值（本发明中的最小值）的逻辑电路细分部分，从而构成整体逻辑电路。

9. 发明授权

US5274793A Automatic logic generation method for pipeline processor 失效
标题翻译：管线处理器的自动逻辑生成方法
公开(公告)号：US5274793A
公开(公告)日：1993-12-28
申请号：US489917
申请日：1990-03-07
申请人： Rikako Kuroda , Tsuguo Shimizu
发明人： Rikako Kuroda , Tsuguo Shimizu
IPC分类号： G06F9/38 , G06F17/50 , G06F15/20 , G06F15/60
CPC分类号： G06F17/5045
摘要： In automatically synthesizing pipeline control, a first circuit indicates the data holding status of a register in response to a circuit description. A second circuit designates the register to receive output of a preceding register in response to the first circuit. A third circuit designates the preceding register to receive input in response to the first circuit without a circuit that indicates the data holding status of the preceding register. Logic responds to: a first file storing circuit description and data propagation behavior; a second file storing register data holding condition and status; and a third file storing logic templates that indicate whether data can be stored by the register, data holding status of the registers, data holding cycles of the registers, and cancel condition of data holding by the registers. The logic templates are assigned for the registers stored in the first file based on the contents of the second file. The element number of the assigned template and mutual connections are defined based on the second file. Based on the second file, determination is made of those registers that may really develop resource conflict among the points where the data meet together and the points where the wait factors of the data transfers develop as well as only those registers which will be affected by the resource conflict. Logic is generated by assigning templates to the thus determined registers, making it possible to suppress the generation of redundant logic.
摘要翻译：在自动合成流水线控制中，第一电路响应于电路描述指示寄存器的数据保持状态。第二电路指定寄存器以响应于第一电路接收先前寄存器的输出。第三电路指定前一个寄存器以响应于第一电路接收输入，而没有指示前一个寄存器的数据保持状态的电路。逻辑响应：第一个文件存储电路描述和数据传播行为; 存储寄存器数据保持条件和状态的第二文件; 以及第三文件，其存储指示数据是否可由寄存器存储的数据，寄存器的数据保持状态，寄存器的数据保持周期以及由寄存器保存的数据的取消条件的逻辑模板。逻辑模板基于第二文件的内容分配给存储在第一文件中的寄存器。基于第二个文件定义分配的模板和相互连接的元素编号。根据第二个文件，确定这些寄存器可能真正发生数据在一起的点与数据传输的等待因素发生的点之间的资源冲突以及只会影响数据传输的那些寄存器资源冲突。通过将模板分配给如此确定的寄存器来产生逻辑，从而可以抑制冗余逻辑的产生。

10. 发明授权

US4385351A Multiprocessor system with apparatus for propagating cache buffer invalidation signals around a circular loop 失效
标题翻译：多处理器系统，具有围绕圆形循环传播缓存无效信号的装置
公开(公告)号：US4385351A
公开(公告)日：1983-05-24
申请号：US136492
申请日：1980-04-03
申请人： Tsuguo Matsuura , Shunichi Torii , Tsuguo Shimizu
发明人： Tsuguo Matsuura , Shunichi Torii , Tsuguo Shimizu
IPC分类号： G06F12/08 , G06F15/16 , G06F15/173 , G06F7/02 , G06F11/00 , G06F15/00
CPC分类号： G06F12/0813
摘要： This data processing system includes a main memory which is shared by a plurality of central processor units (CPUs) which are also coupled in cascade in a closed circular path. Each CPU has a cache buffer memory and two sets of transfer registers for receiving and transmitting cancel request signals which identify cache data which is no longer valid. Each CPU's receiving register subsystem includes circuitry for invalidating cache buffer data which has been updated or rewritten in main memory by another CPU in the loop. Each CPU's transmitting register subsystem includes circuitry for inhibiting the transmittal of a cancel request signal if the next CPU in the circle is the same one which originated the particular cache invalidation signal. Circuitry is also provided for propagating a cancel request signal around the loop in opposite directions simultaneously.
摘要翻译：该数据处理系统包括由多个中央处理器单元（CPU）共享的主存储器，这些中央处理器单元也是以闭合的圆形路径级联耦合的。每个CPU具有高速缓存存储器和两组传输寄存器，用于接收和发送识别不再有效的高速缓存数据的取消请求信号。每个CPU的接收寄存器子系统包括用于使循环中的另一个CPU更新或重写在主存储器中的缓存缓冲器数据无效的电路。每个CPU的发送寄存器子系统包括如果圆中的下一个CPU是相同的，发起特定的高速缓存无效信号，则禁止发送取消请求信号的电路。还提供电路用于在相反方向上同时传播环路周围的取消请求信号。

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