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1. 发明授权

US5475849A Memory control device with vector processors and a scalar processor 失效
标题翻译：具有矢量处理器和标量处理器的存储器控制装置
公开(公告)号：US5475849A
公开(公告)日：1995-12-12
申请号：US846147
申请日：1992-04-06
申请人： Toshimitsu Ando , Tsuguo Matsuura , Tadaaki Isobe
发明人： Toshimitsu Ando , Tsuguo Matsuura , Tadaaki Isobe
IPC分类号： G06F9/38 , G06F12/08 , G06F15/16 , G06F15/177 , G06F15/78 , G06F17/16
CPC分类号： G06F15/8069 , G06F12/0828 , G06F9/3834 , G06F9/3885
摘要： A memory control unit connected to a scalar processor having a buffer for storing a copy of block data of a main storage and a vector processor having a store requester for writing data into the main storage is disclosed. The memory control unit has a block valid memory having a one-bit valid bit for all blocks. The valid bit represents that the copy of the block data corresponding to said bit is in the buffer of the scalar processor. The memory control unit further has a block group valid table which has a block group bit for each block group. The block group bit represents whether any one of the block valid bits of the block belonging to the corresponding group is valid or not. When the vector processor stores the data into the main storage by the store requester, the memory control unit first searches the block group valid table to check whether the block group valid bit of the block group including the store address is valid or not. If it is valid, the memory control unit further searches the block valid memory to check whether the block valid bit of the block including the store address is valid or not. If it is valid, it invalidates the buffer of the scalar processor.
摘要翻译：公开了一种与具有用于存储主存储器的块数据的副本的缓冲器和具有用于将数据写入主存储器的存储请求器的向量处理器的标量处理器连接的存储器控制单元。存储器控制单元具有块有效存储器，其具有用于所有块的一位有效位。有效位表示对应于所述位的块数据的副本位于标量处理器的缓冲器中。存储器控制单元还具有块组有效表，其具有用于每个块组的块组比特。块组位表示属于相应组的块的任何一个块有效位是否有效。当向量处理器通过存储请求者将数据存储到主存储器中时，存储器控制单元首先搜索块组有效表以检查包括存储地址的块组的块组有效位是否有效。如果有效，则存储器控制单元进一步搜索块有效存储器来检查包括存储地址的块的块有效位是否有效。如果它有效，它会使标量处理器的缓冲区无效。

2. 发明授权

US4385351A Multiprocessor system with apparatus for propagating cache buffer invalidation signals around a circular loop 失效
标题翻译：多处理器系统，具有围绕圆形循环传播缓存无效信号的装置
公开(公告)号：US4385351A
公开(公告)日：1983-05-24
申请号：US136492
申请日：1980-04-03
申请人： Tsuguo Matsuura , Shunichi Torii , Tsuguo Shimizu
发明人： Tsuguo Matsuura , Shunichi Torii , Tsuguo Shimizu
IPC分类号： G06F12/08 , G06F15/16 , G06F15/173 , G06F7/02 , G06F11/00 , G06F15/00
CPC分类号： G06F12/0813
摘要： This data processing system includes a main memory which is shared by a plurality of central processor units (CPUs) which are also coupled in cascade in a closed circular path. Each CPU has a cache buffer memory and two sets of transfer registers for receiving and transmitting cancel request signals which identify cache data which is no longer valid. Each CPU's receiving register subsystem includes circuitry for invalidating cache buffer data which has been updated or rewritten in main memory by another CPU in the loop. Each CPU's transmitting register subsystem includes circuitry for inhibiting the transmittal of a cancel request signal if the next CPU in the circle is the same one which originated the particular cache invalidation signal. Circuitry is also provided for propagating a cancel request signal around the loop in opposite directions simultaneously.
摘要翻译：该数据处理系统包括由多个中央处理器单元（CPU）共享的主存储器，这些中央处理器单元也是以闭合的圆形路径级联耦合的。每个CPU具有高速缓存存储器和两组传输寄存器，用于接收和发送识别不再有效的高速缓存数据的取消请求信号。每个CPU的接收寄存器子系统包括用于使循环中的另一个CPU更新或重写在主存储器中的缓存缓冲器数据无效的电路。每个CPU的发送寄存器子系统包括如果圆中的下一个CPU是相同的，发起特定的高速缓存无效信号，则禁止发送取消请求信号的电路。还提供电路用于在相反方向上同时传播环路周围的取消请求信号。

3. 发明授权

US4214304A Multiprogrammed data processing system with improved interlock control 失效
标题翻译：多编程数据处理系统具有改进的互锁控制
公开(公告)号：US4214304A
公开(公告)日：1980-07-22
申请号：US954215
申请日：1978-10-24
申请人： Tsuguo Shimizu , Tsuguo Matsuura
发明人： Tsuguo Shimizu , Tsuguo Matsuura
IPC分类号： G06F12/00 , G06F9/46 , G06F9/48 , G06F15/16 , G06F15/177 , G06F13/00
CPC分类号： G06F9/4881 , G06F9/52
摘要： A multiprogrammed data processing system with reduced processing time for interlock instructions compares the first partial address contained in a request with a corresponding first partial address of an interlocked address in a first comparator when a main storage control unit receives the request from one of central processing units. The main storage control unit sends the request to a main memory in response to non-coincidence signal from the first comparator.In response to a coincidence signal from the first comparator, the main storage control unit compares a second partial address contained in the request with a corresponding second partial address of the interlocked address. The main storage control unit sends the request in response to a non-coincidence signal from the second comparator.
摘要翻译：一种具有缩短的互锁指令处理时间的多程序数据处理系统，当主存储控制单元从中央处理单元之一接收到请求时，将包含在请求中的第一部分地址与第一比较器中互锁地址的相应第一部分地址进行比较。主存储控制单元响应于来自第一比较器的不一致信号将请求发送到主存储器。响应于来自第一比较器的一致信号，主存储控制单元将包含在请求中的第二部分地址与互锁地址的对应的第二部分地址进行比较。主存储控制单元响应于来自第二比较器的不一致信号发送请求。

4. 发明授权

US06335903B2 Memory system 失效
标题翻译：内存系统
公开(公告)号：US06335903B2
公开(公告)日：2002-01-01
申请号：US09778785
申请日：2001-02-08
申请人： Tetsuhito Nakamura , Naonobu Sukegawa , Tsuguo Matsuura , Masanao Ito
发明人： Tetsuhito Nakamura , Naonobu Sukegawa , Tsuguo Matsuura , Masanao Ito
IPC分类号： G11C800
CPC分类号： G06F13/1631 , G06F12/0215
摘要： A memory system having a DRAM or synchronous DRAM as a memory unit. A memory controller which controls the memory unit in correspondence with a memory access request received from a memory access request generator, has a row address buffer for storing a row address extracted from an issued memory access request, avoiding registration of same row address into different positions, a pointer register for storing a pointer to a registration entry in the row address buffer holding the row address, correspondence detection circuit that detects whether or not row addresses of issued access requests correspond with each other by comparing stored pointers, and a memory unit control circuit which continuously issues column addresses of plural requests with row addresses corresponding with each other to the DRAM.
摘要翻译：具有DRAM或同步DRAM作为存储单元的存储器系统。存储器控制器，其与从存储器访问请求生成器接收的存储器访问请求相对应地控制存储器单元，具有用于存储从发布的存储器访问请求中提取的行地址的行地址缓冲器，避免将相同行地址注册到不同的位置用于存储指向存储行地址的行地址缓冲器中的注册条目的指针寄存器，对应检测电路，通过比较存储的指针来检测发出的访问请求的行地址是否相互对应;存储器单元控制电路，其连续地向DRAM发送具有彼此对应的行地址的多个请求的列地址。

5. 发明授权

US4725973A Vector processor 失效
标题翻译：矢量处理器
公开(公告)号：US4725973A
公开(公告)日：1988-02-16
申请号：US545160
申请日：1983-10-25
申请人： Tsuguo Matsuura , Toshihiko Odaka
发明人： Tsuguo Matsuura , Toshihiko Odaka
IPC分类号： G06F17/16 , G06F15/80 , G06F9/00 , G06F9/28
CPC分类号： G06F15/8092
摘要： A vector processor for executing vector instructions comprises a plurality of vector registers and a plurality of pipeline arithmetic logic units. The vector registers are constructed with a circuit which operates in a speed equal to 2n times as fast as the processing speed of the pipeline arithmetic logic units. Either the read or the write operation from or to the vector registers are carried out in the time obtained by a processing cycle of each of the pipeline arithmetic logic units multiplied by n/2.
摘要翻译：用于执行矢量指令的矢量处理器包括多个矢量寄存器和多个流水线运算逻辑单元。矢量寄存器由电路构成，该电路以等于流水线运算逻辑单元的处理速度的2n倍的速度工作。在通过每个流水线运算逻辑单元乘以n / 2的处理周期获得的时间内执行来自向量寄存器的向量寄存器的读操作或写操作。

6. 发明授权

US4441152A Data processing system having ring-like connected multiprocessors relative to key storage 失效
标题翻译：数据处理系统相对于密钥存储具有环状连接的多处理器
公开(公告)号：US4441152A
公开(公告)日：1984-04-03
申请号：US233447
申请日：1981-02-11
申请人： Tsuguo Matsuura , Shunichi Torii , Tsuguo Shimizu
发明人： Tsuguo Matsuura , Shunichi Torii , Tsuguo Shimizu
IPC分类号： G06F12/00 , G06F9/46 , G06F12/14 , G06F15/16 , G06F15/177 , G06F13/00
CPC分类号： G06F9/52 , G06F12/1466 , G06F15/16
摘要： A multiprocessor system includes a plurality of central processing units (CPUs), which have a main storage in common, and a key storage for storing therein control information for storage protection of, reference to, and change in the main storage. Each CPU is provided with the key storage, the CPUs are connected by interface lines so as to form a ring-like combination, a CPU in which a key access request is generated, carries out the key processing for its own key storage and supplies the interface line with an address, data and others which are contained in the key access request, and another CPU receives the address, data and others to perform the key processing for its own key storage. A signal for determining the priority among key access requests simultaneously generated in a plurality of central processing units circulates through the CPUs via the interface lines, one of the CPUs having generated the key access requests catches the priority determining signal to make its own key access request valid, and prevents the circulation of the priority determining signal for a time till the key processing based upon the valid request has been completed.
摘要翻译：多处理器系统包括具有共同的主存储器的多个中央处理单元（CPU）和用于存储用于主存储器的存储保护，参考和变化的控制信息的密钥存储器。每个CPU都配有密钥存储器，CPU通过接口线连接，形成环状组合，生成密钥访问请求的CPU执行自身密钥存储的密钥处理，并提供接口线，其包含在密钥访问请求中的地址，数据等，另一个CPU接收地址，数据等，以对其自己的密钥存储进行密钥处理。用于确定在多个中央处理单元中同时产生的密钥访问请求中的优先级的信号经由接口线通过CPU循环，生成密钥访问请求的一个CPU捕获优先级确定信号以使其自己的密钥访问请求有效，并且防止优先级确定信号的循环一段时间，直到基于有效请求的密钥处理已经完成。

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