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1. 发明授权

US5673229A Dynamic random access memory 失效
标题翻译：动态随机存取存储器
公开(公告)号：US5673229A
公开(公告)日：1997-09-30
申请号：US612759
申请日：1996-03-08
申请人： Junichi Okamura , Tohru Furuyama
发明人： Junichi Okamura , Tohru Furuyama
IPC分类号： G01R31/28 , G01R31/30 , G11C8/12 , G11C11/401 , G11C11/407 , G11C11/408 , G11C29/00 , G11C29/06 , G11C29/34 , G11C29/50 , H01L21/66 , H01L21/8242 , H01L27/10 , H01L27/108 , G11C7/00
CPC分类号： G11C11/4085 , G11C11/4087 , G11C29/50 , G11C8/12 , G11C11/401
摘要： A dynamic random access memory includes a dynamic memory cell having a transfer N-channel MOS transistor and a capacitive element for storing data which is connected to the transfer N-channel MOS transistor, a word line connected to a gate of the transfer N-channel transistor, of the dynamic memory cell, and a word line driving voltage source, to which power voltage is input for raising the input power voltage to generate a word line driving voltage. Also, the dynamic random access memory includes an address circuit for generating internal address signals in accordance with externally input address signals, a word line selecting circuit for decoding the internal address signals and outputting a word line selecting signal which varies within a range between the word line driving voltage and a ground potential, and a word line driving circuit for driving a corresponding word line in accordance with the word line selecting signal, the word line driving circuit being provided in correspondence with the word line and having a P-channel MOS transistor which has a source connected to a first node having the word line driving voltage, a drain connected to the word line and a gate to which the word line selecting signal is applied.
摘要翻译：动态随机存取存储器包括具有传输N沟道MOS晶体管的动态存储单元和用于存储连接到传输N沟道MOS晶体管的数据的电容元件，连接到传输N沟道的栅极的字线晶体管，以及字线驱动电压源，输入电源电压以提高输入电源电压以产生字线驱动电压。此外，动态随机存取存储器包括用于根据外部输入的地址信号产生内部地址信号的地址电路，用于对内部地址信号进行解码的字线选择电路，并输出在字之间的范围内变化的字线选择信号线驱动电压和接地电位，以及用于根据字线选择信号驱动相应字线的字线驱动电路，字线驱动电路与字线对应地设置，并具有P沟道MOS晶体管其源极连接到具有字线驱动电压的第一节点，连接到字线的漏极和施加了字线选择信号的栅极。

2. 发明授权

US5287312A Dynamic random access memory 失效
标题翻译：动态随机存取存储器
公开(公告)号：US5287312A
公开(公告)日：1994-02-15
申请号：US813492
申请日：1991-12-26
申请人： Junichi Okamura , Tohru Furuyama
发明人： Junichi Okamura , Tohru Furuyama
IPC分类号： G01R31/28 , G01R31/30 , G11C8/12 , G11C11/401 , G11C11/407 , G11C11/408 , G11C29/00 , G11C29/06 , G11C29/34 , G11C29/50 , H01L21/66 , H01L21/8242 , H01L27/10 , H01L27/108 , G11C7/00
CPC分类号： G11C11/4085 , G11C11/4087 , G11C29/50 , G11C8/12 , G11C11/401
摘要： A dynamic random access memory according to the present invention comprises a plurality of dynamic memory cells arranged in rows and columns, a word line connected to the memory cells on the same row, a bit line connected to the memory cells on the same column, a word line selecting circuit having a word line selecting function of selecting an arbitrary one of the rows in response to an internal address signal, a word line driving voltage source, a word line driving circuit having at least one driving MOS transistor connected between the word line driving voltage source and the word line, for driving the word line in response to an output signal of the word line selecting circuit, and a control circuit for, in response to a voltage stress test control signal input from outside, controlling the word line driving circuit so that the word line driving circuit drives word lines more than those selected in a normal operation mode upon receiving an external address signal.
摘要翻译：根据本发明的动态随机存取存储器包括以行和列排列的多个动态存储器单元，连接到同一行上的存储器单元的字线，连接到同一列上的存储器单元的位线，字线选择电路，具有响应于内部地址信号选择任意一行的字线选择功能，字线驱动电压源，字线驱动电路，具有连接在字线之间的至少一个驱动MOS晶体管驱动电压源和字线，用于响应于字线选择电路的输出信号驱动字线;以及控制电路，用于响应于从外部输入的电压应力测试控制信号来控制字线驱动使得字线驱动电路在接收到外部地址信号时比在正常操作模式中选择的字线更多地驱动字线。

3. 发明授权

US6101148A Dynamic random access memory 失效
标题翻译：动态随机存取存储器
公开(公告)号：US6101148A
公开(公告)日：2000-08-08
申请号：US907019
申请日：1997-08-06
申请人： Junichi Okamura , Tohru Furuyama
发明人： Junichi Okamura , Tohru Furuyama
IPC分类号： G01R31/28 , G01R31/30 , G11C8/12 , G11C11/401 , G11C11/407 , G11C11/408 , G11C29/00 , G11C29/06 , G11C29/34 , G11C29/50 , H01L21/66 , H01L21/8242 , H01L27/10 , H01L27/108 , G11C8/00
CPC分类号： G11C11/4085 , G11C11/4087 , G11C29/50 , G11C8/12 , G11C11/401
摘要： A dynamic random access memory includes a dynamic memory cell having a transfer N-channel MOS transistor and a capacitive element for storing data which is connected to the transfer N-channel MOS transistor, a word line connected to a gate of the transfer N-channel transistor, of the dynamic memory cell, and a word line driving voltage source, to which power voltage is input for raising the input power voltage to generate a word line driving voltage. Also, the dynamic random access memory includes an address circuit for generating internal address signals in accordance with externally input address signals, a word line selecting circuit for decoding the internal address signals and outputting a word line selecting signal which varies within a range between the word line driving voltage and a ground potential, and a word line driving circuit for driving a corresponding word line in accordance with the word line selecting signal, the word line driving circuit being provided in correspondence with the word line and having a P-channel MOS transistor which has a source connected to a first node having the word line driving voltage, a drain connected to the word line and a gate to which the word line selecting signal is applied.
摘要翻译：动态随机存取存储器包括具有传输N沟道MOS晶体管的动态存储单元和用于存储连接到传输N沟道MOS晶体管的数据的电容元件，连接到传输N沟道的栅极的字线晶体管，以及字线驱动电压源，输入电源电压以提高输入电源电压以产生字线驱动电压。此外，动态随机存取存储器包括用于根据外部输入的地址信号产生内部地址信号的地址电路，用于对内部地址信号进行解码的字线选择电路，并输出在字之间的范围内变化的字线选择信号线驱动电压和接地电位，以及用于根据字线选择信号驱动相应字线的字线驱动电路，字线驱动电路与字线对应地设置，并具有P沟道MOS晶体管其源极连接到具有字线驱动电压的第一节点，连接到字线的漏极和施加了字线选择信号的栅极。

4. 发明授权

US06317366B1 Dynamic random access memory 失效
标题翻译：动态随机存取存储器
公开(公告)号：US06317366B1
公开(公告)日：2001-11-13
申请号：US09630585
申请日：2000-08-01
申请人： Junichi Okamura , Tohru Furuyama
发明人： Junichi Okamura , Tohru Furuyama
IPC分类号： G11C700
CPC分类号： G11C11/4085 , G11C8/12 , G11C11/401 , G11C11/4087 , G11C29/50
摘要： A semiconductor memory device includes a memory cell having a transfer N-channel MOS transistor and a capacitive element for storing data which is connected to the transfer N-channel MOS transistor, a word line connected to a gate of the transfer N-channel transistor, of the memory cell, a charge pump circuit generating an internal power supply voltage which is boosted up from a power supply voltage, and outputting the internal power supply voltage, and a decoder circuit which receives address signals and has a P-channel MOS transistor for receiving the internal power supply voltage, the decoder circuit generating a word line selecting signal. Also, the semiconductor memory device includes a word line driving circuit for driving a corresponding word line in accordance with the word line selecting signal, the word line driving circuit being provided in correspondence with the word line and having a first MOS transistor and a second MOS transistor, the first MOS transistor having a first current path, a first end of the first current path being connected to a first node having the internal power supply voltage, a second end of the first current path being connected to the word line and a gate which is controlled in accordance with the word line selecting signal, the second MOS transistor having a second current path, a first end of the second current path being connected to the first MOS transistor, a second end of the second current path being connected to a predetermined potential lower than the internal power supply voltage, wherein the charge pump circuit outputs the internal power supply voltage for a first period in which at least the P-channel MOS transistor is in an ON state and a second period in which at least the first MOS transistor is in an ON state.
摘要翻译：半导体存储器件包括具有传输N沟道MOS晶体管的存储单元和用于存储连接到传输N沟道MOS晶体管的数据的电容元件，连接到传输N沟道晶体管的栅极的字线，产生从电源电压升高的内部电源电压并输出内部电源电压的电荷泵电路，以及接收地址信号并具有P沟道MOS晶体管的解码器电路，接收内部电源电压，解码器电路产生字线选择信号。此外，半导体存储器件包括用于根据字线选择信号驱动相应字线的字线驱动电路，字线驱动电路与字线对应地设置，并具有第一MOS晶体管和第二MOS 晶体管，第一MOS晶体管具有第一电流路径，第一电流路径的第一端连接到具有内部电源电压的第一节点，第一电流路径的第二端连接到字线和栅极其根据字线选择信号进行控制，第二MOS晶体管具有第二电流路径，第二电流路径的第一端连接到第一MOS晶体管，第二电流路径的第二端连接到预定电位低于内部电源电压，其中电荷泵电路在第一周期内输出内部电源电压 h，至少所述P沟道MOS晶体管处于导通状态，以及至少所述第一MOS晶体管处于导通状态的第二周期。

5. 发明授权

US06381186B1 Dynamic random access memory 失效
标题翻译：动态随机存取存储器
公开(公告)号：US06381186B1
公开(公告)日：2002-04-30
申请号：US09939586
申请日：2001-08-28
申请人： Junichi Okamura , Tohru Furuyama
发明人： Junichi Okamura , Tohru Furuyama
IPC分类号： G11C700
CPC分类号： G11C11/4085 , G11C8/12 , G11C11/401 , G11C11/4087 , G11C29/50
摘要： A dynamic random access memory includes a plurality of dynamic memory cells arranged in rows and columns, a word line connected to the memory cells on the same row, a bit line connected to the memory cells on the same column, a word line selecting circuit having a word line selecting function of selecting an arbitrary one of the rows in response to an internal address signal, a word line driving voltage source, a word line driving circuit having at least one driving MOS transistor connected between the word line driving voltage source and the word line, for driving the word line in response to an output signal of the word line selecting circuit, and a control circuit for, in response to a voltage stress test control signal input from outside, controlling the word line driving circuit so that the word line driving circuit drives word lines more than those selected in a normal operation mode upon receiving an external address signal.
摘要翻译：动态随机存取存储器包括以行和列排列的多个动态存储单元，连接到同一行上的存储单元的字线，连接到同一列上的存储单元的位线，字线选择电路，响应于内部地址信号，字线驱动电压源，字线驱动电路选择任意一行的字线选择功能，具有连接在字线驱动电压源和字线，用于响应于字线选择电路的输出信号驱动字线;以及控制电路，用于响应于从外部输入的电压应力测试控制信号，控制字线驱动电路，使得字线路驱动电路在接收到外部地址信号时，比在正常操作模式中选择的字线更多地驱动字线。

6. 发明授权

US06307796B1 Dynamic random access memory 失效
标题翻译：动态随机存取存储器
公开(公告)号：US06307796B1
公开(公告)日：2001-10-23
申请号：US09688083
申请日：2000-10-16
申请人： Junichi Okamura , Tohru Furuyama
发明人： Junichi Okamura , Tohru Furuyama
IPC分类号： G11C700
CPC分类号： G11C11/4085 , G11C8/12 , G11C11/401 , G11C11/4087 , G11C29/50
摘要： A dynamic random access memory includes a plurality of dynamic memory cells arranged in rows and columns, a word line connected to the memory cells on the same row, a bit line connected to the memory cells on the same column, a word line selecting circuit having a word line selecting function of selecting an arbitrary one of the rows in response to an internal address signal, a word line driving voltage source, a word line driving circuit having at least one driving MOS transistor connected between the word line driving voltage source and the word line, for driving the word line in response to an output signal of the word line selecting circuit, and a control circuit for, in response to a voltage stress test control signal input from outside, controlling the word line driving circuit so that the word line driving circuit drives word lines more than those selected in a normal operation mode upon receiving an external address signal.
摘要翻译：动态随机存取存储器包括以行和列排列的多个动态存储单元，连接到同一行上的存储单元的字线，连接到同一列上的存储单元的位线，字线选择电路，响应于内部地址信号，字线驱动电压源，字线驱动电路选择任意一行的字线选择功能，具有连接在字线驱动电压源和字线，用于响应于字线选择电路的输出信号驱动字线;以及控制电路，用于响应于从外部输入的电压应力测试控制信号，控制字线驱动电路，使得字线路驱动电路在接收到外部地址信号时，比在正常操作模式中选择的字线更多地驱动字线。

7. 发明授权

US06166975A Dynamic random access memory 失效
公开(公告)号：US06166975A
公开(公告)日：2000-12-26
申请号：US468314
申请日：1999-12-21
申请人： Junichi Okamura , Tohru Furuyama
发明人： Junichi Okamura , Tohru Furuyama
IPC分类号： G01R31/28 , G01R31/30 , G11C8/12 , G11C11/401 , G11C11/407 , G11C11/408 , G11C29/00 , G11C29/06 , G11C29/34 , G11C29/50 , H01L21/66 , H01L21/8242 , H01L27/10 , H01L27/108 , G11C7/00
CPC分类号： G11C11/4085 , G11C8/12 , G11C11/401 , G11C11/4087 , G11C29/50
摘要： A dynamic random access memory includes a dynamic memory cell having a transfer N-channel MOS transistor and a capacitive element for storing data which is connected to the transfer N-channel MOS transistor, a word line connected to a gate of the transfer N-channel transistor, of the dynamic memory cell, and a word line driving voltage source, to which power voltage is input for raising the input power voltage to generate a word line driving voltage. Also, the dynamic random access memory includes an address circuit for generating internal address signals in accordance with externally input address signals, a word line selecting circuit for decoding the internal address signals and outputting a word line selecting signal which varies within a range between the word line driving voltage and a ground potential, and a word line driving circuit for driving a corresponding word line in accordance with the word line selecting signal, the word line driving circuit being provided in correspondence with the word line and having a P-channel MOS transistor which has a source connected to a first node having the word line driving voltage, a drain connected to the word line and a gate to which the word line selecting signal is applied.

8. 发明授权

US07158441B2 Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：US07158441B2
公开(公告)日：2007-01-02
申请号：US11008957
申请日：2004-12-13
申请人： Junichi Okamura
发明人： Junichi Okamura
IPC分类号： G11C8/00 , G11C7/00
CPC分类号： H03K3/0231 , G06F1/10 , H03K3/03 , H03K3/0322
摘要： A semiconductor integrated circuit in which multiphase clock signals having the same phase difference are supplied from a multi-stage differential ring oscillator to other circuits, the multiphase clock signals can be prevented from being degraded in waveform due to electrostatic coupling between wirings of the multiphase clock signals and also wired in as small an area as possible. The semiconductor integrated circuit includes: multiple stages of amplifier circuits, connected in a ring form, for performing oscillating operation; a logic circuit for performing logic operation on the basis of predetermined ones of output signals of the multiple stages of amplifier circuits to output a plurality of clock signals having different phases from each other and duties not equal to 0.5; and a plurality of wirings for transmitting the plurality of clock signals output from the logic circuit.
摘要翻译：一种半导体集成电路，其中具有相同相位差的多相时钟信号从多级差分环形振荡器提供给其他电路，可以防止多相时钟信号由于多相时钟的布线之间的静电耦合而在波形中劣化信号，并尽可能小的面积。半导体集成电路包括：以环形连接的多级放大器电路，用于执行振荡操作; 逻辑电路，用于根据多级放大器电路的预定输出信号执行逻辑运算，以输出具有不同相位的多个时钟信号和不等于0.5的功能; 以及用于发送从逻辑电路输出的多个时钟信号的多个布线。

9. 发明授权

US5812478A Semiconductor memory having improved data bus arrangement 失效
标题翻译：具有改进的数据总线布置的半导体存储器
公开(公告)号：US5812478A
公开(公告)日：1998-09-22
申请号：US651418
申请日：1996-05-22
申请人： Junichi Okamura
发明人： Junichi Okamura
IPC分类号： G11C5/02 , G11C7/10 , G11C8/00 , G11C7/00
CPC分类号： G11C7/1006 , G11C5/025 , G11C7/10 , G11C7/1051 , G11C7/1078
摘要： A semiconductor memory including first, second, and third data busses, and first and second memory cell arrays arranged among the first, second, and third data busses. During operation of the semiconductor memory, a first, a second, and a third circuit selectively couple the first, second, and third data busses to a fourth and a fifth data bus. Additionally, there is provided first and second buffer circuits, which are respectively coupled to the fourth and the fifth data busses, and a sixth data bus, which is commonly coupled to the first and second buffer circuits. A control circuit is used to control the operation of the switch circuits. In preferred embodiments, the number of buffer circuits in the semiconductor memory is less than or equal to the number of memory cell arrays.
摘要翻译：包括第一，第二和第三数据总线的半导体存储器以及布置在第一，第二和第三数据总线之间的第一和第二存储单元阵列。在半导体存储器的操作期间，第一，第二和第三电路将第一，第二和第三数据总线选择性地耦合到第四和第五数据总线。另外，提供分别耦合到第四和第五数据总线的第一和第二缓冲电路，以及共同耦合到第一和第二缓冲电路的第六数据总线。控制电路用于控制开关电路的工作。在优选实施例中，半导体存储器中的缓冲电路的数量小于或等于存储单元阵列的数量。

10. 发明授权

US08423165B2 Digital/analogue conversion apparatus 有权
标题翻译：数字/模拟转换装置
公开(公告)号：US08423165B2
公开(公告)日：2013-04-16
申请号：US12285323
申请日：2008-10-01
申请人： Akira Yasuda , Junichi Okamura
发明人： Akira Yasuda , Junichi Okamura
IPC分类号： G06F17/00 , H04R3/00
CPC分类号： H04R3/08 , H03G3/20 , H03H15/00 , H03M3/344 , H03M3/414 , H03M3/504 , H03M7/3022 , H04R1/005 , H04R3/00 , H04R17/005
摘要： A digital/analog conversion apparatus for converting a digital signal into an analog signal. The digital/analog conversion apparatus can generate a high-quality analog signal, even when elements configuring the digital/analog conversion apparatus have variance, with high resolution and a small circuit size. The data conversion apparatus is provided with a first data converter for reducing the number of bits of an input signal, a second data converter for converting the format of the first output signal, and a third data converter for conversion into a code which corresponds to the history of the output from the second data converter.
摘要翻译：一种用于将数字信号转换成模拟信号的数字/模拟转换装置。即使构成数/模转换装置的元件具有高分辨率和小电路尺寸的差异，数/模转换装置也可以产生高质量的模拟信号。数据转换装置设置有用于减少输入信号的位数的第一数据转换器，用于转换第一输出信号的格式的第二数据转换器和用于转换成与第一输出信号对应的代码的第三数据转换器来自第二个数据转换器的输出历史。

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