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1. 发明申请

US20100230738A1 NOR FLASH MEMORY STRUCTURE WITH HIGHLY-DOPED DRAIN REGION AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：具有高排水区域的非闪存存储器结构及其制造方法
公开(公告)号：US20100230738A1
公开(公告)日：2010-09-16
申请号：US12400828
申请日：2009-03-10
申请人： Yider Wu , Yung-Chung Lee , Yi-Hsiu Chen
发明人： Yider Wu , Yung-Chung Lee , Yi-Hsiu Chen
IPC分类号： H01L29/788 , H01L21/336 , H01L29/00
CPC分类号： H01L27/11521 , H01L29/40114 , H01L29/42324
摘要： In a method of manufacturing a NOR flash memory structure, a highly-doped ion implantation process is performed to form a highly-doped drain region to overlap with a lightly-doped drain region. Therefore, the flash memory structure can have a reduced drain junction depth to improve the short channel effect while protecting the lightly-doped drain region from being punched through during an etching process for forming a contact hole.
摘要翻译：在制造NOR闪速存储器结构的方法中，执行高掺杂离子注入工艺以形成与轻掺杂漏极区重叠的高度掺杂的漏极区。因此，在用于形成接触孔的蚀刻工艺期间，闪速存储器结构可以具有减小的漏极结深度以改善短沟道效应，同时保护轻掺杂漏极区域不被穿孔。

2. 发明授权

US08012825B2 Method of manufacturing the double-implant nor flash memory structure 有权
标题翻译：制造双注入器或闪存结构的方法
公开(公告)号：US08012825B2
公开(公告)日：2011-09-06
申请号：US12350298
申请日：2009-01-08
申请人： Yider Wu , Yung-Chung Lee , Yi-Hsiu Chen
发明人： Yider Wu , Yung-Chung Lee , Yi-Hsiu Chen
IPC分类号： H01L21/336
CPC分类号： H01L27/11521 , H01L29/42324 , H01L29/66825 , H01L29/7881
摘要： In a method of manufacturing a double-implant NOR flash memory structure, a phosphorus ion implantation process is performed, so that a P-doped drain region is formed in a semiconductor substrate between two gate structures to overlap with a highly-doped drain (HDD) region and a lightly-doped drain (LDD) region. Therefore, the electric connection at a junction between the HDD region and the LDD region is enhanced and the carrier mobility in the memory is not lowered while the problems of short channel effect and punch-through of LDD region are solved.
摘要翻译：在制造双注入NOR NOR闪存结构的方法中，执行磷离子注入工艺，使得在两个栅极结构之间的半导体衬底中形成P掺杂漏极区，以与高掺杂漏极（HDD ）区域和轻掺杂漏极（LDD）区域。因此，解决了HDD区域和LDD区域之间的连接处的电连接，并且解决了存储器中的载流子迁移率，同时解决了LDD区域的短沟道效应和穿通问题。

3. 发明申请

US20100227460A1 METHOD OF MANUFACTURING NOR FLASH MEMORY 审中-公开
标题翻译：制造或闪存存储器的方法
公开(公告)号：US20100227460A1
公开(公告)日：2010-09-09
申请号：US12399377
申请日：2009-03-06
申请人： Yider Wu , Yung-Chung Lee , Yi-Hsiu Chen
发明人： Yider Wu , Yung-Chung Lee , Yi-Hsiu Chen
IPC分类号： H01L21/4763
CPC分类号： H01L27/11521 , H01L21/76224
摘要： In a method of manufacturing a NOR flash memory, when the memory device dimensions are further reduced, the forming of spacers at two lateral sides of the gate structures is omitted, and a space between two gate structures can be directly filled up with a dielectric spacer or a shallow trench isolation (STI) layer. Therefore, it is possible to avoid the problem of increased difficulty in manufacturing memory device caused by forming spacers in an extremely small space between the gate structures. The method also enables omission of the self-alignment step needed to form the salicide layer. Therefore, the difficulty in self-alignment due to the extremely small space between the gate structures can also be avoided.
摘要翻译：在制造NOR闪速存储器的方法中，当存储器件尺寸进一步减小时，省略在栅极结构的两个侧面处形成间隔物，并且两个栅极结构之间的间隔可以直接用介电间隔件或浅沟槽隔离（STI）层。因此，可以避免在栅极结构之间的极小空间中形成间隔物而造成存储器件制造难度增大的问题。该方法还能够省略形成硅化物层所需的自对准步骤。因此，也可以避免由于栅极结构之间的极小空间而导致的自对准难度。

4. 发明申请

US20100099262A1 METHOD OF MANUFACTURING NON-VOLATILE MEMORY CELL USING SELF-ALIGNED METAL SILICIDE 有权
标题翻译：使用自对准金属硅化物制造非挥发性记忆体的方法
公开(公告)号：US20100099262A1
公开(公告)日：2010-04-22
申请号：US12254022
申请日：2008-10-20
申请人： Yi-Hsiu Chen , Yung-Chung Lee , Yider Wu
发明人： Yi-Hsiu Chen , Yung-Chung Lee , Yider Wu
IPC分类号： H01L21/3105
CPC分类号： H01L21/28273 , H01L21/28282 , H01L27/11521 , H01L27/11568 , Y10S438/976
摘要： In a method of manufacturing a non-volatile memory cell, a self-aligned metal silicide is used in place of a conventional tungsten metal layer to form a polysilicon gate, and the self-aligned metal silicide is used as a connection layer on the polysilicon gate. By using the self-aligned metal silicide to form the polysilicon gate, the use of masks in the etching process may be saved to thereby enable simplified manufacturing process and accordingly, reduced manufacturing cost. Meanwhile, the problem of resistance shift caused by an oxidized tungsten metal layer can be avoided.
摘要翻译：在制造非易失性存储单元的方法中，使用自对准金属硅化物代替常规钨金属层以形成多晶硅栅极，并且自对准金属硅化物用作多晶硅上的连接层门。通过使用自对准的金属硅化物来形成多晶硅栅极，可以节省在蚀刻工艺中使用掩模，从而能够简化制造工艺，从而降低制造成本。同时，可以避免由氧化的钨金属层引起的电阻偏移的问题。

5. 发明授权

US08158519B2 Method of manufacturing non-volatile memory cell using self-aligned metal silicide 有权
标题翻译：使用自对准金属硅化物制造非易失性存储单元的方法
公开(公告)号：US08158519B2
公开(公告)日：2012-04-17
申请号：US12254022
申请日：2008-10-20
申请人： Yi-Hsiu Chen , Yung-Chung Lee , Yider Wu
发明人： Yi-Hsiu Chen , Yung-Chung Lee , Yider Wu
IPC分类号： H01L21/84 , H01L21/00 , H01L21/8238 , H01L21/44
CPC分类号： H01L21/28273 , H01L21/28282 , H01L27/11521 , H01L27/11568 , Y10S438/976
摘要： In a method of manufacturing a non-volatile memory cell, a self-aligned metal silicide is used in place of a conventional tungsten metal layer to form a polysilicon gate, and the self-aligned metal silicide is used as a connection layer on the polysilicon gate. By using the self-aligned metal silicide to form the polysilicon gate, the use of masks in the etching process may be saved to thereby enable simplified manufacturing process and accordingly, reduced manufacturing cost. Meanwhile, the problem of resistance shift caused by an oxidized tungsten metal layer can be avoided.
摘要翻译：在制造非易失性存储单元的方法中，使用自对准金属硅化物代替常规钨金属层以形成多晶硅栅极，并且自对准金属硅化物用作多晶硅上的连接层门。通过使用自对准的金属硅化物来形成多晶硅栅极，可以节省在蚀刻工艺中使用掩模，从而能够简化制造工艺，从而降低制造成本。同时，可以避免由氧化的钨金属层引起的电阻偏移的问题。

6. 发明申请

US20100171161A1 DOUBLE-IMPLANT NOR FLASH MEMORY STRUCTURE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：双重印记或闪存存储器结构及其制造方法
公开(公告)号：US20100171161A1
公开(公告)日：2010-07-08
申请号：US12350298
申请日：2009-01-08
申请人： Yider Wu , Yung-Chung Lee , Yi-Hsiu Chen
发明人： Yider Wu , Yung-Chung Lee , Yi-Hsiu Chen
IPC分类号： H01L29/788 , H01L29/00 , H01L21/336
CPC分类号： H01L27/11521 , H01L29/42324 , H01L29/66825 , H01L29/7881
摘要： In a method of manufacturing a double-implant NOR flash memory structure, a phosphorus ion implantation process is performed, so that a P-doped drain region is formed in a semiconductor substrate between two gate structures to overlap with a highly-doped drain (HDD) region and a lightly-doped drain (LDD) region. Therefore, the electric connection at a junction between the HDD region and the LDD region is enhanced and the carrier mobility in the memory is not lowered while the problems of short channel effect and punch-through of LDD region are solved.
摘要翻译：在制造双注入NOR NOR闪存结构的方法中，执行磷离子注入工艺，使得在两个栅极结构之间的半导体衬底中形成P掺杂漏极区，以与高掺杂漏极（HDD ）区域和轻掺杂漏极（LDD）区域。因此，解决了HDD区域和LDD区域之间的连接处的电连接，并且解决了存储器中的载流子迁移率，同时解决了LDD区域的短沟道效应和穿通问题。

7. 发明申请

US20090086548A1 FLASH MEMORY 审中-公开
标题翻译：闪存
公开(公告)号：US20090086548A1
公开(公告)日：2009-04-02
申请号：US11866018
申请日：2007-10-02
申请人： Yider Wu , Yung-Chung Lee
发明人： Yider Wu , Yung-Chung Lee
IPC分类号： G11C11/34
CPC分类号： G11C16/0475
摘要： A flash memory applied in NAND and/or NOR flash memory has a silicon-oxide-nitride-oxide-silicon cell structure, uses channel-hot-electron injection as a write mechanism thereof to have a localized trapping characteristic, and uses hot-hole injection as an erase mechanism thereof. The flash memory uses an oxide-nitride-oxide structure to replace a floating gate, and thereby solves the problem of an entire leakage caused by a local leakage of the floating gate. The flash memory may be miniaturized without the problem of data mutual interference, and may be easily integrated into the CMOS process to largely reduce the manufacturing cost thereof. Meanwhile, the flash memory also enables faster program time and erase time.
摘要翻译：应用于NAND和/或NOR闪速存储器的闪速存储器具有氧化硅 - 氮化物 - 氧化物 - 硅电池结构，其通道 - 热电子注入作为其写入机制具有局部捕获特性，并且使用热孔注射作为其擦除机制。闪速存储器使用氧化物 - 氮化物 - 氧化物结构来代替浮动栅极，从而解决了浮栅的局部泄漏引起的整个泄漏的问题。闪存可以小型化而没有数据相互干扰的问题，并且可以容易地集成到CMOS工艺中以大大降低其制造成本。同时，闪存还可以实现更快的编程时间和擦除时间。

8. 发明申请

US20110070707A1 METHOD OF MANUFACTURING NOR FLASH MEMORY 审中-公开
标题翻译：制造或闪存存储器的方法
公开(公告)号：US20110070707A1
公开(公告)日：2011-03-24
申请号：US12562936
申请日：2009-09-18
申请人： Yung-Chung Lee
发明人： Yung-Chung Lee
IPC分类号： H01L21/336
CPC分类号： H01L29/7881 , H01L21/26586 , H01L27/11521 , H01L29/66825
摘要： In a method of manufacturing a NOR flash memory, two times of tilt ion implantation process are conducted to form a tilt-implanted source region, so as to improve the distribution of the source region in a semiconductor substrate and reduce the probability of short channel effect (SCE) between the drain regions and the source region in the NOR flash memory.
摘要翻译：在制造NOR闪速存储器的方法中，进行两次倾斜离子注入工艺以形成倾斜注入源极区域，从而改善半导体衬底中的源极区域的分布并降低短沟道效应的概率（SCE）在NOR闪存中的漏极区域和源极区域之间。

9. 发明申请

US20050266623A1 Trench power MOSFET in silicon carbide and method of making the same 失效
标题翻译：沟槽功率MOSFET在碳化硅及其制作方法
公开(公告)号：US20050266623A1
公开(公告)日：2005-12-01
申请号：US10952848
申请日：2004-09-30
申请人： Chih-Wei Hsu , Yung-Chung Lee , Tsung-Ming Pan , Yen Chuo
发明人： Chih-Wei Hsu , Yung-Chung Lee , Tsung-Ming Pan , Yen Chuo
IPC分类号： H01L21/04 , H01L21/331 , H01L29/24 , H01L29/76 , H01L29/772 , H01L29/78
CPC分类号： H01L29/66068 , H01L29/1608 , H01L29/7827 , H01L29/7828
摘要： A structure of accumulated type trench MOSFET in silicon carbide(SiC) and forming method are disclosed. The MOSFET includes a trench gate having a gate oxide layer, a polysilicon layer, a source region, and a drain region. The source region contains a p+ heavily doped region, an n+ heavily doped region and a p-base region, and a source contact metal layer. The p+ heavily doped region the n+ heavily doped region and the p-base region are abutting each other. The former two are extended to the front surface of the silicon carbide substrate having the source contact metal layer formed over and the latter one is beneath them. Moreover, the p-base region is separated from the trench by an accumulation channel. The drain contact metal layer is formed on the rear surface of the silicon carbide substrate where the rear region of the silicon carbide is heavily doped than the front region thereof.
摘要翻译：公开了碳化硅（SiC）中的累积型沟槽MOSFET的结构和形成方法。 MOSFET包括具有栅极氧化层，多晶硅层，源极区和漏极区的沟槽栅极。源区包含p +重掺杂区，n +重掺杂区和p基区，以及源极接触金属层。 p +重掺杂区域，n +重掺杂区域和p基区域彼此邻接。前者两者延伸到碳化硅衬底的前表面，其具有形成在其上的源极接触金属层，而后者位于它们之下。此外，p基区通过积累通道与沟槽分离。漏极接触金属层形成在碳化硅衬底的后表面上，其中碳化硅的后部区域比其前部区域重掺杂。

10. 发明申请

US20070108504A1 NON-VOLATILE MEMORY AND MANUFACTURING METHOD AND OPERATING METHOD THEREOF 审中-公开
标题翻译：非易失性存储器及其制造方法及其工作方法
公开(公告)号：US20070108504A1
公开(公告)日：2007-05-17
申请号：US11308507
申请日：2006-03-31
申请人： Yung-Chung Lee , Hann-Ping Hwang , Chin-Chung Wang , Chih-Ming Chao , Saysamone Pittikoun , Chih-Chen Cho
发明人： Yung-Chung Lee , Hann-Ping Hwang , Chin-Chung Wang , Chih-Ming Chao , Saysamone Pittikoun , Chih-Chen Cho
IPC分类号： H01L29/788 , H01L29/76 , H01L21/336
CPC分类号： H01L29/792 , G11C16/0483 , H01L27/115 , H01L27/11568 , H01L29/42344
摘要： A non-volatile memory having a plurality of gate structures, a plurality of charge storage layers and two doped regions is provided. The gate structures are disposed on the substrate and connected in series. The charge storage layers are disposed between every two neighboring gate structures respectively. The gate structures and the charge storage layers form a memory cell column. The two doped regions are disposed in the substrate at both sides of the memory cell column.
摘要翻译：提供具有多个栅极结构，多个电荷存储层和两个掺杂区域的非易失性存储器。栅极结构设置在基板上并串联连接。电荷存储层分别设置在每两个相邻栅极结构之间。栅极结构和电荷存储层形成存储单元列。两个掺杂区域在存储单元列的两侧设置在基板中。

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