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1. 发明申请

US20050266623A1 Trench power MOSFET in silicon carbide and method of making the same 失效
标题翻译：沟槽功率MOSFET在碳化硅及其制作方法
公开(公告)号：US20050266623A1
公开(公告)日：2005-12-01
申请号：US10952848
申请日：2004-09-30
申请人： Chih-Wei Hsu , Yung-Chung Lee , Tsung-Ming Pan , Yen Chuo
发明人： Chih-Wei Hsu , Yung-Chung Lee , Tsung-Ming Pan , Yen Chuo
IPC分类号： H01L21/04 , H01L21/331 , H01L29/24 , H01L29/76 , H01L29/772 , H01L29/78
CPC分类号： H01L29/66068 , H01L29/1608 , H01L29/7827 , H01L29/7828
摘要： A structure of accumulated type trench MOSFET in silicon carbide(SiC) and forming method are disclosed. The MOSFET includes a trench gate having a gate oxide layer, a polysilicon layer, a source region, and a drain region. The source region contains a p+ heavily doped region, an n+ heavily doped region and a p-base region, and a source contact metal layer. The p+ heavily doped region the n+ heavily doped region and the p-base region are abutting each other. The former two are extended to the front surface of the silicon carbide substrate having the source contact metal layer formed over and the latter one is beneath them. Moreover, the p-base region is separated from the trench by an accumulation channel. The drain contact metal layer is formed on the rear surface of the silicon carbide substrate where the rear region of the silicon carbide is heavily doped than the front region thereof.
摘要翻译：公开了碳化硅（SiC）中的累积型沟槽MOSFET的结构和形成方法。 MOSFET包括具有栅极氧化层，多晶硅层，源极区和漏极区的沟槽栅极。源区包含p +重掺杂区，n +重掺杂区和p基区，以及源极接触金属层。 p +重掺杂区域，n +重掺杂区域和p基区域彼此邻接。前者两者延伸到碳化硅衬底的前表面，其具有形成在其上的源极接触金属层，而后者位于它们之下。此外，p基区通过积累通道与沟槽分离。漏极接触金属层形成在碳化硅衬底的后表面上，其中碳化硅的后部区域比其前部区域重掺杂。

2. 发明授权

US07033892B2 Trench power MOSFET in silicon carbide and method of making the same 失效
标题翻译：沟槽功率MOSFET在碳化硅及其制作方法
公开(公告)号：US07033892B2
公开(公告)日：2006-04-25
申请号：US10952848
申请日：2004-09-30
申请人： Chih-Wei Hsu , Yung-Chung Lee , Tsung-Ming Pan , Yen Chuo
发明人： Chih-Wei Hsu , Yung-Chung Lee , Tsung-Ming Pan , Yen Chuo
IPC分类号： H01L21/336
CPC分类号： H01L29/66068 , H01L29/1608 , H01L29/7827 , H01L29/7828
摘要： A structure of accumulated type trench MOSFET in silicon carbide(SiC) and forming method are disclosed. The MOSFET includes a trench gate having a gate oxide layer, a polysilicon layer, a source region, and a drain region. The source region contains a p+ heavily doped region, an n+ heavily doped region and a p-base region, and a source contact metal layer. The p+ heavily doped region the n+ heavily doped region and the p-base region are abutting each other. The former two are extended to the front surface of the silicon carbide substrate having the source contact metal layer formed over and the latter one is beneath them. Moreover, the p-base region is separated from the trench by an accumulation channel. The drain contact metal layer is formed on the rear surface of the silicon carbide substrate where the rear region of the silicon carbide is heavily doped than the front region thereof.
摘要翻译：公开了碳化硅（SiC）中的累积型沟槽MOSFET的结构和形成方法。 MOSFET包括具有栅极氧化层，多晶硅层，源极区和漏极区的沟槽栅极。源区包含p +重掺杂区，n +重掺杂区和p基区，以及源极接触金属层。 p +重掺杂区域，n +重掺杂区域和p基区域彼此邻接。前者两者延伸到碳化硅衬底的前表面，其具有形成在其上的源极接触金属层，而后者位于它们之下。此外，p基区通过积累通道与沟槽分离。漏极接触金属层形成在碳化硅衬底的后表面上，其中碳化硅的后部区域比其前部区域重掺杂。

3. 发明授权

US09142876B2 Planar antenna and handheld device 有权
标题翻译：平面天线和手持设备
公开(公告)号：US09142876B2
公开(公告)日：2015-09-22
申请号：US13041435
申请日：2011-03-07
申请人： Min-Che Chen , Chia-I Lin , Chih-Wei Hsu
发明人： Min-Che Chen , Chia-I Lin , Chih-Wei Hsu
IPC分类号： H01Q1/24 , H01Q1/52 , H01Q9/42 , H01Q21/28 , H01Q5/10
CPC分类号： H01Q1/243 , H01Q1/521 , H01Q5/10 , H01Q9/42 , H01Q21/28
摘要： A planar antenna and a handheld device are provided. The handheld device includes the planar antenna and a system ground plane. The planar antenna has a first feed point, a first ground point, a second feed point, and a second ground point. The first ground point and the second ground point are located between the first feed point and the second feed point. The system ground plane is electrically connected to the first feed point, the first ground point, the second feed point, and the second ground point. Thereby, the performance in radio signal transceiving is improved.
摘要翻译：提供平面天线和手持设备。手持设备包括平面天线和系统接地平面。平面天线具有第一馈电点，第一接地点，第二馈电点和第二接地点。第一接地点和第二接地点位于第一馈电点和第二馈电点之间。系统接地层电连接到第一馈电点，第一接地点，第二馈电点和第二接地点。从而提高了无线电信号收发的性能。

4. 发明授权

US08950074B2 Slider for a cutter 有权
标题翻译：滑块为切割机
公开(公告)号：US08950074B2
公开(公告)日：2015-02-10
申请号：US13586101
申请日：2012-08-15
申请人： Chih-Wei Hsu
发明人： Chih-Wei Hsu
IPC分类号： B26B3/06
CPC分类号： B26B5/002
摘要： A slider has an upper sliding element, a lower sliding element and a resilient tab. The upper sliding element has two first engaging segments disposed on an inner side of the upper sliding element. The lower sliding element has two second engaging segments disposed on an outer side facing the inner side of the upper sliding element and engaging the first engaging segments. A tab holding base is formed on and protrudes from the outer side of the lower sliding element and has a chamber defined in the tab holding base. The resilient tab is held in the chamber in the lower sliding element and has two legs. Accordingly, a slider having a structure in a closed condition is provided to prevent objects from entering into the chamber to interfere the operation of the resilient tab and the operation of the slider is smooth.
摘要翻译：滑块具有上滑动元件，下滑动元件和弹性凸片。上滑动元件具有设置在上滑动元件的内侧上的两个第一接合段。下滑动元件具有两个第二接合段，其设置在面向上滑动元件的内侧的外侧上并与第一接合段接合。在下滑动元件的外侧形成突出部保持基座，并且在该突出部保持基部具有限定的室。弹性片保持在下滑动元件的腔室中并具有两个腿。因此，具有处于闭合状态的结构的滑块被设置成防止物体进入室以干扰弹性片的操作，并且滑块的操作是平滑的。

5. 发明授权

US08656319B2 Optical proximity correction convergence control 有权
标题翻译：光学接近校正收敛控制
公开(公告)号：US08656319B2
公开(公告)日：2014-02-18
申请号：US13368919
申请日：2012-02-08
申请人： Cheng-Cheng Kuo , Ching-Che Tsai , Tzu-Chun Lo , Chih-Wei Hsu , Hua-Tai Lin , Tsai-Sheng Gau , Wen-Chun Huang , Chih-Shiang Chou , Hsin-Chang Lee , Kuei Shun Chen
发明人： Cheng-Cheng Kuo , Ching-Che Tsai , Tzu-Chun Lo , Chih-Wei Hsu , Hua-Tai Lin , Tsai-Sheng Gau , Wen-Chun Huang , Chih-Shiang Chou , Hsin-Chang Lee , Kuei Shun Chen
IPC分类号： G06F17/50
CPC分类号： G03F7/70441 , G03F7/70125
摘要： A method of optical proximity correction (OPC) convergence control that includes providing a lithography system having a photomask and an illuminator. The method further includes performing an exposure by the illuminator on the photomask. Also, the method includes optimizing an optical illuminator setting for the lithography system with a defined gate pitch in a first direction in a first template. Additionally, the method includes determining OPC correctors to converge the OPC results with a target edge placement error (EPE) to produce a first OPC setting for the first template. The first OPC setting targets a relatively small EPE and mask error enhancement factor (MEEF)of the defined gate pitch in the first template. In addition, the method includes checking the first OPC setting for a relatively small EPE, MEEF and DOM consistency with the first template of the defined gate pitch in a second, adjacent template.
摘要翻译：一种光学邻近校正（OPC）会聚控制的方法，包括提供具有光掩模和照明器的光刻系统。该方法还包括执行照明器在光掩模上的曝光。此外，该方法包括在第一模板中以第一方向限定的门间距优化光刻系统的光照射器设置。此外，该方法包括确定OPC校正器以使目标边缘放置误差（EPE）收敛OPC结果，以产生第一模板的第一OPC设置。第一个OPC设置针对第一个模板中定义的门间距的相对较小的EPE和掩模误差增强因子（MEEF）。此外，该方法包括在第二相邻模板中检查第一OPC设置以获得相对较小的EPE，MEEF和DOM与限定的门间距的第一模板的一致性。

6. 发明授权

US08239056B2 Advanced process control for new tapeout product 有权
标题翻译：新的流片产品的高级过程控制
公开(公告)号：US08239056B2
公开(公告)日：2012-08-07
申请号：US12616681
申请日：2009-11-11
申请人： Chih-Wei Hsu , Yu-Jen Cheng , Wen-Pin Liu , Shun-Ping Wang , Shin-Rung Lu , Jo Fei Wang , Jong-I Mou , Andy Tsen , Chun-Hsien Lin
发明人： Chih-Wei Hsu , Yu-Jen Cheng , Wen-Pin Liu , Shun-Ping Wang , Shin-Rung Lu , Jo Fei Wang , Jong-I Mou , Andy Tsen , Chun-Hsien Lin
IPC分类号： G06F19/00
CPC分类号： H01L21/67253 , G05B19/41865 , H01L21/67276 , Y02P90/20
摘要： The present disclosure provides a semiconductor manufacturing method. The method includes providing product data of a product, the product data including a sensitive product parameter; searching existing products according to the sensitive product parameter to identify a relevant product from the existing products; determining an initial value of a processing model parameter to the product using corresponding data of the relevant product; assigning the initial value of the processing model parameter to a processing model associated with a manufacturing process; thereafter, tuning a processing recipe using the processing model; and performing the manufacturing process to a semiconductor wafer using the processing recipe.
摘要翻译：本发明提供一种半导体制造方法。该方法包括提供产品的产品数据，产品数据包括敏感产品参数; 根据敏感产品参数搜索现有产品，从现有产品中识别相关产品; 使用相关产品的相应数据确定产品的处理模型参数的初始值; 将处理模型参数的初始值分配给与制造过程相关联的处理模型; 此后，使用该处理模型调整处理配方; 以及使用所述处理配方对所述半导体晶片进行制造处理。

7. 发明申请

US20110238197A1 DYNAMIC COMPENSATION IN ADVANCED PROCESS CONTROL 有权
标题翻译：高级过程控制中的动态补偿
公开(公告)号：US20110238197A1
公开(公告)日：2011-09-29
申请号：US12731348
申请日：2010-03-25
申请人： Chih-Wei Hsu , Jin-Ning Sung , Shin-Rung Lu , Jong-I Mou
发明人： Chih-Wei Hsu , Jin-Ning Sung , Shin-Rung Lu , Jong-I Mou
IPC分类号： G05B13/04 , G06F17/00
CPC分类号： G05B19/41875 , G05B2219/32017 , G05B2219/32189 , G05B2219/45031 , Y02P90/22
摘要： A method of semiconductor fabrication is provided. The method includes providing a model for a device parameter of a wafer as a function of first and second process parameters. The first and second process parameters correspond to different wafer characteristics, respectively. The method includes deriving target values of the first and second process parameters based on a specified target value of the device parameter. The method includes performing a first fabrication process in response to the target value of the first process parameter. The method includes measuring an actual value of the first process parameter thereafter. The method includes updating the model using the actual value of the first process parameter. The method includes deriving a revised target value of the second process parameter using the updated model. The method includes performing a second fabrication process in response to the revised target value of the second process parameter.
摘要翻译：提供了一种半导体制造方法。该方法包括提供晶片的器件参数的模型作为第一和第二工艺参数的函数。第一和第二工艺参数分别对应于不同的晶片特性。该方法包括基于设备参数的指定目标值导出第一和第二处理参数的目标值。该方法包括响应于第一过程参数的目标值执行第一制造过程。该方法包括此后测量第一处理参数的实际值。该方法包括使用第一过程参数的实际值更新模型。该方法包括使用更新的模型导出第二过程参数的修正目标值。该方法包括响应于修改的第二过程参数的目标值执行第二制造过程。

8. 发明申请

US20110193838A1 Driving Device, Driving Method, and Flat Panel Display 审中-公开
标题翻译：驱动装置，驾驶方法和平板显示器
公开(公告)号：US20110193838A1
公开(公告)日：2011-08-11
申请号：US12978423
申请日：2010-12-24
申请人： Chih-Wei Hsu
发明人： Chih-Wei Hsu
IPC分类号： G09G3/36 , G09G5/00
CPC分类号： G09G5/00 , G02B27/0093 , G09G3/342 , G09G2320/0261 , G09G2330/021 , G09G2340/04 , G09G2354/00
摘要： A driving device for a flat panel display includes a distance detection module for detecting a distance between a base point of a housing of the flat panel display and a user, to generate a detection result, and a control module for adjusting output effects of the flat panel display according to the detection result.
摘要翻译：用于平板显示器的驱动装置包括：距离检测模块，用于检测平板显示器的壳体的基点与用户之间的距离，以产生检测结果;以及控制模块，用于调节平板的输出效果面板显示根据检测结果。

9. 外观设计

USD604896S1 Circular lamp housing 有权
标题翻译：圆形灯罩
公开(公告)号：USD604896S1
公开(公告)日：2009-11-24
申请号：US29341974
申请日：2009-08-16
申请人： Pin-Chun Chen , Chih-Wei Hsu , Po-Hsun Yu , Chun-Chiang Huang
设计人： Pin-Chun Chen , Chih-Wei Hsu , Po-Hsun Yu , Chun-Chiang Huang

10. 发明申请

US20090283796A1 SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME 有权
标题翻译：半导体器件及其形成方法
公开(公告)号：US20090283796A1
公开(公告)日：2009-11-19
申请号：US12186966
申请日：2008-08-06
申请人： Florin Udrea , Chih-Wei Hsu
发明人： Florin Udrea , Chih-Wei Hsu
IPC分类号： H01L29/739
CPC分类号： H01L29/7397 , H01L29/0834 , H01L29/66348
摘要： A bipolar high voltage/power semiconductor device having a low voltage terminal and a high voltage terminal is disclosed. The bipolar high voltage/power semiconductor is a vertical insulated gate bipolar transistor with injection efficiency adjustment formed by highly doped n+ islands in a p+ anode layer. The device has a vertical drift region of a first conductivity type and having vertical first and second ends. In one example, a region of the second conductivity type is provided at the second end of the vertical drift region connected directly to the vertical high voltage terminal. In another example, a vertical buffer region of the first conductivity type is provided at the vertical second end of the vertical drift region and a vertical region of a second conductivity type is provided on the other side of the vertical buffer region and connected to the vertical high voltage terminal. A plurality of electrically floating lateral island regions are provided within the vertical drift region at or towards the vertical second end of the vertical drift region, the plurality of electrically floating lateral island regions being of the first conductivity type and being more highly doped than the drift region.
摘要翻译：公开了一种具有低电压端子和高电压端子的双极型高压/功率半导体器件。双极性高压/功率半导体是垂直绝缘栅双极晶体管，其具有由p +阳极层中的高掺杂n +岛形成的注入效率调节。该器件具有第一导电类型的垂直漂移区，并具有垂直的第一和第二端。在一个示例中，第二导电类型的区域设置在直接连接到垂直高压端子的垂直漂移区域的第二端。在另一示例中，第一导电类型的垂直缓冲区域设置在垂直漂移区域的垂直第二端，并且第二导电类型的垂直区域设置在垂直缓冲区域的另一侧并连接到垂直方向高压端子。多个电浮动横向岛区域设置在垂直漂移区域内或垂直于垂直漂移区域的垂直第二端处，多个电浮动横向岛区域是第一导电类型并且比漂移更高的掺杂地区。

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