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1. 发明授权

US07170796B1 Methods and systems for reducing the threshold voltage distribution following a memory cell erase 有权
标题翻译：减少存储单元擦除后阈值电压分布的方法和系统
公开(公告)号：US07170796B1
公开(公告)日：2007-01-30
申请号：US11193391
申请日：2005-08-01
申请人： Yi He , Gwyn Jones , Edward F. Runnion , Mark Randolph
发明人： Yi He , Gwyn Jones , Edward F. Runnion , Mark Randolph
IPC分类号： G11C11/34
CPC分类号： G11C16/14 , G11C16/3468 , G11C16/3472 , G11C16/3477
摘要： A method is provided for erasing a memory device including a number of memory cells, the memory cells including a substrate, a control gate, a charge storage element, a source region and a drain region. The method includes erasing a group of memory cells to lower a maximum threshold voltage of the group of memory cells below a first predetermined level. The group of memory cells is soft-programmed to raise a minimum threshold voltage of the group of memory cells above a second predetermined level. The group of memory cells is erased, following soft-programming, resulting in a reduced threshold voltage distribution associated with the group of memory cells.
摘要翻译：提供了一种用于擦除包括多个存储单元的存储器件的方法，所述存储器单元包括衬底，控制栅极，电荷存储元件，源极区域和漏极区域。该方法包括擦除一组存储器单元以将存储器单元组的最大阈值电压降低到低于第一预定水平。存储器单元组被软编程以将存储器单元组的最小阈值电压提高到高于第二预定水平。在软编程之后，存储单元组被擦除，导致与该组存储器单元相关联的阈值电压分布降低。

2. 发明授权

US06958272B2 Pocket implant for complementary bit disturb improvement and charging improvement of SONOS memory cell 有权
标题翻译：袖珍种植体用于SONOS存储器单元的互补位干扰改进和充电改进
公开(公告)号：US06958272B2
公开(公告)日：2005-10-25
申请号：US10755740
申请日：2004-01-12
申请人： Emmanuil H. Lingunis , Nga-Ching Alan Wong , Sameer Haddad , Mark W. Randolph , Mark T. Ramsbey , Ashot Melik-Martirosian , Edward F. Runnion , Yi He
发明人： Emmanuil H. Lingunis , Nga-Ching Alan Wong , Sameer Haddad , Mark W. Randolph , Mark T. Ramsbey , Ashot Melik-Martirosian , Edward F. Runnion , Yi He
IPC分类号： H01L21/265 , H01L21/336 , H01L21/8234 , H01L21/8246 , H01L27/115 , H01L29/10 , H01L29/792
CPC分类号： H01L27/11568 , H01L21/26586 , H01L27/115 , H01L29/1083 , H01L29/66833 , Y10S438/959
摘要： A technique for forming at least part of an array of a dual bit memory core is disclosed. Initially, a portion of a charge trapping dielectric layer is formed over a substrate and a resist is formed over the portion of the charge trapping dielectric layer. The resist is patterned and a pocket implant is performed at an angle to establish pocket implants within the substrate. A bitline implant is then performed to establish buried bitlines within the substrate. The patterned resist is then removed and the remainder of the charge trapping dielectric layer is formed. A wordline material is formed over the remainder of the charge trapping dielectric layer and patterned to form wordlines that overlie the bitlines. The pocket implants serve to mitigate, among other things, complementary bit disturb (CBD) that can result from semiconductor scaling. As such, semiconductor devices can be made smaller and increased packing densities can be achieved by virtue of the inventive concepts set forth herein.
摘要翻译：公开了一种用于形成双位存储器核心的阵列的至少一部分的技术。最初，电荷俘获电介质层的一部分形成在衬底上，并且在电荷俘获电介质层的部分上形成抗蚀剂。抗蚀剂被图案化，并且以一定角度执行凹穴注入以在衬底内建立口袋植入物。然后执行位线注入以在衬底内建立掩埋位线。然后去除图案化的抗蚀剂，并形成剩余的电荷捕获介电层。在剩余的电荷俘获电介质层中形成字线材料，并且被图案化以形成覆盖在位线上的字线。口袋种植体用于缓解由半导体尺度缩小引起的互补位干扰（CBD）。因此，可以使半导体器件更小，并且可以通过本文所阐述的发明概念来实现增加的封装密度。

3. 发明授权

US06906959B2 Method and system for erasing a nitride memory device 有权
标题翻译：擦除氮化物存储器件的方法和系统
公开(公告)号：US06906959B2
公开(公告)日：2005-06-14
申请号：US10306252
申请日：2002-11-27
申请人： Mark W. Randolph , Chi Chang , Yi He , Wei Zheng , Edward F. Runnion , Zhizheng Liu
发明人： Mark W. Randolph , Chi Chang , Yi He , Wei Zheng , Edward F. Runnion , Zhizheng Liu
IPC分类号： G11C16/04 , G11C16/14 , H01L21/336 , H01L29/792
CPC分类号： H01L29/66833 , G11C16/0475 , G11C16/14 , H01L29/7923
摘要： The present invention is a method and system for erasing a nitride memory device. In one embodiment of the present invention, an isolated P-well is formed in a semiconductor substrate. A plurality of N-type impurity concentrations are formed in the isolated P-well and a nitride memory cell is fabricated between two of the N-type impurity concentrations. Finally, an electrical contact is coupled to the isolated P-well.
摘要翻译：本发明是一种擦除氮化物存储器件的方法和系统。在本发明的一个实施例中，在半导体衬底中形成隔离的P阱。在分离的P阱中形成多个N型杂质浓度，并且在两种N型杂质浓度之间制造氮化物存储单元。最后，电接点耦合到隔离的P阱。

4. 发明授权

US06788583B2 Pre-charge method for reading a non-volatile memory cell 失效
标题翻译：用于读取非易失性存储单元的预充电方法
公开(公告)号：US06788583B2
公开(公告)日：2004-09-07
申请号：US10307749
申请日：2002-12-02
申请人： Yi He , Edward F. Runnion , Zhizheng Liu , Mark W. Randolph , Darlene G. Hamilton , Pauling Chen , Binh Le
发明人： Yi He , Edward F. Runnion , Zhizheng Liu , Mark W. Randolph , Darlene G. Hamilton , Pauling Chen , Binh Le
IPC分类号： G11C1606
CPC分类号： G11C7/12 , G11C16/0475 , G11C16/24
摘要： A method of detecting a charge stored on a charge storage region of a first dual bit dielectric memory cell within an array of dual bit dielectric memory cells comprises grounding a first bit line that forms a source junction with a channel region of the first memory cell. A high voltage is applied to a gate of the first memory cell and to a second bit line that is the next bit line to the right of the first bit line and separated from the first bit line only by the channel region. A third bit line, that is the next bit line to the right of the second bit line, is isolated such that its potential is effected only by its junctions with the a second channel region and a third channel region on opposing sides of the third bit line. A high voltage is applied to a pre-charge bit line that is to the right of the third bit line and current flow is detected at the second bit line to determine the programmed status of a source bit of the memory cell.
摘要翻译：一种检测存储在双位介质存储器单元阵列内的第一双位介质存储单元的电荷存储区域上的电荷的方法包括使与第一存储单元的沟道区形成源极结的第一位线接地。高电压被施加到第一存储单元的栅极和第二位线，第二位线是第一位线右侧的下一个位线，并且仅与通道区域从第一位线分离。位于第二位线右侧的下一个位线的第三位线是隔离的，使得其电位仅由其与第二通道区域的结和仅在第三位的相对侧上的第三通道区域线。将高电压施加到位于第三位线右侧的预充电位线，并且在第二位线处检测电流以确定存储器单元的源位的编程状态。

5. 发明授权

US06822909B1 Method of controlling program threshold voltage distribution of a dual cell memory device 有权
标题翻译：控制双电池存储器件的程序阈值电压分布的方法
公开(公告)号：US06822909B1
公开(公告)日：2004-11-23
申请号：US10422090
申请日：2003-04-24
申请人： Darlene G. Hamilton , Edward Hsia , Mark W. Randolph , Edward F. Runnion , Kulachet Tanpairoj
发明人： Darlene G. Hamilton , Edward Hsia , Mark W. Randolph , Edward F. Runnion , Kulachet Tanpairoj
IPC分类号： G11C1134
CPC分类号： G11C16/0475 , G11C11/5671 , G11C16/3454
摘要： A method of programming a dual cell memory device having a first charge storing cell and a second charge storing cell. The method can include applying an initial program pulse to the memory device; comparing the threshold voltage of the memory device with a verify threshold voltage; and if the threshold voltage of the memory device is less than the verify threshold voltage, applying a second program pulse to the memory device during which at least one condition of the second program pulse is modified from the initial program pulse.
摘要翻译：一种编程具有第一电荷存储单元和第二电荷存储单元的双单元存储器件的方法。该方法可以包括将初始编程脉冲施加到存储器件; 将存储器件的阈值电压与验证阈值电压进行比较; 并且如果所述存储器件的阈值电压小于所述验证阈值电压，则向所述存储器件施加第二编程脉冲，在所述存储器件期间，从所述初始编程脉冲修改所述第二编程脉冲的至少一个条件。

6. 发明授权

US06735114B1 Method of improving dynamic reference tracking for flash memory unit 有权
标题翻译：改进闪存单元动态参考跟踪的方法
公开(公告)号：US06735114B1
公开(公告)日：2004-05-11
申请号：US10357879
申请日：2003-02-04
申请人： Darlene G. Hamilton , Eric M. Ajimine , Ming-Huei Shieh , Lee Cleveland , Edward F. Runnion , Mark W. Randolph , Sameer S. Haddad
发明人： Darlene G. Hamilton , Eric M. Ajimine , Ming-Huei Shieh , Lee Cleveland , Edward F. Runnion , Mark W. Randolph , Sameer S. Haddad
IPC分类号： G11C1604
CPC分类号： G11C16/3418 , G11C16/0475 , G11C16/28
摘要： A method of programming a memory unit having a plurality of dual cell core memory devices and at least one dual cell dynamic reference device. The memory unit is subjected to an erase configuration operation such that each cell of the core memory devices is in a blank state and such that a threshold voltage of the at least one dynamic reference device is less than a charged program level threshold voltage. Thereafter, the at least one dynamic reference and the core memory devices are programmed using a page programming routine.
摘要翻译：一种编程具有多个双单元核心存储器件和至少一个双单元动态参考器件的存储器单元的方法。对存储器单元进行擦除配置操作，使得核心存储器件的每个单元处于空白状态，并且使得至少一个动态参考器件的阈值电压小于充电的程序电平阈值电压。此后，使用页面编程例程对至少一个动态参考和核心存储器设备进行编程。

7. 发明授权

US06944057B1 Method to obtain temperature independent program threshold voltage distribution using temperature dependent voltage reference 有权
标题翻译：使用温度依赖电压参考获得温度独立程序阈值电压分布的方法
公开(公告)号：US06944057B1
公开(公告)日：2005-09-13
申请号：US10431065
申请日：2003-05-06
申请人： Edward F. Runnion , Tien-Chun Yang , Binh Quang Le , Shigekazu Yamada , Darlene G. Hamilton , Ming-Huei Shieh , Pau-Ling Chen , Kazuhiro Kurihara
发明人： Edward F. Runnion , Tien-Chun Yang , Binh Quang Le , Shigekazu Yamada , Darlene G. Hamilton , Ming-Huei Shieh , Pau-Ling Chen , Kazuhiro Kurihara
IPC分类号： G11C16/06
CPC分类号： G11C16/3418 , G11C16/10
摘要： A method for controlling gate voltage in a memory device is described. The method includes providing a circuit that is adapted to be coupled with the memory device. The circuit is for generating a reference voltage. The method further includes utilizing the reference voltage provided by the circuit to apply a voltage at a gate of the memory device. The voltage has a value corresponding to a temperature of the memory device. The method also includes retaining a proportional relationship between the reference voltage and the temperature of the memory device, regardless of the change in the temperature of the memory device. The reference voltage provides a substantially constant programming time for the memory device regardless of the temperature of the memory device.
摘要翻译：描述了一种用于控制存储器件中的栅极电压的方法。该方法包括提供适于与存储器件耦合的电路。该电路用于产生参考电压。该方法还包括利用由电路提供的参考电压来在存储器件的栅极处施加电压。电压具有对应于存储器件的温度的值。该方法还包括保持参考电压与存储器件的温度之间的比例关系，而与存储器件的温度变化无关。参考电压为存储器件提供基本上恒定的编程时间，而与存储器件的温度无关。

8. 发明授权

US06775187B1 Method of programming a dual cell memory device 失效
标题翻译：编程双单元存储器件的方法
公开(公告)号：US06775187B1
公开(公告)日：2004-08-10
申请号：US10422489
申请日：2003-04-24
申请人： Darlene G. Hamilton , Edward F. Runnion , Edward Hsia , Kulachet Tanpairoj
发明人： Darlene G. Hamilton , Edward F. Runnion , Edward Hsia , Kulachet Tanpairoj
IPC分类号： G11C1604
CPC分类号： G11C16/10 , G11C16/0475
摘要： A method of programming a dual cell memory device having a first charge storing cell and second charge storing cell. The first charge storing cell can be pre-read to determine if the first charge storing cell stores an amount of charge to increase a threshold voltage of the memory device over a specified threshold voltage. If not, the second charge storing cell can be programmed with a standard program pulse. If so, the second charge storing cell can be programed with a modified program pulse.
摘要翻译：一种编程具有第一电荷存储单元和第二电荷存储单元的双单元存储器件的方法。可以预先读取第一电荷存储单元，以确定第一电荷存储单元是否存储一定量的电荷以增加存储器件的阈值电压超过指定的阈值电压。如果不是，则可以用标准编程脉冲编程第二电荷存储单元。如果是这样，则可以用修改的编程脉冲对第二电荷存储单元进行编程。

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