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1. 发明授权

US06579791B1 Method to form dual damascene structure 有权
标题翻译：形成双镶嵌结构的方法
公开(公告)号：US06579791B1
公开(公告)日：2003-06-17
申请号：US10074909
申请日：2002-02-12
申请人： Yeur Luen Tu , Chia-Shiung Tsai , Min-Hwa Chi
发明人： Yeur Luen Tu , Chia-Shiung Tsai , Min-Hwa Chi
IPC分类号： H01L214763
CPC分类号： H01L21/76808
摘要： A method of fabricating a dual damascene opening, comprising the following sequential steps. A structure having a stop layer formed over a second low-k material layer formed over a stop layer formed over a first low-k material layer is provided. These layers are etched to form a via opening exposing a portion of the structure. A photoresist layer is formed over the second low-k material layer stop layer and filling the via opening. The photoresist layer having a treated upper portion including a central trench pattern area that is wider than, and substantially centered over, the via opening. The treated upper portion of the photoresist layer preventing any effects to the underlying photoresist layer so that the underlying photoresist layer does not deleteriously interact with the first or second low-k material layer. Removing: (1) the central trench pattern area of the upper treated portion of the photoresist and the photoresist under the central trench pattern area a to form a trench pattern opening exposing a portion of the second low-k material layer stop layer under the removed central trench pattern area; and (2) the photoresist layer within the via opening while leaving a portion of the photoresist layer within the via opening overlying the portion of the structure that was exposed by the via opening. Transferring the trench pattern opening to the second low-k material layer stop layer and the second low-k material layer to form a trench substantially centered over the remaining via opening and completing the dual damascene opening.
摘要翻译：一种制造双镶嵌开口的方法，包括以下顺序步骤。提供一种具有形成在形成在第一低k材料层上形成的停止层上的第二低k材料层上的停止层的结构。蚀刻这些层以形成露出结构的一部分的通孔。在第二低k材料层停止层上形成光致抗蚀剂层并填充通孔。光致抗蚀剂层具有经处理的上部，其包括中心沟槽图案区域，该中心沟槽图案区域比通孔开口宽，并且基本上居中。光致抗蚀剂层的经处理的上部防止对下面的光致抗蚀剂层的任何影响，使得下面的光致抗蚀剂层不会与第一或第二低k材料层有害地相互作用。去除：（1）光致抗蚀剂的上部处理部分的中心沟槽图案区域和在中心沟槽图案区域a下方的光致抗蚀剂，以形成沟槽图形开口，暴露出被去除的第二低k材料层停止层的一部分中央沟槽图案区; 和（2）通孔开口内的光致抗蚀剂层，同时留下通孔开口内的一部分光致抗蚀剂层，覆盖由通孔开口暴露的结构部分。将沟槽图案开口转移到第二低k材料层停止层和第二低k材料层，以形成基本上位于剩余通孔开口上方的沟槽，并完成双镶嵌开口。

2. 发明授权

US06501120B1 Capacitor under bitline (CUB) memory cell structure employing air gap void isolation 有权
标题翻译：位线（CUB）下的电容器采用气隙空隙隔离的存储单元结构
公开(公告)号：US06501120B1
公开(公告)日：2002-12-31
申请号：US10053151
申请日：2002-01-15
申请人： Yeur-Luen Tu , Chia-Shiung Tsai , Min-Hwa Chi
发明人： Yeur-Luen Tu , Chia-Shiung Tsai , Min-Hwa Chi
IPC分类号： H01L218242
CPC分类号： H01L27/10888 , H01L21/7682 , H01L27/10811 , H01L28/84 , H01L28/90
摘要： Within both: (1) a method for forming a memory cell structure within a semiconductor integrated circuit microelectronic fabrication; and (2) the memory cell structure resulting from the method, there is provided a capacitor structure whose sidewall is separated from a bitline stud layer which is adjacent thereto and extends there above, by an air gap void. The air gap void provides for attenuated bitline to capacitor structure capacitive coupling, and thus enhanced performance of the memory cell structure.
摘要翻译：在两者中：（1）在半导体集成电路微电子制造中形成存储单元结构的方法; 和（2）由该方法得到的存储单元结构，提供了一个电容器结构，其电容器结构的侧壁与位于其周围的位线柱层分离，并在其上方延伸有气隙空隙。气隙空隙为衰减位线提供电容结构电容耦合，从而提高存储单元结构的性能。

3. 发明授权

US06271084B1 Method of fabricating a metal-insulator-metal (MIM), capacitor structure using a damascene process 有权
标题翻译：金属绝缘体金属（MIM）的制造方法，使用镶嵌工艺的电容器结构
公开(公告)号：US06271084B1
公开(公告)日：2001-08-07
申请号：US09759912
申请日：2001-01-16
申请人： Yeur-Luen Tu , Chia-Shiung Tsai , Min-Hwa Chi
发明人： Yeur-Luen Tu , Chia-Shiung Tsai , Min-Hwa Chi
IPC分类号： H01L218242
CPC分类号： H01L28/82 , H01L21/76838 , H01L21/76895 , H01L27/10855 , H01L27/10894 , H01L28/55 , H01L28/60
摘要： A process for forming a vertical, metal-insulator-metal (MIM), capacitor structure, for embedded DRAM devices, using a damascene procedure, has been developed. The process features forming a capacitor opening in a composite insulator layer comprised of a overlying insulator stop layer, a low k insulator layer, and an underlying insulator stop layer, with a lateral recess isotropically formed in the low k insulator layer. After formation of a bottom electrode structure in the capacitor opening, a high k insulator layer is deposited followed by the deposition of a conductive layer, completely filling the capacitor opening. A chemical mechanical polishing procedure is then used to remove portions of the conductive layer, and portions of the high k insulator layer, from the top surface of the overlying insulator stop layer, resulting in the formation of the vertical MIM capacitor structure, in the capacitor opening, comprised of: a top electrode structure, defined from the conductive layer; a capacitor dielectric layer, formed from the high k insulator layer; and a bottom electrode structure.
摘要翻译：已经开发了使用镶嵌程序形成用于嵌入式DRAM器件的垂直金属 - 绝缘体金属（MIM），电容器结构的工艺。该工艺的特征是在复合绝缘层中形成电容器开口，该复合绝缘层由上覆的绝缘体停止层，低k绝缘体层和下面的绝缘体阻挡层组成，在低k绝缘体层中各向同性地形成有横向凹槽。在电容器开口中形成底部电极结构之后，沉积高k绝缘体层，随后沉积导电层，完全填充电容器开口。然后使用化学机械抛光方法从上覆绝缘体停止层的顶表面去除导电层的部分和高k绝缘体层的部分，从而在电容器中形成垂直MIM电容器结构开口，包括：由导电层限定的顶部电极结构; 由高k绝缘体层形成的电容器电介质层; 和底部电极结构。

4. 发明授权

US06555442B1 Method of forming shallow trench isolation with rounded corner and divot-free by using disposable spacer 有权
标题翻译：通过使用一次性间隔件形成具有圆角和无凹槽的浅沟槽隔离的方法
公开(公告)号：US06555442B1
公开(公告)日：2003-04-29
申请号：US10042075
申请日：2002-01-08
申请人： Chih-Yang Pai , Chih-Hsing Yu , Yeur-Luen Tu , Chia-Shiung Tsai , Min-Hwa Chi
发明人： Chih-Yang Pai , Chih-Hsing Yu , Yeur-Luen Tu , Chia-Shiung Tsai , Min-Hwa Chi
IPC分类号： H01L2176
CPC分类号： H01L21/76235
摘要： A method of fabricating an STI, comprising the following steps. A silicon structure having a pad oxide layer formed thereover is provided. An undoped poly buffer layer is formed over the pad oxide layer. A hard mask layer is formed over the undoped poly buffer layer. The hard mask layer, the undoped poly buffer layer and the pad oxide layer are patterned to form an opening exposing a portion of the silicon structure within an active area. The opening having exposed side walls. Inorganic spacers are formed over the exposed side walls. Using the patterned hard mask layer and the spacers as hard masks, the silicon structure is etched to form an STI opening within the active area. The inorganic spacers are removed exposing the upper corners of the STI opening. Using an oxidation process, a liner oxide layer is formed within the STI opening, over the upper corners of the STI opening and at least the patterned undoped poly buffer layer exposed by the removal of the inorganic spacers. An STI oxide layer is formed over the patterned hard mask layer, filling the liner oxide layer lined STI opening. The STI oxide layer is planarized and the patterned hard mask, the patterned undoped poly buffer layer and the patterned pad oxide layer are removed to fabricate the STI having rounded corners and without substantial divots.
摘要翻译：一种制造STI的方法，包括以下步骤。提供了具有形成在其上的衬垫氧化物层的硅结构。在衬垫氧化物层上形成未掺杂的多晶缓冲层。在未掺杂的多缓冲层上形成硬掩模层。将硬掩模层，未掺杂的多晶缓冲层和焊盘氧化物层图案化以形成暴露有源区域内的硅结构的一部分的开口。开口具有暴露的侧壁。在暴露的侧壁上形成无机间隔物。使用图案化的硬掩模层和间隔物作为硬掩模，蚀刻硅结构以在有效区域内形成STI开口。去除暴露STI开口的上角的无机间隔物。使用氧化工艺，在STI开口内，在STI开口的上角上形成衬里氧化物层，并且至少通过去除无机间隔物露出图案化的未掺杂多缓冲层。在图案化的硬掩模层之上形成STI氧化物层，填充衬里氧化物层衬里的STI开口。将STI氧化物层平坦化，并且去除图案化的硬掩模，图案化的未掺杂多缓冲层和图案化的衬垫氧化物层，以制造具有圆角并且没有实质上的纹理的STI。

5. 发明授权

US06486529B2 Structure of merged vertical capacitor inside spiral conductor for RF and mixed-signal applications 有权
公开(公告)号：US06486529B2
公开(公告)日：2002-11-26
申请号：US10066512
申请日：2002-02-04
申请人： Min-Hwa Chi , Chia-Shiung Tsai , Yeur-Luen Tu
发明人： Min-Hwa Chi , Chia-Shiung Tsai , Yeur-Luen Tu
IPC分类号： H01L218242
CPC分类号： H01L23/5223 , H01L23/5227 , H01L27/08 , H01L28/10 , H01L28/91 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A new method and structure is provided for the simultaneous creation of inductive and capacitive components in a monolithic substrate. The invention provides a method and structure whereby a vertical spiral inductor is created on the surface of a substrate. Multiple capacitors are created inside the coils of the vertical spiral conductor. A base layer of dielectric is deposited over the surface of a semiconductor substrate, contact plugs are provided in the base layer of dielectric. Multiple layers of dielectric are deposited over the surface of the base layer, layers of coils are created in the multiple layers of dielectric. Vias are provided in the layer of dielectric to interconnect overlying coils of the spiral inductor. An etch stop layer is deposited on the surface of the upper layer of dielectric. At least two openings are etched in the multiple layers of dielectric, these at least two openings are surrounded by the coils of the spiral inductor and align with the contact plugs provided in the base layers. Spacers are formed on the sidewalls of the openings, the bottom electrode layer, dielectric layer and top electrode layer of the at least two capacitors are deposited over the spacers. The openings are filled with a conductive material, the surface of the conductive material is polished down to the surface of the etch stop.

6. 发明授权

US06486025B1 Methods for forming memory cell structures 有权
标题翻译：形成记忆细胞结构的方法
公开(公告)号：US06486025B1
公开(公告)日：2002-11-26
申请号：US10047265
申请日：2002-01-14
申请人： Yuan-Hung Liu , Yeur-Luen Tu , Chia-Shiung Tsai , Min-Hwa Chi , Chih-Hsing Yu
发明人： Yuan-Hung Liu , Yeur-Luen Tu , Chia-Shiung Tsai , Min-Hwa Chi , Chih-Hsing Yu
IPC分类号： H01L218242
CPC分类号： H01L27/10888 , H01L27/10811 , H01L28/84 , H01L28/91
摘要： Within a first of a pair of methods for forming a memory cell structure there is employed a sacrificial spacer layer formed adjacent a capacitor structure and subsequently stripped therefrom to provide an air gap void interposed between a bitline stud layer and the capacitor structure. Within a second of the pair of methods for forming a memory cell structure there is employed a topographically variable thickness masking layer as a self aligned mask layer for forming a patterned capacitor plate layer from a topographic blanket capacitor plate layer. The methods provide for readily forming the memory cell structure with enhanced performance.
摘要翻译：在用于形成存储单元结构的一对方法中的第一种中，采用邻近电容器结构形成并随后从其中剥离的牺牲隔离层，以提供位于位线支柱层和电容器结构之间的气隙空隙。在用于形成存储单元结构的一对方法的一秒钟内，采用形貌可变的厚度掩模层作为自对准掩模层，用于从地形覆盖电容器板层形成图案化电容器板层。该方法提供了容易地形成具有增强性能的存储单元结构。

7. 发明授权

US06362012B1 Structure of merged vertical capacitor inside spiral conductor for RF and mixed-signal applications 有权
标题翻译：用于RF和混合信号应用的螺旋导体内并联垂直电容器的结构
公开(公告)号：US06362012B1
公开(公告)日：2002-03-26
申请号：US09798651
申请日：2001-03-05
申请人： Min-Hwa Chi , Chia-Shiung Tsai , Yeur-Luen Tu
发明人： Min-Hwa Chi , Chia-Shiung Tsai , Yeur-Luen Tu
IPC分类号： H01L2100
CPC分类号： H01L23/5223 , H01L23/5227 , H01L27/08 , H01L28/10 , H01L28/91 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A new method and structure is provided for the simultaneous creation of inductive and capacitive components in a monolithic substrate. The invention provides a method and structure whereby a vertical spiral inductor is created on the surface of a substrate. Multiple capacitors are created inside the coils of the vertical spiral conductor. A base layer of dielectric is deposited over the surface of a semiconductor substrate, contact plugs are provided in the base layer of dielectric. Multiple layers of dielectric are deposited over the surface of the base layer, layers of coils are created in the multiple layers of dielectric. Vias are provided in the layer of dielectric to interconnect overlying coils of the spiral inductor. An etch stop layer is deposited on the surface of the upper layer of dielectric. At least two openings are etched in the multiple layers of dielectric, these at least two openings are surrounded by the coils of the spiral inductor and align with the contact plugs provided in the base layers. Spacers are formed on the sidewalls of the openings, the bottom electrode layer, dielectric layer and top electrode layer of the at least two capacitors are deposited over the spacers. The openings are filled with a conductive material, the surface of the conductive material is polished down to the surface of the etch stop.
摘要翻译：提供了一种新的方法和结构，用于在单片基板中同时产生感应和电容部件。本发明提供一种方法和结构，由此在衬底的表面上产生垂直螺旋电感器。在垂直螺旋导体的线圈内部产生多个电容器。电介质的基底层沉积在半导体衬底的表面上，接触插塞设置在电介质的基底层中。在基层的表面上沉积多层电介质，在多层电介质中形成线圈层。在电介质层中提供通孔以互连螺旋电感器的上覆线圈。蚀刻停止层沉积在电介质上层的表面上。在多层电介质中蚀刻至少两个开口，这些至少两个开口被螺旋电感器的线圈包围，并与设置在基层中的接触插塞对准。隔板形成在开口的侧壁上，至少两个电容器的底部电极层，电介质层和顶部电极层沉积在间隔物上。开口填充有导电材料，导电材料的表面被抛光到蚀刻停止件的表面。

8. 发明授权

US09099389B2 Method and apparatus for reducing stripe patterns 有权
标题翻译：减少条纹图案的方法和装置
公开(公告)号：US09099389B2
公开(公告)日：2015-08-04
申请号：US13371303
申请日：2012-02-10
申请人： Chung Chien Wang , Yeur-Luen Tu , Cheng-Ta Wu , Chia-Shiung Tsai
发明人： Chung Chien Wang , Yeur-Luen Tu , Cheng-Ta Wu , Chia-Shiung Tsai
IPC分类号： H01L21/268 , H01L27/146
CPC分类号： H01L21/268 , G01B11/14 , H01L27/1464 , H01L27/14643 , H01L27/14689
摘要： A method for reducing stripe patterns comprising receiving scattered light signals from a backside surface of a laser annealed backside illuminated image sensor wafer, generating a backside surface image based upon the scattered light signals, determining a distance between an edge of a sensor array of the laser anneal backside illuminated image sensor wafer and an adjacent boundary of a laser beam and re-calibrating the laser beam if the distance is less than a predetermined value.
摘要翻译：一种用于减少条纹图案的方法，包括从激光退火背面照射图像传感器晶片的背面接收散射光信号，基于散射光信号产生背面图像，确定激光器的传感器阵列的边缘之间的距离退火背面照射的图像传感器晶片和激光束的相邻边界，并且如果距离小于预定值则重新校准激光束。

9. 发明授权

US09059057B2 Image sensor having compressive layers 有权
标题翻译：具有压缩层的图像传感器
公开(公告)号：US09059057B2
公开(公告)日：2015-06-16
申请号：US13492258
申请日：2012-06-08
申请人： Chun-Han Tsao , Chih-Yu Lai , Chih-Hui Huang , Cheng-Ta Wu , Yeur-Luen Tu , Ching-Chun Wang , Shyh-Fann Ting , Chia-Shiung Tsai
发明人： Chun-Han Tsao , Chih-Yu Lai , Chih-Hui Huang , Cheng-Ta Wu , Yeur-Luen Tu , Ching-Chun Wang , Shyh-Fann Ting , Chia-Shiung Tsai
IPC分类号： H01L31/102 , H01L21/00 , H01L27/146 , H01L27/148
CPC分类号： H01L31/02164 , H01L27/14623 , H01L27/14632 , H01L27/1464 , H01L27/14643 , H01L27/14687 , H01L27/148 , H01L51/4273
摘要： An image sensor device including a semiconductor substrate that includes an array region and a black level correction region. The array region contains a plurality of radiation-sensitive pixels. The black level correction region contains one or more reference pixels. The substrate has a front side and a back side. The image sensor device includes a first compressively-stressed layer formed on the back side of the substrate. The first compressively-stressed layer contains silicon oxide, and is negatively charged. The second compressively-stressed layer contains silicon nitride, and is negatively charged. A metal shield is formed over at least a portion of the black level correction region. The image sensor device includes a third compressively-stressed layer formed on the metal shield and the second compressively-stressed layer. The third compressively-stressed layer contains silicon oxide. A sidewall of the metal shield is protected by the third compressively-stressed layer.
摘要翻译：一种包括具有阵列区域和黑色电平校正区域的半导体衬底的图像传感器装置。阵列区域包含多个辐射敏感像素。黑色电平校正区域包含一个或多个参考像素。基板具有前侧和后侧。图像传感器装置包括形成在基板的背面上的第一压缩应力层。第一压应力层含有氧化硅，带负电荷。第二压应力层含有氮化硅，带负电荷。在黑色电平校正区域的至少一部分上形成金属屏蔽。图像传感器装置包括形成在金属屏蔽和第二压缩应力层上的第三压缩应力层。第三压缩应力层含有氧化硅。金属屏蔽层的侧壁由第三压应力层保护。

10. 发明授权

US08802457B2 Backside surface treatment of semiconductor chips 有权
标题翻译：半导体芯片的背面表面处理
公开(公告)号：US08802457B2
公开(公告)日：2014-08-12
申请号：US13205179
申请日：2011-08-08
申请人： Chih-Yu Lai , Cheng-Ta Wu , Kai-Chun Hsu , Yeur-Luen Tu , Ching-Chun Wang , Chia-Shiung Tsai
发明人： Chih-Yu Lai , Cheng-Ta Wu , Kai-Chun Hsu , Yeur-Luen Tu , Ching-Chun Wang , Chia-Shiung Tsai
IPC分类号： H01L21/00 , H01L21/46 , H01L21/322
CPC分类号： H01L27/14687 , H01L27/1464
摘要： A method includes performing a grinding to a backside of a semiconductor substrate, wherein a remaining portion of the semiconductor substrate has a back surface. A treatment is then performed on the back surface using a method selected from the group consisting essentially of a dry treatment and a plasma treatment. Process gases that are used in the treatment include oxygen (O2). The plasma treatment is performed without vertical bias in a direction perpendicular to the back surface.
摘要翻译：一种方法包括对半导体衬底的背面进行研磨，其中半导体衬底的剩余部分具有背面。然后使用基本上由干法处理和等离子体处理组成的组中的方法在背面进行处理。用于处理的工艺气体包括氧（O 2）。在垂直于后表面的方向上进行等离子体处理而没有垂直偏压。

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