专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06306721B1 Method of forming salicided poly to metal capacitor 有权
标题翻译：形成水银多金属电容器的方法
公开(公告)号：US06306721B1
公开(公告)日：2001-10-23
申请号：US09808926
申请日：2001-03-16
申请人： Yeow Meng Teo , Madhusudan Mukhopadhyay , Heng Jee Kiat
发明人： Yeow Meng Teo , Madhusudan Mukhopadhyay , Heng Jee Kiat
IPC分类号： H01L2120
CPC分类号： H01L28/40 , H01L28/60
摘要： A new method is provided for the creation of a salicided polysilicon capacitor. A salicided layer of polysilicon is created as the lower plate of a salicided polysilicon capacitor over the surface of a field isolation region. A layer of silicon nitride is deposited over the field oxide isolation region including the surface of the salicided polysilicon layer. A layer of TEOS is deposited over the surface of the layer of silicon nitride, a layer if titanium nitride is deposited over the surface of the layer of TEOS. The layer of TiN is etched after which the layer of TEOS is etched. The etch of the layer of TEOS is an overetch whereby TEOS is symmetrically removed from underneath the etched layer of TiN, leaving remnants of TEOS in place underneath the etched layer of TiN while at the same time creating air gaps underneath the etched layer of TiN. A layer of silane based oxide is deposited over the surface of the field oxide isolation region including the surface of the etched layer of TiN, thus enclosing the air gaps that have been created underneath the etched layer of TiN. The latter layer of silane based oxide is patterned and etched, forming the upper plate of the salicided polysilicon capacitor. The TEOS remnants remaining in place underneath the etched layer of TiN is part of the dielectric layer of the capacitor.
摘要翻译：提供了一种新的方法来创建一个多晶硅多晶硅电容器。在场隔离区域的表面上形成多晶硅的含水层作为水化多晶硅电容器的下板。在包括水化多晶硅层的表面的场氧化物隔离区域上沉积氮化硅层。一层TEOS沉积在氮化硅层的表面上，如果氮化钛沉积在TEOS层的表面上，则是层。蚀刻TiN层，之后蚀刻TEOS层。 TEOS层的蚀刻是过蚀刻，其中TEOS从TiN的蚀刻层下方对称地移除，在TEN的蚀刻层下方留下TEOS的残留物，同时在TiN的蚀刻层下面形成气隙。在包括TiN蚀刻层的表面的场氧化物隔离区的表面上沉积硅烷基氧化物层，从而包围在TiN的蚀刻层下方产生的气隙。对硅烷基氧化物的后一层进行图案化和蚀刻，形成多晶硅电容器的上层板。保留在TiN蚀刻层下方的TEOS残留物是电容器介质层的一部分。

2. 发明授权

US06368900B1 Method of fabricating an antifuse element 有权
标题翻译：制造反熔丝元件的方法
公开(公告)号：US06368900B1
公开(公告)日：2002-04-09
申请号：US09501374
申请日：2000-02-11
申请人： John Prasao Kenkaraseril , Madhusudan Mukhopadhyay , Qi Dong Xiang , Yeow-Meng Teo
发明人： John Prasao Kenkaraseril , Madhusudan Mukhopadhyay , Qi Dong Xiang , Yeow-Meng Teo
IPC分类号： H01L2182
CPC分类号： H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： A process for forming an amorphous silicon, antifuse element, on an underlying, raised tungsten plug structure, has been developed. The process features the recessing of the insulator layer, in which the tungsten plug structure resides, resulting in a raised portion of a tungsten plug structure. Conductive spacers are then formed on the exposed sides of the raised portion of the tungsten plug structure, resulting in smooth edges, at the perophery of the raised tungsten plug structure. An amorphous silicon layer is then deposited and defined to create the amorphous silicon, antifuse element, on the underlying raised tungsten plug structure, smoothed via the addition of the conductive, sidewall spacers. The use of the underlying, smooth, raised tungsten plug structure, alleviates excessive current crowding, presnet at the edges of the raised tungsten plug structure, during a high voltage pulsing procedure, performed to the overlying antifuse element.
摘要翻译：已经开发了用于在下面的凸起的钨插塞结构上形成非晶硅，反熔丝元件的工艺。该方法的特征在于钨插塞结构所在的绝缘体层的凹陷，导致钨插塞结构的凸起部分。然后，在钨插头结构的凸起部分的暴露侧上形成导电间隔物，从而在凸起的钨插头结构的多孔处形成光滑的边缘。然后沉积和限定非晶硅层以在下面的隆起的钨插塞结构上产生非晶硅，反熔丝元件，通过添加导电侧壁间隔物而平滑化。在高电压脉冲过程中，使用底层的，平滑的，提升的钨插头结构，减轻过度的电流拥挤，在升高的钨插塞结构的边缘处，对上覆的反熔丝元件执行。

3. 发明授权

US06362102B1 Method of forming top metal contact to antifuse 有权
标题翻译：形成顶部金属接触到反熔丝的方法
公开(公告)号：US06362102B1
公开(公告)日：2002-03-26
申请号：US09472415
申请日：1999-12-27
申请人： Say Gut Piew , Madhusudan Mukhopadhyay , Yeow Meng Teo
发明人： Say Gut Piew , Madhusudan Mukhopadhyay , Yeow Meng Teo
IPC分类号： H01L21302
CPC分类号： H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： A method for fabricating a self-aligned antifuse cell is described. An antifuse is provided overlying a metal plug in an insulating layer on a semiconductor substrate. A dielectric layer is deposited overlying the antifuse. The dielectric layer is etched to form dielectric spacers on the sidewalls of the antifuse. A top metal layer is deposited overlying the antifuse and dielectric spacers and patterned to complete the antifuse cell in an integrated circuit device.
摘要翻译：描述了制造自对准反熔丝电池的方法。在半导体衬底上的绝缘层中的金属插头上设置反熔丝。沉积在反熔丝上的电介质层。蚀刻电介质层以在反熔丝的侧壁上形成电介质间隔物。顶部金属层沉积在反熔丝和电介质间隔物上，并被图案化以在集成电路器件中完成反熔丝电池。

4. 发明授权

US06248006B1 CMP uniformity 失效
标题翻译： CMP均匀性
公开(公告)号：US06248006B1
公开(公告)日：2001-06-19
申请号：US09490155
申请日：2000-01-24
申请人： Madhusudan Mukhopadhyay , Subramanian Balakumar , Chivukula Subrahmanyam , Yelehanka Ramachandramurthy Pradeep
发明人： Madhusudan Mukhopadhyay , Subramanian Balakumar , Chivukula Subrahmanyam , Yelehanka Ramachandramurthy Pradeep
IPC分类号： B24B508
CPC分类号： B24B37/20 , B24B37/26 , B24B57/02
摘要： A new apparatus is provided that allows for uniform polishing of semiconductor surfaces. The single polishing pad of conventional CMP methods is divided into a split pad, the split pad allows for separate adjustments of CMP control parameters across the surface of the wafer. These adjustments can extend from the center of the wafer to its perimeter (along the radius of the wafer) thereby allowing for the elimination of conventional problems of non-uniformity of polishing between the center of the surface that is polished and the perimeter of the surface that is polished.
摘要翻译：提供了允许半导体表面的均匀抛光的新设备。传统CMP方法的单个抛光垫被分成分裂垫，分离垫允许跨晶片表面的CMP控制参数的单独调整。这些调整可以从晶片的中心延伸到其周边（沿着晶片的半径），从而可以消除抛光表面的中心与表面周边之间的抛光不均匀的常规问题那是抛光。

5. 发明授权

US06399448B1 Method for forming dual gate oxide 失效
标题翻译：形成双栅极氧化物的方法
公开(公告)号：US06399448B1
公开(公告)日：2002-06-04
申请号：US09443426
申请日：1999-11-19
申请人： Madhusudan Mukhopadhyay , Chivukula Subrahmanyam , Yelehanka Ramachandramurthy Pradeep
发明人： Madhusudan Mukhopadhyay , Chivukula Subrahmanyam , Yelehanka Ramachandramurthy Pradeep
IPC分类号： H01L218234
CPC分类号： H01L21/823462 , Y10S438/981
摘要： A method for forming a multiple thickness gate oxide layer by implanting nitrogen ions in a first area of a semiconductor substrate while a second area of the semiconductor substrate is masked; implanting argon ions into the second area of the semiconductor substrate while the first area of the semiconductor substrate is masked; and thermally growing a gate oxide layer wherein, the oxide growth is retarded in the first area and enhanced in the second area. A threshold voltage implant and/or an anti-punchthrough implant can optionally be implanted into the semiconductor substrate prior to the nitrigen implant using the same implant mask as the nitrogen implant for a low voltage gate, and prior to the argon implant using the same implant mask as the argonm implant for a high voltage gate, further reducing processing steps.
摘要翻译：一种在半导体衬底的第二区域被掩蔽的同时，在半导体衬底的第一区域中注入氮离子形成多层栅极氧化层的方法; 在半导体衬底的第一区域被掩蔽时将氩离子注入到半导体衬底的第二区域中; 并且热生长栅极氧化物层，其中氧化物生长在第一区域中延迟并在第二区域增强。在使用与用于低电压栅极的氮注入相同的注入掩模的氮掺杂之前，以及在使用相同植入物的氩注入之前，可以可选地将阈值电压注入和/或抗穿透注入注入到半导体衬底中掩模作为高压栅极的氩离子注入，进一步减少加工步骤。

6. 发明授权

US06228770B1 Method to form self-sealing air gaps between metal interconnects 有权
标题翻译：在金属互连之间形成自密封气隙的方法
公开(公告)号：US06228770B1
公开(公告)日：2001-05-08
申请号：US09531784
申请日：2000-03-21
申请人： Yelehanka Ramachandramurthy Pradeep , Vijai Kumar Chhagan , Henry Gerung , Madhusudan Mukhopadhyay
发明人： Yelehanka Ramachandramurthy Pradeep , Vijai Kumar Chhagan , Henry Gerung , Madhusudan Mukhopadhyay
IPC分类号： H01L2100
CPC分类号： H01L21/7682
摘要： A new method of forming metal interconnects with air gaps between adjacent interconnects in the manufacture of an integrated circuit device is achieved. A semiconductor substrate is provided. The metal interconnects are formed overlying the semiconductor substrate. A silicon nitride liner layer is deposited. A gap filling oxide layer is deposited to fill gaps between adjacent metal interconnects. The gap filling oxide layer is polished down to the silicon nitride liner layer. A silicon nitride thin layer is deposited. The silicon nitride thin layer is patterned using an oversized, reverse mask of the metal interconnects. The patterning of the silicon nitride thin layer creates openings to thereby expose a portion of the gap filling oxide. The gap filling oxide layer is etched away. A self-sealing oxide layer is deposited overlying the silicon nitride thin layer and the silicon nitride liner layer. The self-sealing oxide layer seals over the gaps between the silicon nitride thin layer and the silicon nitride liner layer to thereby form permanent air gaps between the adjacent metal interconnects, and the integrated circuit is completed.
摘要翻译：实现了在制造集成电路器件中在相邻互连之间形成具有气隙的金属互连的新方法。提供半导体衬底。金属互连形成在半导体衬底上。沉积氮化硅衬垫层。沉积间隙填充氧化物层以填充相邻的金属互连之间的间隙。间隙填充氧化物层被抛光到氮化硅衬垫层。沉积氮化硅薄层。使用金属互连的过大的反向掩模来对氮化硅薄层进行构图。氮化硅薄层的图案化形成开口，从而暴露间隙填充氧化物的一部分。间隙填充氧化物层被蚀刻掉。沉积氮化硅薄层和氮化硅衬层的自密封氧化层。自密封氧化物层在氮化硅薄层和氮化硅衬垫层之间的间隙上密封，从而在相邻的金属互连之间形成永久的气隙，并且完成集成电路。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式