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1. 发明授权

US5515517A Data processing device with test circuit 失效
标题翻译：具有测试电路的数据处理设备
公开(公告)号：US5515517A
公开(公告)日：1996-05-07
申请号：US357052
申请日：1994-12-14
申请人： Yasuyuki Nozuyama , Kazuhiko Ohashi
发明人： Yasuyuki Nozuyama , Kazuhiko Ohashi
IPC分类号： G06F11/22 , G01R31/3185 , G06F11/26
CPC分类号： G01R31/318541 , G01R31/318536
摘要： A data processing device with a test circuit has a plurality of macro blocks, a common bus for transferring the output of one of the macro blocks to the other macro blocks, and a tri-state buffer incorporated into each macro block. A bus control circuit selects the tri-state buffer in a normal operation mode in which the device performs its normal functions, in order to transfer the information stored in the macro block corresponding to the tri-state buffer selected by the bus control circuit to the common bus. A selecting control circuit, which includes a selector, an AND gate, and a flip-flop (F/F), is used for selecting the tri-state buffer in a test operation mode which the device has entered, then for transferring the information stored in the macro block corresponding to the tri-state buffer selected by the selecting control circuit to the common bus. A F/F is provided for setting the device in either the normal operation mode or the test operation mode. In the data processing device according to the present invention, in addition to the bus control circuit, which is used in the normal operation mode, the selecting control circuit, which is used in the test operation mode, is provided, so that the efficiency of the test vector generation is greatly improved.
摘要翻译：具有测试电路的数据处理装置具有多个宏块，用于将宏块中的一个的输出传送到其他宏块的公共总线，以及并入每个宏块中的三态缓冲器。总线控制电路在设备执行其正常功能的正常操作模式中选择三态缓冲器，以将存储在与由总线控制电路选择的三态缓冲器相对应的宏块中的信息传送到公车包括选择器，与门和触发器（F / F）的选择控制电路用于在设备输入的测试操作模式中选择三态缓冲器，然后用于传送信息存储在与由选择控制电路选择的三态缓冲器对应的宏块中的公共总线。提供F / F用于在正常操作模式或测试操作模式下设置设备。在根据本发明的数据处理装置中，除了在正常操作模式下使用的总线控制电路之外，还提供了在测试操作模式中使用的选择控制电路，测试向量生成得到很大的改善。

2. 发明授权

US07406645B2 Test pattern generating apparatus, method for automatically generating test patterns and computer program product for executing an application for a test pattern generating apparatus 失效
标题翻译：测试图形生成装置，用于自动生成测试图案的方法和用于执行测试图形生成装置的应用的计算机程序产品
公开(公告)号：US07406645B2
公开(公告)日：2008-07-29
申请号：US11158261
申请日：2005-06-20
申请人： Yasuyuki Nozuyama
发明人： Yasuyuki Nozuyama
IPC分类号： G01R31/28
CPC分类号： G01R31/31835
摘要： A test pattern generating apparatus includes an extractor configured to extract a plurality of layout parameters (elements) of a circuit under test based on gate net information and layout information of the circuit, and to link the layout parameters (elements) with corresponding fault models respectively. A weight calculator is configured to calculate a weight for each fault model linked with the layout parameters (elements) for both a plurality of undetected faults of the fault model and a plurality of faults detected by a plurality of test patterns, based on process failure (defect) information and layout parameter (element) information. An automatic test pattern generator is configured to generate the test patterns in accordance with the weight of each fault model linked with the layout parameters (elements).
摘要翻译：测试图形生成装置包括提取器，其被配置为基于所述电路的栅网信息和布局信息来提取被测电路的多个布局参数（元件），并且将布局参数（元件）分别与相应的故障模型链接。权重计算器被配置为基于过程失败来计算与用于故障模型的多个未检测到的故障和由多个测试模式检测的多个故障的布局参数（元件）链接的每个故障模型的权重（缺陷）信息和布局参数（元素）信息。自动测试模式生成器被配置为根据与布局参数（元素）链接的每个故障模型的权重生成测试模式。

3. 发明授权

US07139956B2 Semiconductor integrated circuit device and test method thereof 失效
公开(公告)号：US07139956B2
公开(公告)日：2006-11-21
申请号：US10918732
申请日：2004-08-16
申请人： Yasuyuki Nozuyama
发明人： Yasuyuki Nozuyama
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G11C29/56 , G11C29/40
摘要： A semiconductor integrated circuit device includes a test target circuit, a control circuit, and an observation circuit. The control circuit generates a reset signal, and an operation mode signal. The observation circuit is controlled by the signals, and receives input data from observation points in the test target circuit. The observation circuit includes a plurality of flip-flops. The observation circuit performs a reset operation in response to the reset signal. The observation circuit selectively performs a signature-compression operation, and a serial operation of outputting the test result, in response to the operation mode signal. The signature-compression operation is performed, using input data generated in the test target circuit in accordance with test patterns for a normal functional operation.

4. 发明申请

US20060005094A1 Test pattern generating apparatus, method for automatically generating test patterns and computer program product for executing an application for a test pattern generating apparatus 失效
标题翻译：测试图形生成装置，用于自动生成测试图案的方法和用于执行测试图形生成装置的应用的计算机程序产品
公开(公告)号：US20060005094A1
公开(公告)日：2006-01-05
申请号：US11158261
申请日：2005-06-20
申请人： Yasuyuki Nozuyama
发明人： Yasuyuki Nozuyama
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G01R31/31835
摘要： A test pattern generating apparatus includes an extractor configured to extract a plurality of layout parameters (elements) of a circuit under test based on gate net information and layout information of the circuit, and to link the layout parameters (elements) with corresponding fault models respectively. A weight calculator is configured to calculate a weight for each fault model linked with the layout parameters (elements) for both a plurality of undetected faults of the fault model and a plurality of faults detected by a plurality of test patterns, based on process failure (defect) information and layout parameter (element) information. An automatic test pattern generator is configured to generate the test patterns in accordance with the weight of each fault model linked with the layout parameters (elements).
摘要翻译：测试图形生成装置包括提取器，其被配置为基于所述电路的栅网信息和布局信息来提取被测电路的多个布局参数（元件），并且将布局参数（元件）分别与相应的故障模型链接。权重计算器被配置为基于过程失败来计算与用于故障模型的多个未检测到的故障和由多个测试模式检测的多个故障的布局参数（元件）链接的每个故障模型的权重（缺陷）信息和布局参数（元素）信息。自动测试模式生成器被配置为根据与布局参数（元素）链接的每个故障模型的权重生成测试模式。

5. 发明申请

US20050182587A1 Circuit quality evaluation method and apparatus, circuit quality evaluation program, and medium having the program recorded thereon 审中-公开
标题翻译：电路质量评估方法和装置，电路质量评估程序和其上记录有程序的介质
公开(公告)号：US20050182587A1
公开(公告)日：2005-08-18
申请号：US11052908
申请日：2005-02-09
申请人： Yasuo Sato , Shuji Hamada , Toshiyuki Maeda , Atsuo Takatori , Yasuyuki Nozuyama
发明人： Yasuo Sato , Shuji Hamada , Toshiyuki Maeda , Atsuo Takatori , Yasuyuki Nozuyama
IPC分类号： G01R31/317 , G01R31/30 , H01L21/66 , H01L21/82 , G06F19/00
CPC分类号： G01R31/31704 , G01R31/3016
摘要： A circuit quality evaluation method obtains an indicator linked to the quality of a circuit by applying information representing a minimum delay margin of a path passing through an assumed fault site, a machine cycle, and a delay fault occurrence frequency. Further, the circuit quality evaluation method evaluates the quality of the circuit based on the indicator.
摘要翻译：电路质量评估方法通过应用表示通过假定故障位置的路径的最小延迟余量，机器周期和延迟故障发生频率的信息来获得与电路质量相关联的指示符。此外，电路质量评估方法基于指示器来评估电路的质量。

6. 发明申请

US20050015691A1 Semiconductor integrated circuit device and test method thereof 失效
标题翻译：半导体集成电路器件及其测试方法
公开(公告)号：US20050015691A1
公开(公告)日：2005-01-20
申请号：US10918732
申请日：2004-08-16
申请人： Yasuyuki Nozuyama
发明人： Yasuyuki Nozuyama
IPC分类号： G01R31/28 , G01R31/3185 , G11C29/40 , G11C29/56 , H01L21/82 , H01L21/822 , H01L27/04 , H03K19/00
CPC分类号： G11C29/56 , G11C29/40
摘要： A semiconductor integrated circuit device includes a test target circuit, a control circuit, and an observation circuit. The control circuit generates a reset signal, and an operation mode signal. The observation circuit is controlled by the signals, and receives input data from observation points in the test target circuit. The observation circuit includes a plurality of flip-flops. The observation circuit performs a reset operation in response to the reset signal. The observation circuit selectively performs a signature-compression operation, and a serial operation of outputting the test result, in response to the operation mode signal. The signature-compression operation is performed, using input data generated in the test target circuit in accordance with test patterns for a normal functional operation.
摘要翻译：半导体集成电路器件包括测试对象电路，控制电路和观测电路。控制电路产生复位信号和操作模式信号。观测电路由信号控制，并从测试对象电路的观测点接收输入数据。观察电路包括多个触发器。观察电路根据复位信号进行复位动作。观察电路响应于操作模式信号选择性地进行签名压缩操作和输出测试结果的串行操作。使用根据用于正常功能操作的测试模式在测试对象电路中生成的输入数据来执行签名压缩操作。

7. 发明授权

US06223312B1 Test-facilitating circuit for information processing devices 失效
标题翻译：用于信息处理设备的测试便利电路
公开(公告)号：US06223312B1
公开(公告)日：2001-04-24
申请号：US08229135
申请日：1994-04-18
申请人： Yasuyuki Nozuyama
发明人： Yasuyuki Nozuyama
IPC分类号： G01R3128
CPC分类号： G06F11/27
摘要： A test-facilitating circuit selectively carries out tests for self-testing and for fault diagnosis and failure analysis. In a test for fault diagnosis or failure analysis, necessary test data are supplied from outside the circuit and microprograms for self-testing are used. When carrying out a test for fault diagnosis or failure analysis, a test data generating circuit for self-testing is inhibited from outputting test data to an internal bus and test data are taken in by the internal bus from external input terminals in accordance with a microinstruction.
摘要翻译：一个测试便利电路选择性地执行自检和故障诊断和故障分析的测试。在进行故障诊断或故障分析的测试中，需要从电路外部提供必要的测试数据，并使用微程序进行自检。当进行故障诊断或故障分析测试时，禁止用于自检的测试数据产生电路将测试数据输出到内部总线，并且测试数据由内部总线从外部输入端子根据微指令。

8. 发明授权

US5631910A Information processing system provided with self-diagnosing circuit and the self-diagnosing method therefor 失效
标题翻译：提供自诊断电路的信息处理系统及其自诊断方法
公开(公告)号：US5631910A
公开(公告)日：1997-05-20
申请号：US243517
申请日：1994-05-16
申请人： Yasuyuki Nozuyama , Tsuneaki Kudou
发明人： Yasuyuki Nozuyama , Tsuneaki Kudou
IPC分类号： G01R31/28 , G06F11/22 , G06F11/267 , H01L21/66 , G06F11/00
CPC分类号： G06F11/2236
摘要： An information processing system composed of a plurality of circuit blocks operative in an normal operation mode and in a self-diagnosis mode comprises: a clock signal generating circuit for generating a basic clock signal in the normal operation mode, and a first clock signal with a period. N times (N=2, 3, . . . ) as long as that of the basic clock signal and a second clock signal out of phase from the first clock signal by a delay less than one cycle of the first clock signal in the self-diagnosis mode; a memory for storing microinstructions for self-diagnosis operative in synchronism with the basic clock signal in the normal operation mode, and in synchronism with the first clock signal in the self-diagnosis mode; a decoder for inputting and decoding the mlcroinstructions for self-diagnosis stored in the memory; a test data generating circuit for generating test data in accordance with the decoded results obtained by the decoder in synchronism with the first clock signal at the self-diagnosis mode; first type circuit blocks operative in synchronism with the basic clock in the normal operation mode, for storing test data generated by said test data generating means In synchronism with the second clock and outputting test data therein In synchronism with the first clock In the self-diagnosis mode; second type circuit blocks for outputting output data corresponding to the test data provided in synchronism with the basic clock signal in the normal operation mode, and in synchronism with the first clock in the self-diagnosis mode; and a signature compressing circuit for inputting the test resultant data outputted from the circuit blocks to diagnose the operation of the circuit blocks, in synchronism with the second clock signal in the self-diagnosis mode.
摘要翻译：由在正常操作模式和自诊断模式下操作的多个电路块组成的信息处理系统包括：用于在正常操作模式下产生基本时钟信号的时钟信号发生电路和具有正常操作模式的第一时钟信号期。 N次（N = 2,3，...），只要基本时钟信号和第二时钟信号与第一时钟信号异相延迟小于自身中的第一时钟信号的一个周期的延迟诊断模式; 存储器，用于存储与正常操作模式中的基本时钟信号同步操作的自诊断微指令，并且与自诊断模式中的第一时钟信号同步; 用于输入和解码存储在存储器中的用于自诊断的mlcroinstructions的解码器; 测试数据产生电路，用于根据在自诊断模式下与第一时钟信号同步地由解码器获得的解码结果产生测试数据; 用于存储由所述测试数据产生装置产生的测试数据与第二时钟同步并在其中输出测试数据的第一类型电路块与正常操作模式中的基本时钟同步操作。与第一时钟同步在自诊断中模式; 第二类型电路块，用于在正常操作模式中输出与基本时钟信号同步提供的测试数据相对应的输出数据，并且与自诊断模式中的第一时钟同步; 以及签名压缩电路，用于输入从电路块输出的测试结果数据，以与自诊断模式中的第二时钟信号同步地诊断电路块的操作。

9. 发明授权

US5588006A Logic circuit having a control signal switching logic function and having a testing arrangement 失效
标题翻译：具有控制信号切换逻辑功能并具有测试装置的逻辑电路
公开(公告)号：US5588006A
公开(公告)日：1996-12-24
申请号：US139011
申请日：1993-10-21
申请人： Yasuyuki Nozuyama
发明人： Yasuyuki Nozuyama
IPC分类号： G01R31/28 , G01R31/3185 , H03K17/693 , H03K19/21 , G06F11/00
CPC分类号： G01R31/318547 , H03K17/693 , H03K19/215
摘要： A logic circuit for a built-in self test or for a built-in logic block observer responds to at least first and second input signals and control signals. The circuit includes a first circuit with two outputs, one for always outputting the second input signal, and the other for outputting the second input signal and the inverse value thereof according to a first control signal, a second circuit for selecting and outputting one of the two outputs of the first circuit according to the first input signal, then outputting an exclusive OR value or an exclusive NOR value of the first input signal and the second input signal, and a third circuit for providing a third input signal or a fixed value as a second input signal to the first circuit according to a second control signal. The inversion functions for obtaining an adequate polarity of signals employing clocked inverters, or transfer gates and an inverter. The logic functions also employ cascaded flip-flop circuits and a linear feedback shift register.
摘要翻译：用于内置自测或用于内置逻辑块观测器的逻辑电路至少响应于第一和第二输入信号和控制信号。电路包括具有两个输出的第一电路，一个用于总是输出第二输入信号，另一个用于根据第一控制信号输出第二输入信号及其反相值;第二电路，用于选择和输出根据第一输入信号的第一电路的两个输出，然后输出第一输入信号和第二输入信号的异或值或异或值，以及第三电路，用于提供第三输入信号或固定值作为根据第二控制信号到第一电路的第二输入信号。用于获得采用时钟反相器或传输门和逆变器的信号的足够极性的反转功能。逻辑功能还采用级联触发器电路和线性反馈移位寄存器。

10. 发明授权

US08508249B2 Semiconductor integrated circuit and method for designing the same 失效
标题翻译：半导体集成电路及其设计方法
公开(公告)号：US08508249B2
公开(公告)日：2013-08-13
申请号：US13237053
申请日：2011-09-20
申请人： Yasuyuki Nozuyama
发明人： Yasuyuki Nozuyama
IPC分类号： H03K19/00
CPC分类号： G06F17/5068 , G01R31/318536 , G06F17/5045 , H03K3/012
摘要： A semiconductor integrated circuit according to one embodiment includes a plurality of flip-flop groups configured by dividing a plurality of flip-flops, connected in series, for carrying out a serial operation of serially transferring data, a continuous signal determination circuit configured to output a first signal if outputs of the flip-flops contained in the flip-flop group match, and output a second signal in other cases; and a clock gating circuit configured not to provide a clock signal when receiving the first signal and to provide a clock signal when receiving the second signal with respect to the flip-flops other than a head of the flip-flop group.
摘要翻译：根据一个实施例的半导体集成电路包括多个触发器组，其通过分开串联连接的多个触发器来进行串行传送数据的串行操作，连续信号确定电路被配置为输出第一信号，如果触发器组中包含的触发器的输出匹配，并且在其他情况下输出第二信号; 以及时钟门控电路，其被配置为在接收到第一信号时不提供时钟信号，并且当接收除触发器组的头之外的触发器的第二信号时提供时钟信号。

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