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1. 发明申请

US20050182587A1 Circuit quality evaluation method and apparatus, circuit quality evaluation program, and medium having the program recorded thereon 审中-公开
标题翻译：电路质量评估方法和装置，电路质量评估程序和其上记录有程序的介质
公开(公告)号：US20050182587A1
公开(公告)日：2005-08-18
申请号：US11052908
申请日：2005-02-09
申请人： Yasuo Sato , Shuji Hamada , Toshiyuki Maeda , Atsuo Takatori , Yasuyuki Nozuyama
发明人： Yasuo Sato , Shuji Hamada , Toshiyuki Maeda , Atsuo Takatori , Yasuyuki Nozuyama
IPC分类号： G01R31/317 , G01R31/30 , H01L21/66 , H01L21/82 , G06F19/00
CPC分类号： G01R31/31704 , G01R31/3016
摘要： A circuit quality evaluation method obtains an indicator linked to the quality of a circuit by applying information representing a minimum delay margin of a path passing through an assumed fault site, a machine cycle, and a delay fault occurrence frequency. Further, the circuit quality evaluation method evaluates the quality of the circuit based on the indicator.
摘要翻译：电路质量评估方法通过应用表示通过假定故障位置的路径的最小延迟余量，机器周期和延迟故障发生频率的信息来获得与电路质量相关联的指示符。此外，电路质量评估方法基于指示器来评估电路的质量。

2. 发明申请

US20080120585A1 DELAY FAULT TEST QUALITY CALCULATION APPARATUS, DELAY FAULT TEST QUALITY CALCULATION METHOD, AND DELAY FAULT TEST PATTERN GENERATION APPARATUS 有权
标题翻译：延迟故障测试质量计算设备，延迟故障测试质量计算方法和延迟故障测试模式生成设备
公开(公告)号：US20080120585A1
公开(公告)日：2008-05-22
申请号：US11943170
申请日：2007-11-20
申请人： Yasuyuki Nozuyama , Atsuo Takatori
发明人： Yasuyuki Nozuyama , Atsuo Takatori
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/5081
摘要： A delay fault test quality calculation apparatus for calculating delay fault test quality to be achieved by a test pattern to be applied to a semiconductor integrated circuit includes a defect distribution extraction unit, a delay fault-layout element information extraction unit, and a weighting unit. The delay fault test quality calculation apparatus further includes a delay fault test quality calculation unit which calculates the delay fault test quality on the basis of delay design information of the semiconductor integrated circuit, detection information of the test pattern to test the semiconductor integrated circuit, execution conditions of the test, a physical defect distribution extracts the defect distribution extraction unit, and a weights adds the weighting unit.
摘要翻译：用于计算要应用于半导体集成电路的测试图形来实现的延迟故障测试质量的延迟故障测试质量计算装置包括缺陷分布提取单元，延迟故障布局单元信息提取单元和加权单元。延迟故障测试质量计算装置还包括延迟故障测试质量计算单元，其基于半导体集成电路的延迟设计信息，测试半导体集成电路的测试图案的检测信息，执行测试条件，物理缺陷分布提取缺陷分布提取单元，加权加权加权单位。

3. 发明授权

US08051403B2 Delay fault test quality calculation apparatus, delay fault test quality calculation method, and delay fault test pattern generation apparatus 有权
标题翻译：延迟故障测试质量计算装置，延迟故障测试质量计算方法和延迟故障测试模式生成装置
公开(公告)号：US08051403B2
公开(公告)日：2011-11-01
申请号：US11943170
申请日：2007-11-20
申请人： Yasuyuki Nozuyama , Atsuo Takatori
发明人： Yasuyuki Nozuyama , Atsuo Takatori
IPC分类号： G06F11/22
CPC分类号： G06F17/5031 , G06F17/5081
摘要： A delay fault test quality calculation apparatus for calculating delay fault test quality to be achieved by a test pattern to be applied to a semiconductor integrated circuit includes a defect distribution extraction unit, a delay fault-layout element information extraction unit, and a weighting unit. The delay fault test quality calculation apparatus further includes a delay fault test quality calculation unit which calculates the delay fault test quality on the basis of delay design information of the semiconductor integrated circuit, detection information of the test pattern to test the semiconductor integrated circuit, execution conditions of the test, a physical defect distribution extracts the defect distribution extraction unit, and a weights adds the weighting unit.
摘要翻译：用于计算要应用于半导体集成电路的测试图形来实现的延迟故障测试质量的延迟故障测试质量计算装置包括缺陷分布提取单元，延迟故障布局单元信息提取单元和加权单元。延迟故障测试质量计算装置还包括延迟故障测试质量计算单元，其基于半导体集成电路的延迟设计信息，测试半导体集成电路的测试图案的检测信息，执行测试条件，物理缺陷分布提取缺陷分布提取单元，加权加权加权单位。

4. 发明授权

US08185863B2 Delay fault test quality calculation apparatus, delay fault test quality calculation method, and delay fault test pattern generation apparatus 有权
标题翻译：延迟故障测试质量计算装置，延迟故障测试质量计算方法和延迟故障测试模式生成装置
公开(公告)号：US08185863B2
公开(公告)日：2012-05-22
申请号：US13243070
申请日：2011-09-23
申请人： Yasuyuki Nozuyama , Atsuo Takatori
发明人： Yasuyuki Nozuyama , Atsuo Takatori
IPC分类号： G06F11/22
CPC分类号： G06F17/5031 , G06F17/5081
摘要： A delay fault test quality calculation apparatus for calculating delay fault test quality to be achieved by a test pattern to be applied to a semiconductor integrated circuit includes a defect distribution extraction unit, a delay fault-layout element information extraction unit, and a weighting unit. The delay fault test quality calculation apparatus further includes a delay fault test quality calculation unit which calculates the delay fault test quality on the basis of delay design information of the semiconductor integrated circuit, detection information of the test pattern to test the semiconductor integrated circuit, execution conditions of the test, a physical defect distribution extracts the defect distribution extraction unit, and a weights adds the weighting unit.
摘要翻译：用于计算要应用于半导体集成电路的测试图形来实现的延迟故障测试质量的延迟故障测试质量计算装置包括缺陷分布提取单元，延迟故障布局单元信息提取单元和加权单元。延迟故障测试质量计算装置还包括延迟故障测试质量计算单元，其基于半导体集成电路的延迟设计信息，测试半导体集成电路的测试图案的检测信息，执行测试条件，物理缺陷分布提取缺陷分布提取单元，加权加权加权单位。

5. 发明申请

US20120016619A1 DELAY FAULT TEST QUALITY CALCULATION APPARATUS, DELAY FAULT TEST QUALITY CALCULATION METHOD, AND DELAY FAULT TEST PATTERN GENERATION APPARATUS 有权
标题翻译：延迟故障测试质量计算设备，延迟故障测试质量计算方法和延迟故障测试模式生成设备
公开(公告)号：US20120016619A1
公开(公告)日：2012-01-19
申请号：US13243070
申请日：2011-09-23
申请人： Yasuyuki Nozuyama , Atsuo Takatori
发明人： Yasuyuki Nozuyama , Atsuo Takatori
IPC分类号： G06F19/00
CPC分类号： G06F17/5031 , G06F17/5081
摘要： A delay fault test quality calculation apparatus for calculating delay fault test quality to be achieved by a test pattern to be applied to a semiconductor integrated circuit includes a defect distribution extraction unit, a delay fault-layout element information extraction unit, and a weighting unit. The delay fault test quality calculation apparatus further includes a delay fault test quality calculation unit which calculates the delay fault test quality on the basis of delay design information of the semiconductor integrated circuit, detection information of the test pattern to test the semiconductor integrated circuit, execution conditions of the test, a physical defect distribution extracts the defect distribution extraction unit, and a weights adds the weighting unit.
摘要翻译：用于计算要应用于半导体集成电路的测试图形来实现的延迟故障测试质量的延迟故障测试质量计算装置包括缺陷分布提取单元，延迟故障布局单元信息提取单元和加权单元。延迟故障测试质量计算装置还包括延迟故障测试质量计算单元，其基于半导体集成电路的延迟设计信息，测试半导体集成电路的测试图案的检测信息，执行测试条件，物理缺陷分布提取缺陷分布提取单元，加权加权加权单位。

6. 发明授权

US07406645B2 Test pattern generating apparatus, method for automatically generating test patterns and computer program product for executing an application for a test pattern generating apparatus 失效
标题翻译：测试图形生成装置，用于自动生成测试图案的方法和用于执行测试图形生成装置的应用的计算机程序产品
公开(公告)号：US07406645B2
公开(公告)日：2008-07-29
申请号：US11158261
申请日：2005-06-20
申请人： Yasuyuki Nozuyama
发明人： Yasuyuki Nozuyama
IPC分类号： G01R31/28
CPC分类号： G01R31/31835
摘要： A test pattern generating apparatus includes an extractor configured to extract a plurality of layout parameters (elements) of a circuit under test based on gate net information and layout information of the circuit, and to link the layout parameters (elements) with corresponding fault models respectively. A weight calculator is configured to calculate a weight for each fault model linked with the layout parameters (elements) for both a plurality of undetected faults of the fault model and a plurality of faults detected by a plurality of test patterns, based on process failure (defect) information and layout parameter (element) information. An automatic test pattern generator is configured to generate the test patterns in accordance with the weight of each fault model linked with the layout parameters (elements).
摘要翻译：测试图形生成装置包括提取器，其被配置为基于所述电路的栅网信息和布局信息来提取被测电路的多个布局参数（元件），并且将布局参数（元件）分别与相应的故障模型链接。权重计算器被配置为基于过程失败来计算与用于故障模型的多个未检测到的故障和由多个测试模式检测的多个故障的布局参数（元件）链接的每个故障模型的权重（缺陷）信息和布局参数（元素）信息。自动测试模式生成器被配置为根据与布局参数（元素）链接的每个故障模型的权重生成测试模式。

7. 发明授权

US07139956B2 Semiconductor integrated circuit device and test method thereof 失效
公开(公告)号：US07139956B2
公开(公告)日：2006-11-21
申请号：US10918732
申请日：2004-08-16
申请人： Yasuyuki Nozuyama
发明人： Yasuyuki Nozuyama
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G11C29/56 , G11C29/40
摘要： A semiconductor integrated circuit device includes a test target circuit, a control circuit, and an observation circuit. The control circuit generates a reset signal, and an operation mode signal. The observation circuit is controlled by the signals, and receives input data from observation points in the test target circuit. The observation circuit includes a plurality of flip-flops. The observation circuit performs a reset operation in response to the reset signal. The observation circuit selectively performs a signature-compression operation, and a serial operation of outputting the test result, in response to the operation mode signal. The signature-compression operation is performed, using input data generated in the test target circuit in accordance with test patterns for a normal functional operation.

8. 发明申请

US20060005094A1 Test pattern generating apparatus, method for automatically generating test patterns and computer program product for executing an application for a test pattern generating apparatus 失效
标题翻译：测试图形生成装置，用于自动生成测试图案的方法和用于执行测试图形生成装置的应用的计算机程序产品
公开(公告)号：US20060005094A1
公开(公告)日：2006-01-05
申请号：US11158261
申请日：2005-06-20
申请人： Yasuyuki Nozuyama
发明人： Yasuyuki Nozuyama
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G01R31/31835
摘要： A test pattern generating apparatus includes an extractor configured to extract a plurality of layout parameters (elements) of a circuit under test based on gate net information and layout information of the circuit, and to link the layout parameters (elements) with corresponding fault models respectively. A weight calculator is configured to calculate a weight for each fault model linked with the layout parameters (elements) for both a plurality of undetected faults of the fault model and a plurality of faults detected by a plurality of test patterns, based on process failure (defect) information and layout parameter (element) information. An automatic test pattern generator is configured to generate the test patterns in accordance with the weight of each fault model linked with the layout parameters (elements).
摘要翻译：测试图形生成装置包括提取器，其被配置为基于所述电路的栅网信息和布局信息来提取被测电路的多个布局参数（元件），并且将布局参数（元件）分别与相应的故障模型链接。权重计算器被配置为基于过程失败来计算与用于故障模型的多个未检测到的故障和由多个测试模式检测的多个故障的布局参数（元件）链接的每个故障模型的权重（缺陷）信息和布局参数（元素）信息。自动测试模式生成器被配置为根据与布局参数（元素）链接的每个故障模型的权重生成测试模式。

9. 发明申请

US20050015691A1 Semiconductor integrated circuit device and test method thereof 失效
标题翻译：半导体集成电路器件及其测试方法
公开(公告)号：US20050015691A1
公开(公告)日：2005-01-20
申请号：US10918732
申请日：2004-08-16
申请人： Yasuyuki Nozuyama
发明人： Yasuyuki Nozuyama
IPC分类号： G01R31/28 , G01R31/3185 , G11C29/40 , G11C29/56 , H01L21/82 , H01L21/822 , H01L27/04 , H03K19/00
CPC分类号： G11C29/56 , G11C29/40
摘要： A semiconductor integrated circuit device includes a test target circuit, a control circuit, and an observation circuit. The control circuit generates a reset signal, and an operation mode signal. The observation circuit is controlled by the signals, and receives input data from observation points in the test target circuit. The observation circuit includes a plurality of flip-flops. The observation circuit performs a reset operation in response to the reset signal. The observation circuit selectively performs a signature-compression operation, and a serial operation of outputting the test result, in response to the operation mode signal. The signature-compression operation is performed, using input data generated in the test target circuit in accordance with test patterns for a normal functional operation.
摘要翻译：半导体集成电路器件包括测试对象电路，控制电路和观测电路。控制电路产生复位信号和操作模式信号。观测电路由信号控制，并从测试对象电路的观测点接收输入数据。观察电路包括多个触发器。观察电路根据复位信号进行复位动作。观察电路响应于操作模式信号选择性地进行签名压缩操作和输出测试结果的串行操作。使用根据用于正常功能操作的测试模式在测试对象电路中生成的输入数据来执行签名压缩操作。

10. 发明授权

US06223312B1 Test-facilitating circuit for information processing devices 失效
标题翻译：用于信息处理设备的测试便利电路
公开(公告)号：US06223312B1
公开(公告)日：2001-04-24
申请号：US08229135
申请日：1994-04-18
申请人： Yasuyuki Nozuyama
发明人： Yasuyuki Nozuyama
IPC分类号： G01R3128
CPC分类号： G06F11/27
摘要： A test-facilitating circuit selectively carries out tests for self-testing and for fault diagnosis and failure analysis. In a test for fault diagnosis or failure analysis, necessary test data are supplied from outside the circuit and microprograms for self-testing are used. When carrying out a test for fault diagnosis or failure analysis, a test data generating circuit for self-testing is inhibited from outputting test data to an internal bus and test data are taken in by the internal bus from external input terminals in accordance with a microinstruction.
摘要翻译：一个测试便利电路选择性地执行自检和故障诊断和故障分析的测试。在进行故障诊断或故障分析的测试中，需要从电路外部提供必要的测试数据，并使用微程序进行自检。当进行故障诊断或故障分析测试时，禁止用于自检的测试数据产生电路将测试数据输出到内部总线，并且测试数据由内部总线从外部输入端子根据微指令。

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