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1. 发明申请

US20050206461A1 Integrated circuit device having clock signal output circuit 有权
标题翻译：具有时钟信号输出电路的集成电路器件
公开(公告)号：US20050206461A1
公开(公告)日：2005-09-22
申请号：US11075882
申请日：2005-03-10
申请人： Katsutoyo Misawa , Yasuyuki Ishikawa , Akira Suzuki , Yoshinori Teshima , Hideaki Ishihara
发明人： Katsutoyo Misawa , Yasuyuki Ishikawa , Akira Suzuki , Yoshinori Teshima , Hideaki Ishihara
IPC分类号： G06F1/04 , G06F1/26 , H03B1/00 , H03K3/03
CPC分类号： G06F1/04 , G06F1/26 , H03K3/0315
摘要： Integrated circuit device includes: a wiring; a clock signal output circuit including a ring oscillator; an internal circuit; an internal power supply generation circuit for supplying an electric power to the clock signal output circuit and to the internal circuit on the basis of a power supplied from an external circuit; and a capacitor connection terminal. The internal power supply generation circuit supplies the electric power to the ring oscillator through the wiring connecting between the internal power supply generation circuit and the capacitor connection terminal. The internal power supply generation circuit supplies the electric power to the internal circuit through the wiring connecting to the capacitor connection terminal.
摘要翻译：集成电路装置包括：布线; 包括环形振荡器的时钟信号输出电路; 内部电路; 内部电源产生电路，用于根据从外部电路提供的电力向时钟信号输出电路和内部电路提供电力; 和电容器连接端子。内部电源产生电路通过内部电源产生电路和电容器连接端子之间的布线将电力供给环形振荡器。内部电源产生电路通过连接到电容器连接端子的布线将电力供给内部电路。

2. 发明授权

US07248092B2 Clamp circuit device 有权
标题翻译：钳位电路器件
公开(公告)号：US07248092B2
公开(公告)日：2007-07-24
申请号：US11073564
申请日：2005-03-08
申请人： Katsutoyo Misawa , Yasuyuki Ishikawa , Akira Suzuki , Yoshinori Teshima , Hideaki Ishihara , Toshiharu Muramatsu
发明人： Katsutoyo Misawa , Yasuyuki Ishikawa , Akira Suzuki , Yoshinori Teshima , Hideaki Ishihara , Toshiharu Muramatsu
IPC分类号： H03K5/08
CPC分类号： H03K5/08
摘要： In a clamp circuit device, reference voltages are set up by a series circuit of an FET, a resistor and an FET. Gate potentials of FETs are set up by performing addition and subtraction of these reference voltages and a reference voltage generated by a bandgap reference circuit, respectively. The clamp circuit device is constructed by connecting together a source of the one FET with its drain connected with the power supply and a source of the other FET with its drain connected with the ground to an input terminal of a control IC unit. Thus, an input voltage is clamped to [V4+Vtp] when an excessive voltage of positive polarity is applied to an input terminal, and the input voltage is clamped to [V5−Vtn] when an excessive voltage of negative polarity is applied.
摘要翻译：在钳位电路器件中，参考电压由FET，电阻器和FET的串联电路构成。通过执行这些参考电压的加法和减法以及由带隙基准电路产生的参考电压来建立FET的栅极电位。钳位电路器件通过将一个FET的源极与其电源连接在一起而将另一个FET的源极与地线连接到控制IC单元的输入端而构成。因此，当施加过大的正极性电压到输入端子时，输入电压被钳位到[V 4+ Vtp]，并且当施加负极性的过大电压时，输入电压被钳位到[V 5- Vtn] 。

3. 发明申请

US20080303497A1 Semiconductor integrated circuit device for providing series regulator 有权
标题翻译：用于提供串联调节器的半导体集成电路器件
公开(公告)号：US20080303497A1
公开(公告)日：2008-12-11
申请号：US12076451
申请日：2008-03-19
申请人： Shinichirou Taguchi , Yasuyuki Ishikawa , Akira Suzuki , Hideaki Ishihara
发明人： Shinichirou Taguchi , Yasuyuki Ishikawa , Akira Suzuki , Hideaki Ishihara
IPC分类号： G05F1/00
CPC分类号： G05F1/56
摘要： A semiconductor integrated circuit device for controlling an external output transistor is provided. The semiconductor integrated circuit device comprises: a first power supply circuit including an output circuit and providing a first series regulator in cooperation with the output external transistor; and a plurality of terminals. The plurality of terminals includes a control signal output terminal and high and low electric potential side power supply terminals for supplying electric power to the first power supply circuit. At least one of the high and low electric potential side power supply terminals is arranged adjacent to the control signal output terminal and defined as a first terminal. Short-circuiting between the control signal output terminal and the first terminal causes the external output transistor to switch into an off state.
摘要翻译：提供一种用于控制外部输出晶体管的半导体集成电路器件。所述半导体集成电路装置包括：第一电源电路，包括输出电路，并与所述输出外部晶体管配合提供第一串联调节器; 和多个终端。多个端子包括用于向第一电源电路供电的控制信号输出端子和高低电位侧电源端子。高电压侧电源端子和低电位侧电源端子中的至少一个被配置为与控制信号输出端子相邻并被定义为第一端子。控制信号输出端子与第一端子之间的短路导致外部输出晶体管切换到断开状态。

4. 发明申请

US20070210834A1 Reset detection circuit in semiconductor integrated circuit 有权
标题翻译：半导体集成电路中的复位检测电路
公开(公告)号：US20070210834A1
公开(公告)日：2007-09-13
申请号：US11714203
申请日：2007-03-06
申请人： Yasuyuki Ishikawa , Akira Suzuki , Hideaki Ishihara
发明人： Yasuyuki Ishikawa , Akira Suzuki , Hideaki Ishihara
IPC分类号： H03K5/153
CPC分类号： H03K5/19 , H03K5/24
摘要： A reset detection circuit for a logic circuit and a RAM includes a first determining circuit, a second determining circuit and a reset signal generating circuit. The first determining circuit operates with a first voltage and determines whether a second voltage is equal to or higher than a reset voltage for the logic circuit. The second determining circuit operates with the first voltage and determines whether the first voltage is equal to or higher than a minimum operating voltage as a guarantee voltage for an operation of the first determining circuit. The reset signal generating circuit outputs a reset signal for resetting the logic circuit and the RAM, when the first voltage is lower than the minimum operating voltage and the second voltage is lower than the reset voltage.
摘要翻译：用于逻辑电路和RAM的复位检测电路包括第一确定电路，第二确定电路和复位信号发生电路。第一确定电路以第一电压工作，并确定第二电压是否等于或高于逻辑电路的复位电压。第二确定电路以第一电压工作，并且确定第一电压是否等于或高于最小工作电压，作为用于第一确定电路的操作的保证电压。当第一电压低于最小工作电压并且第二电压低于复位电压时，复位信号发生电路输出用于复位逻辑电路和RAM的复位信号。

5. 发明授权

US07906946B2 Semiconductor integrated circuit device for providing series regulator 有权
标题翻译：用于提供串联调节器的半导体集成电路器件
公开(公告)号：US07906946B2
公开(公告)日：2011-03-15
申请号：US12076451
申请日：2008-03-19
申请人： Shinichirou Taguchi , Yasuyuki Ishikawa , Akira Suzuki , Hideaki Ishihara
发明人： Shinichirou Taguchi , Yasuyuki Ishikawa , Akira Suzuki , Hideaki Ishihara
IPC分类号： G05F1/00
CPC分类号： G05F1/56
摘要： A semiconductor integrated circuit device for controlling an external output transistor is provided. The semiconductor integrated circuit device comprises: a first power supply circuit including an output circuit and providing a first series regulator in cooperation with the output external transistor; and a plurality of terminals. The plurality of terminals includes a control signal output terminal and high and low electric potential side power supply terminals for supplying electric power to the first power supply circuit. At least one of the high and low electric potential side power supply terminals is arranged adjacent to the control signal output terminal and defined as a first terminal. Short-circuiting between the control signal output terminal and the first terminal causes the external output transistor to switch into an off state.
摘要翻译：提供一种用于控制外部输出晶体管的半导体集成电路器件。所述半导体集成电路装置包括：第一电源电路，包括输出电路，并与所述输出外部晶体管配合提供第一串联调节器; 和多个终端。多个端子包括用于向第一电源电路供电的控制信号输出端子和高低电位侧电源端子。高电压侧电源端子和低电位侧电源端子中的至少一个被配置为与控制信号输出端子相邻并被定义为第一端子。控制信号输出端子与第一端子之间的短路导致外部输出晶体管切换到断开状态。

6. 发明授权

US07313048B2 Reset detection circuit in semiconductor integrated circuit 有权
公开(公告)号：US07313048B2
公开(公告)日：2007-12-25
申请号：US11714203
申请日：2007-03-06
申请人： Yasuyuki Ishikawa , Akira Suzuki , Hideaki Ishihara
发明人： Yasuyuki Ishikawa , Akira Suzuki , Hideaki Ishihara
IPC分类号： G11C29/52 , G05F1/10 , G05F3/02
CPC分类号： H03K5/19 , H03K5/24
摘要： A reset detection circuit for a logic circuit and a RAM includes a first determining circuit, a second determining circuit and a reset signal generating circuit. The first determining circuit operates with a first voltage and determines whether a second voltage is equal to or higher than a reset voltage for the logic circuit. The second determining circuit operates with the first voltage and determines whether the first voltage is equal to or higher than a minimum operating voltage as a guarantee voltage for an operation of the first determining circuit. The reset signal generating circuit outputs a reset signal for resetting the logic circuit and the RAM, when the first voltage is lower than the minimum operating voltage and the second voltage is lower than the reset voltage.

7. 发明授权

US07221206B2 Integrated circuit device having clock signal output circuit 有权
标题翻译：具有时钟信号输出电路的集成电路器件
公开(公告)号：US07221206B2
公开(公告)日：2007-05-22
申请号：US11075882
申请日：2005-03-10
申请人： Katsutoyo Misawa , Yasuyuki Ishikawa , Akira Suzuki , Yoshinori Teshima , Hideaki Ishihara
发明人： Katsutoyo Misawa , Yasuyuki Ishikawa , Akira Suzuki , Yoshinori Teshima , Hideaki Ishihara
IPC分类号： G06F1/04
CPC分类号： G06F1/04 , G06F1/26 , H03K3/0315
摘要： Integrated circuit device includes: a wiring; a clock signal output circuit including a ring oscillator; an internal circuit; an internal power supply generation circuit for supplying an electric power to the clock signal output circuit and to the internal circuit on the basis of a power supplied from an external circuit; and a capacitor connection terminal. The internal power supply generation circuit supplies the electric power to the ring oscillator through the wiring connecting between the internal power supply generation circuit and the capacitor connection terminal. The internal power supply generation circuit supplies the electric power to the internal circuit through the wiring connecting to the capacitor connection terminal.
摘要翻译：集成电路装置包括：布线; 包括环形振荡器的时钟信号输出电路; 内部电路; 内部电源产生电路，用于根据从外部电路提供的电力向时钟信号输出电路和内部电路提供电力; 和电容器连接端子。内部电源产生电路通过内部电源产生电路和电容器连接端子之间的布线将电力供给环形振荡器。内部电源产生电路通过连接到电容器连接端子的布线将电力供给内部电路。

8. 发明申请

US20050206429A1 Clamp circuit device 有权
标题翻译：钳位电路器件
公开(公告)号：US20050206429A1
公开(公告)日：2005-09-22
申请号：US11073564
申请日：2005-03-08
申请人： Katsutoyo Misawa , Yasuyuki Ishikawa , Akira Suzuki , Yoshinori Teshima , Hideaki Ishihara , Toshiharu Muramatsu
发明人： Katsutoyo Misawa , Yasuyuki Ishikawa , Akira Suzuki , Yoshinori Teshima , Hideaki Ishihara , Toshiharu Muramatsu
IPC分类号： H03K5/08 , H03L5/00
CPC分类号： H03K5/08
摘要： In a clamp circuit device, reference voltages are set up by a series circuit of an FET, a resistor and an FET. Gate potentials of FETs are set up by performing addition and subtraction of these reference voltages and a reference voltage generated by a bandgap reference circuit, respectively. The clamp circuit device is constructed by connecting together a source of the one FET with its drain connected with the power supply and a source of the other FET with its drain connected with the ground to an input terminal of a control IC unit. Thus, an input voltage is clamped to [V4+Vtp] when an excessive voltage of positive polarity is applied to an input terminal, and the input voltage is clamped to [V5−Vtn] when an excessive voltage of negative polarity is applied.
摘要翻译：在钳位电路器件中，参考电压由FET，电阻器和FET的串联电路构成。通过执行这些参考电压的加法和减法以及由带隙基准电路产生的参考电压来建立FET的栅极电位。钳位电路器件通过将一个FET的源极与其电源连接在一起而将另一个FET的源极与地线连接到控制IC单元的输入端而构成。因此，当施加过大的正极性电压到输入端子时，输入电压被钳位到[V 4+ Vtp]，并且当施加负极性的过大电压时，输入电压被钳位到[V 5- Vtn] 。

9. 发明授权

US07467294B2 Microcomputer with mode decoder operable upon receipt of either power-on or external reset signal 有权
标题翻译：具有模式解码器的微计算机，在接收到电源接通或外部复位信号时可操作
公开(公告)号：US07467294B2
公开(公告)日：2008-12-16
申请号：US11270447
申请日：2005-11-10
申请人： Toshihiko Matsuoka , Naoki Ito , Hideaki Ishihara , Yasuyuki Ishikawa
发明人： Toshihiko Matsuoka , Naoki Ito , Hideaki Ishihara , Yasuyuki Ishikawa
IPC分类号： G06F9/00
CPC分类号： G06F1/24
摘要： A microcomputer includes a plurality of operation mode selecting terminals to which data for selecting plural operation modes are set. The plurality of operation mode selecting terminals is designed so as to be usable as general-purpose input terminals or output terminals. A decoder decodes the data set to the plurality of operation mode selecting terminals and outputting a mode signal for switching an internal function in accordance with a selected operation mode. A timing signal output unit outputs to the decoder a timing signal for making the decoder execute a decode operation. The timing signal output unit outputs the timing signal when at least one of power-on-reset and an externally controlled reset is varied from an active state to an inactive state.
摘要翻译：微型计算机包括多个操作模式选择端子，用于选择多个操作模式的数据。多个操作模式选择端子被设计为可用作通用输入端子或输出端子。解码器将对多个操作模式选择端子设置的数据进行解码，并根据选择的操作模式输出用于切换内部功能的模式信号。定时信号输出单元向解码器输出用于使解码器执行解码操作的定时信号。当上电复位和外部控制的复位中的至少一个从活动状态变为非活动状态时，定时信号输出单元输出定时信号。

10. 发明申请

US20060107082A1 Microcomputer 有权
标题翻译：微电脑
公开(公告)号：US20060107082A1
公开(公告)日：2006-05-18
申请号：US11270447
申请日：2005-11-10
申请人： Toshihiko Matsuoka , Naoki Ito , Hideaki Ishihara , Yasuyuki Ishikawa
发明人： Toshihiko Matsuoka , Naoki Ito , Hideaki Ishihara , Yasuyuki Ishikawa
IPC分类号： G06F1/30
CPC分类号： G06F1/24
摘要： A microcomputer includes a plurality of operation mode selecting terminals to which data for selecting plural operation modes are set. The plurality of operation mode selecting terminals is designed so as to be usable as general-purpose input terminals or output terminals. A decoder decodes the data set to the plurality of operation mode selecting terminals and outputting a mode signal for switching an internal function in accordance with a selected operation mode. A timing signal output unit outputs to the decoder a timing signal for making the decoder execute a decode operation. The timing signal output unit outputs the timing signal when at least one of power-on-reset and an externally controlled reset is varied from an active state to an inactive state.
摘要翻译：微型计算机包括多个操作模式选择端子，用于选择多个操作模式的数据。多个操作模式选择端子被设计为可用作通用输入端子或输出端子。解码器将对多个操作模式选择端子设置的数据进行解码，并根据选择的操作模式输出用于切换内部功能的模式信号。定时信号输出单元向解码器输出用于使解码器执行解码操作的定时信号。当上电复位和外部控制的复位中的至少一个从活动状态变为非活动状态时，定时信号输出单元输出定时信号。

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