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1. 发明申请

US20050206461A1 Integrated circuit device having clock signal output circuit 有权
标题翻译：具有时钟信号输出电路的集成电路器件
公开(公告)号：US20050206461A1
公开(公告)日：2005-09-22
申请号：US11075882
申请日：2005-03-10
申请人： Katsutoyo Misawa , Yasuyuki Ishikawa , Akira Suzuki , Yoshinori Teshima , Hideaki Ishihara
发明人： Katsutoyo Misawa , Yasuyuki Ishikawa , Akira Suzuki , Yoshinori Teshima , Hideaki Ishihara
IPC分类号： G06F1/04 , G06F1/26 , H03B1/00 , H03K3/03
CPC分类号： G06F1/04 , G06F1/26 , H03K3/0315
摘要： Integrated circuit device includes: a wiring; a clock signal output circuit including a ring oscillator; an internal circuit; an internal power supply generation circuit for supplying an electric power to the clock signal output circuit and to the internal circuit on the basis of a power supplied from an external circuit; and a capacitor connection terminal. The internal power supply generation circuit supplies the electric power to the ring oscillator through the wiring connecting between the internal power supply generation circuit and the capacitor connection terminal. The internal power supply generation circuit supplies the electric power to the internal circuit through the wiring connecting to the capacitor connection terminal.
摘要翻译：集成电路装置包括：布线; 包括环形振荡器的时钟信号输出电路; 内部电路; 内部电源产生电路，用于根据从外部电路提供的电力向时钟信号输出电路和内部电路提供电力; 和电容器连接端子。内部电源产生电路通过内部电源产生电路和电容器连接端子之间的布线将电力供给环形振荡器。内部电源产生电路通过连接到电容器连接端子的布线将电力供给内部电路。

2. 发明授权

US07221206B2 Integrated circuit device having clock signal output circuit 有权
标题翻译：具有时钟信号输出电路的集成电路器件
公开(公告)号：US07221206B2
公开(公告)日：2007-05-22
申请号：US11075882
申请日：2005-03-10
申请人： Katsutoyo Misawa , Yasuyuki Ishikawa , Akira Suzuki , Yoshinori Teshima , Hideaki Ishihara
发明人： Katsutoyo Misawa , Yasuyuki Ishikawa , Akira Suzuki , Yoshinori Teshima , Hideaki Ishihara
IPC分类号： G06F1/04
CPC分类号： G06F1/04 , G06F1/26 , H03K3/0315
摘要： Integrated circuit device includes: a wiring; a clock signal output circuit including a ring oscillator; an internal circuit; an internal power supply generation circuit for supplying an electric power to the clock signal output circuit and to the internal circuit on the basis of a power supplied from an external circuit; and a capacitor connection terminal. The internal power supply generation circuit supplies the electric power to the ring oscillator through the wiring connecting between the internal power supply generation circuit and the capacitor connection terminal. The internal power supply generation circuit supplies the electric power to the internal circuit through the wiring connecting to the capacitor connection terminal.
摘要翻译：集成电路装置包括：布线; 包括环形振荡器的时钟信号输出电路; 内部电路; 内部电源产生电路，用于根据从外部电路提供的电力向时钟信号输出电路和内部电路提供电力; 和电容器连接端子。内部电源产生电路通过内部电源产生电路和电容器连接端子之间的布线将电力供给环形振荡器。内部电源产生电路通过连接到电容器连接端子的布线将电力供给内部电路。

3. 发明申请

US20050206429A1 Clamp circuit device 有权
标题翻译：钳位电路器件
公开(公告)号：US20050206429A1
公开(公告)日：2005-09-22
申请号：US11073564
申请日：2005-03-08
申请人： Katsutoyo Misawa , Yasuyuki Ishikawa , Akira Suzuki , Yoshinori Teshima , Hideaki Ishihara , Toshiharu Muramatsu
发明人： Katsutoyo Misawa , Yasuyuki Ishikawa , Akira Suzuki , Yoshinori Teshima , Hideaki Ishihara , Toshiharu Muramatsu
IPC分类号： H03K5/08 , H03L5/00
CPC分类号： H03K5/08
摘要： In a clamp circuit device, reference voltages are set up by a series circuit of an FET, a resistor and an FET. Gate potentials of FETs are set up by performing addition and subtraction of these reference voltages and a reference voltage generated by a bandgap reference circuit, respectively. The clamp circuit device is constructed by connecting together a source of the one FET with its drain connected with the power supply and a source of the other FET with its drain connected with the ground to an input terminal of a control IC unit. Thus, an input voltage is clamped to [V4+Vtp] when an excessive voltage of positive polarity is applied to an input terminal, and the input voltage is clamped to [V5−Vtn] when an excessive voltage of negative polarity is applied.
摘要翻译：在钳位电路器件中，参考电压由FET，电阻器和FET的串联电路构成。通过执行这些参考电压的加法和减法以及由带隙基准电路产生的参考电压来建立FET的栅极电位。钳位电路器件通过将一个FET的源极与其电源连接在一起而将另一个FET的源极与地线连接到控制IC单元的输入端而构成。因此，当施加过大的正极性电压到输入端子时，输入电压被钳位到[V 4+ Vtp]，并且当施加负极性的过大电压时，输入电压被钳位到[V 5- Vtn] 。

4. 发明授权

US07248092B2 Clamp circuit device 有权
标题翻译：钳位电路器件
公开(公告)号：US07248092B2
公开(公告)日：2007-07-24
申请号：US11073564
申请日：2005-03-08
申请人： Katsutoyo Misawa , Yasuyuki Ishikawa , Akira Suzuki , Yoshinori Teshima , Hideaki Ishihara , Toshiharu Muramatsu
发明人： Katsutoyo Misawa , Yasuyuki Ishikawa , Akira Suzuki , Yoshinori Teshima , Hideaki Ishihara , Toshiharu Muramatsu
IPC分类号： H03K5/08
CPC分类号： H03K5/08
摘要： In a clamp circuit device, reference voltages are set up by a series circuit of an FET, a resistor and an FET. Gate potentials of FETs are set up by performing addition and subtraction of these reference voltages and a reference voltage generated by a bandgap reference circuit, respectively. The clamp circuit device is constructed by connecting together a source of the one FET with its drain connected with the power supply and a source of the other FET with its drain connected with the ground to an input terminal of a control IC unit. Thus, an input voltage is clamped to [V4+Vtp] when an excessive voltage of positive polarity is applied to an input terminal, and the input voltage is clamped to [V5−Vtn] when an excessive voltage of negative polarity is applied.
摘要翻译：在钳位电路器件中，参考电压由FET，电阻器和FET的串联电路构成。通过执行这些参考电压的加法和减法以及由带隙基准电路产生的参考电压来建立FET的栅极电位。钳位电路器件通过将一个FET的源极与其电源连接在一起而将另一个FET的源极与地线连接到控制IC单元的输入端而构成。因此，当施加过大的正极性电压到输入端子时，输入电压被钳位到[V 4+ Vtp]，并且当施加负极性的过大电压时，输入电压被钳位到[V 5- Vtn] 。

5. 发明授权

US07906946B2 Semiconductor integrated circuit device for providing series regulator 有权
标题翻译：用于提供串联调节器的半导体集成电路器件
公开(公告)号：US07906946B2
公开(公告)日：2011-03-15
申请号：US12076451
申请日：2008-03-19
申请人： Shinichirou Taguchi , Yasuyuki Ishikawa , Akira Suzuki , Hideaki Ishihara
发明人： Shinichirou Taguchi , Yasuyuki Ishikawa , Akira Suzuki , Hideaki Ishihara
IPC分类号： G05F1/00
CPC分类号： G05F1/56
摘要： A semiconductor integrated circuit device for controlling an external output transistor is provided. The semiconductor integrated circuit device comprises: a first power supply circuit including an output circuit and providing a first series regulator in cooperation with the output external transistor; and a plurality of terminals. The plurality of terminals includes a control signal output terminal and high and low electric potential side power supply terminals for supplying electric power to the first power supply circuit. At least one of the high and low electric potential side power supply terminals is arranged adjacent to the control signal output terminal and defined as a first terminal. Short-circuiting between the control signal output terminal and the first terminal causes the external output transistor to switch into an off state.
摘要翻译：提供一种用于控制外部输出晶体管的半导体集成电路器件。所述半导体集成电路装置包括：第一电源电路，包括输出电路，并与所述输出外部晶体管配合提供第一串联调节器; 和多个终端。多个端子包括用于向第一电源电路供电的控制信号输出端子和高低电位侧电源端子。高电压侧电源端子和低电位侧电源端子中的至少一个被配置为与控制信号输出端子相邻并被定义为第一端子。控制信号输出端子与第一端子之间的短路导致外部输出晶体管切换到断开状态。

6. 发明授权

US07313048B2 Reset detection circuit in semiconductor integrated circuit 有权
公开(公告)号：US07313048B2
公开(公告)日：2007-12-25
申请号：US11714203
申请日：2007-03-06
申请人： Yasuyuki Ishikawa , Akira Suzuki , Hideaki Ishihara
发明人： Yasuyuki Ishikawa , Akira Suzuki , Hideaki Ishihara
IPC分类号： G11C29/52 , G05F1/10 , G05F3/02
CPC分类号： H03K5/19 , H03K5/24
摘要： A reset detection circuit for a logic circuit and a RAM includes a first determining circuit, a second determining circuit and a reset signal generating circuit. The first determining circuit operates with a first voltage and determines whether a second voltage is equal to or higher than a reset voltage for the logic circuit. The second determining circuit operates with the first voltage and determines whether the first voltage is equal to or higher than a minimum operating voltage as a guarantee voltage for an operation of the first determining circuit. The reset signal generating circuit outputs a reset signal for resetting the logic circuit and the RAM, when the first voltage is lower than the minimum operating voltage and the second voltage is lower than the reset voltage.

7. 发明申请

US20080303497A1 Semiconductor integrated circuit device for providing series regulator 有权
标题翻译：用于提供串联调节器的半导体集成电路器件
公开(公告)号：US20080303497A1
公开(公告)日：2008-12-11
申请号：US12076451
申请日：2008-03-19
申请人： Shinichirou Taguchi , Yasuyuki Ishikawa , Akira Suzuki , Hideaki Ishihara
发明人： Shinichirou Taguchi , Yasuyuki Ishikawa , Akira Suzuki , Hideaki Ishihara
IPC分类号： G05F1/00
CPC分类号： G05F1/56
摘要： A semiconductor integrated circuit device for controlling an external output transistor is provided. The semiconductor integrated circuit device comprises: a first power supply circuit including an output circuit and providing a first series regulator in cooperation with the output external transistor; and a plurality of terminals. The plurality of terminals includes a control signal output terminal and high and low electric potential side power supply terminals for supplying electric power to the first power supply circuit. At least one of the high and low electric potential side power supply terminals is arranged adjacent to the control signal output terminal and defined as a first terminal. Short-circuiting between the control signal output terminal and the first terminal causes the external output transistor to switch into an off state.
摘要翻译：提供一种用于控制外部输出晶体管的半导体集成电路器件。所述半导体集成电路装置包括：第一电源电路，包括输出电路，并与所述输出外部晶体管配合提供第一串联调节器; 和多个终端。多个端子包括用于向第一电源电路供电的控制信号输出端子和高低电位侧电源端子。高电压侧电源端子和低电位侧电源端子中的至少一个被配置为与控制信号输出端子相邻并被定义为第一端子。控制信号输出端子与第一端子之间的短路导致外部输出晶体管切换到断开状态。

8. 发明申请

US20070210834A1 Reset detection circuit in semiconductor integrated circuit 有权
标题翻译：半导体集成电路中的复位检测电路
公开(公告)号：US20070210834A1
公开(公告)日：2007-09-13
申请号：US11714203
申请日：2007-03-06
申请人： Yasuyuki Ishikawa , Akira Suzuki , Hideaki Ishihara
发明人： Yasuyuki Ishikawa , Akira Suzuki , Hideaki Ishihara
IPC分类号： H03K5/153
CPC分类号： H03K5/19 , H03K5/24
摘要： A reset detection circuit for a logic circuit and a RAM includes a first determining circuit, a second determining circuit and a reset signal generating circuit. The first determining circuit operates with a first voltage and determines whether a second voltage is equal to or higher than a reset voltage for the logic circuit. The second determining circuit operates with the first voltage and determines whether the first voltage is equal to or higher than a minimum operating voltage as a guarantee voltage for an operation of the first determining circuit. The reset signal generating circuit outputs a reset signal for resetting the logic circuit and the RAM, when the first voltage is lower than the minimum operating voltage and the second voltage is lower than the reset voltage.
摘要翻译：用于逻辑电路和RAM的复位检测电路包括第一确定电路，第二确定电路和复位信号发生电路。第一确定电路以第一电压工作，并确定第二电压是否等于或高于逻辑电路的复位电压。第二确定电路以第一电压工作，并且确定第一电压是否等于或高于最小工作电压，作为用于第一确定电路的操作的保证电压。当第一电压低于最小工作电压并且第二电压低于复位电压时，复位信号发生电路输出用于复位逻辑电路和RAM的复位信号。

9. 发明授权

US06737905B1 Clamp circuit 失效
标题翻译：钳位电路
公开(公告)号：US06737905B1
公开(公告)日：2004-05-18
申请号：US10374695
申请日：2003-02-26
申请人： Shinichi Noda , Hideaki Ishihara , Akira Suzuki
发明人： Shinichi Noda , Hideaki Ishihara , Akira Suzuki
IPC分类号： H03K508
CPC分类号： H03K5/08 , G05F3/242
摘要： The clamp circuit clamps an input voltage at prescribed higher and lower clamp voltages which are stabilized under a temperature fluctuation. Transistors Q12 and Q14 are switched on in their linear region. In a lower voltage clamp circuit 18, an Vin detecting circuit 20 outputs Va1 by level-shifting Vin by Q13 and voltage-divides by series resistance circuit 23 the level-shifted Vin, while a reference voltage generating circuit 21 outputs Vr1 by level-shifting 0 V by Q15 and voltage-divides by series resistance circuit 25 the level-shifted voltage. Q11 is switched on, when a comparator 22 determines that Va1 descends and goes across Vr1. Here, Q12 is of the same characteristics as Q14, while Q13is of the same characteristics as Q15. Further, the resistance of the circuits 23 is the same as that of the circuit 25. The higher voltage clamp circuit 19 is similar to the circuit 18.
摘要翻译：钳位电路以在温度波动下稳定的规定的较高和较低钳位电压来钳位输入电压。晶体管Q12和Q14在它们的线性区域中导通。在较低电压钳位电路18中，Vin检测电路20通过电平移位Vin输出Va1，并通过串联电阻电路23对电平移位的Vin进行电压分压，而参考电压产生电路21通过电平移位输出Vr1 0 V由Q15和电压分压由串联电阻电路25的电平转换电压。当比较器22确定Va1下降并经过Vr1时，Q11接通。这里，Q12具有与Q14相同的特性，而Q13具有与Q15相同的特性。此外，电路23的电阻与电路25的电阻相同。较高电压钳位电路19类似于电路18。

10. 发明授权

US06876180B2 Power supply circuit having a start up circuit 有权
标题翻译：电源电路具有启动电路
公开(公告)号：US06876180B2
公开(公告)日：2005-04-05
申请号：US10292125
申请日：2002-11-11
申请人： Akira Suzuki , Hirofumi Abe , Hideaki Ishihara
发明人： Akira Suzuki , Hirofumi Abe , Hideaki Ishihara
IPC分类号： G05F1/56 , G05F1/575 , G05F1/40 , G05F1/44
CPC分类号： G05F1/575
摘要： A reference voltage circuit and an operational amplifier operate when an output voltage is produced from an output terminal of a power supply circuit. When the output voltage is low in the rising phase of a power source voltage, a transistor Q17 in a startup circuit turns on and a transistor Q14 turns off to surely turn on transistors Q11 and Q12. Upon the output voltage exceeding a predetermined level, the transistor Q17 turns off and an ordinary feedback control starts.
摘要翻译：当从电源电路的输出端产生输出电压时，参考电压电路和运算放大器工作。当在电源电压的上升相中的输出电压为低时，启动电路中的晶体管Q17导通，晶体管Q14截止，可靠地导通晶体管Q11，Q12。当输出电压超过预定电平时，晶体管Q17截止，并开始普通的反馈控制。

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