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1. 发明授权

US07342562B2 Liquid crystal drive device 有权
标题翻译：液晶驱动装置
公开(公告)号：US07342562B2
公开(公告)日：2008-03-11
申请号：US10830072
申请日：2004-04-23
申请人： Yasushi Kawase , Takesada Akiba , Kazuya Endo , Goro Sakamaki
发明人： Yasushi Kawase , Takesada Akiba , Kazuya Endo , Goro Sakamaki
IPC分类号： G09G3/36
CPC分类号： G09G3/3655 , G09G3/3696 , G09G2330/021
摘要： By implementing reduction in power of common electrode voltages applied from a power source of a liquid crystal drive device to common electrode interconnects of a liquid crystal display panel, respectively, reduction in power consumption of the liquid crystal display panel as a whole is attained.A VCOM operation waveform in a charging process from a second voltage VCOML to a first voltage VCOMH shows that a charging current Icha represents the sum of a charging current from VCOML to a reference voltage VCI, Icha1=Cp (VCI−VCOML)/Δt, and a charging current from the reference voltage VCI to the first voltage VCOMH, Icha2=Cp (VCOMH−VCI)/Δt. Accordingly, power consumed by Icha1 is the reference voltage VCI×Icha1, and power consumed by Icha2 is VCI×Icha2×2. Meanwhile, a discharging current at a time of discharging from the first voltage VCOMH to the second voltage VCOML is the sum of a discharging current from the first voltage VCOMH to the ground potential GND, Idis1=Cp (VCOMH−GND)/Δt, and a discharging current from the ground potential GND to the second voltage VCOML, Idis2=Cp (GND−VCOML)/Δt. Now, if converted in terms of power consumed at the reference voltage VCI, since Idis1 represents discharge to GND, power consumption thereby becomes zero. Then, consumed power due to the discharging current from the ground potential GND to the second voltage VCOML, Idis2, is VCI×Idis2.
摘要翻译：通过将从液晶驱动装置的电源施加的共电极电压的功率分别实现为液晶显示面板的公共电极互连，能够实现液晶显示面板的整体功耗的降低。从第二电压VCOML到第一电压VCOMH的充电过程中的VCOM操作波形示出充电电流Icha表示从VCOML到参考电压VCI的充电电流之和Icha 1 = Cp（VCI-VCOML）/ Deltat ，以及从参考电压VCI到第一电压VCOMH，Icha 2 = Cp（VCOMH-VCI）/ Deltat的充电电流。因此，Icha1消耗的功率是参考电压VCIxIcha1，Icha2消耗的功率是VCIxIcha 2×2。同时，从第一电压VCOMH向第二电压VCOML放电时的放电电流是从第一电压VCOMH到地电位GND的放电电流Idis 1 = Cp（VCOMH-GND）/ Deltat，和从地电位GND到第二电压VCOML的放电电流Idis 2 = Cp（GND-VCOML）/ Deltat。现在，如果以参考电压VCI消耗的功率转换，由于Idis 1表示放电到GND，因此功耗为零。然后，由于从地电位GND到第二电压VCOML，Idis2的放电电流的消耗功率为VCIxIdis 2。

2. 发明申请

US20070296665A1 Liquid crystal drive device 审中-公开
标题翻译：液晶驱动装置
公开(公告)号：US20070296665A1
公开(公告)日：2007-12-27
申请号：US11892619
申请日：2007-08-24
申请人： Yasushi Kawase , Takesada Akiba , Kazuya Endo , Goro Sakamaki
发明人： Yasushi Kawase , Takesada Akiba , Kazuya Endo , Goro Sakamaki
IPC分类号： G09G3/36
CPC分类号： G09G3/3655 , G09G3/3696 , G09G2330/021
摘要： By implementing reduction in power of common electrode voltages applied from a power source of a liquid crystal drive device to common electrode interconnects of a liquid crystal display panel, respectively, reduction in power consumption of the liquid crystal display panel as a whole is attained. A VCOM operation waveform in a charging process from a second voltage VCOML to a first voltage VCOMH shows that a charging current Icha represents the sum of a charging current from VCOML to a reference voltage VCI, Icha1=Cp (VCI−VCOML)/Δt, and a charging current from the reference voltage VCI to the first voltage VCOMH, Icha2=Cp (VCOMH−VCI)/Δt. Accordingly, power consumed by Icha1 is the reference voltage VCI×Icha1, and power consumed by Icha2 is VCI×Icha2×2. Meanwhile, a discharging current at a time of discharging from the first voltage VCOMH to the second voltage VCOML is the sum of a discharging current from the first voltage VCOMH to the ground potential GND, Idis1=Cp (VCOMH−GND)/Δt, and a discharging current from the ground potential GND to the second voltage VCOML, Idis2=Cp (GND−VCOML)/Δt. Now, if converted in terms of power consumed at the reference voltage VCI, since Idis1 represents discharge to GND, power consumption thereby becomes zero. Then, consumed power due to the discharging current from the ground potential GND to the second voltage VCOML, Idis2, is VCI×Idis2.
摘要翻译：通过将从液晶驱动装置的电源施加的共电极电压的功率分别实现为液晶显示面板的公共电极互连，能够实现液晶显示面板的整体功耗的降低。从第二电压VCOML到第一电压VCOMH的充电过程中的VCOM操作波形示出充电电流Icha表示从VCOML到参考电压VCI的充电电流之和Icha 1 = Cp（VCI-VCOML）/ Deltat ，以及从参考电压VCI到第一电压VCOMH，Icha 2 = Cp（VCOMH-VCI）/ Deltat的充电电流。因此，Icha1消耗的功率是参考电压VCIxIcha1，Icha2消耗的功率是VCIxIcha 2×2。同时，从第一电压VCOMH向第二电压VCOML放电时的放电电流是从第一电压VCOMH到地电位GND的放电电流Idis 1 = Cp（VCOMH-GND）/ Deltat，和从地电位GND到第二电压VCOML的放电电流Idis 2 = Cp（GND-VCOML）/ Deltat。现在，如果以参考电压VCI消耗的功率转换，由于Idis 1表示放电到GND，因此功耗为零。然后，由于从地电位GND到第二电压VCOML，Idis2的放电电流的消耗功率为VCIxIdis 2。

3. 发明申请

US20080042951A1 Liquid crystal drive device 审中-公开
标题翻译：液晶驱动装置
公开(公告)号：US20080042951A1
公开(公告)日：2008-02-21
申请号：US11892385
申请日：2007-08-22
申请人： Yasushi Kawasa , Takesada Akiba , Kazuya Endo , Goro Sakamaki
发明人： Yasushi Kawasa , Takesada Akiba , Kazuya Endo , Goro Sakamaki
IPC分类号： G09G3/36
CPC分类号： G09G3/3655 , G09G3/3696 , G09G2330/021
摘要： By implementing reduction in power of common electrode voltages applied from a power source of a liquid crystal drive device to common electrode interconnects of a liquid crystal display panel, respectively, reduction in power consumption of the liquid crystal display panel as a whole is attained. A VCOM operation waveform in a charging process from a second voltage VCOML to a first voltage VCOMH shows that a charging current Icha represents the sum of a charging current from VCOML to a reference voltage VCI, Icha1=Cp(VCI-VCOML)/Δt, and a charging current from the reference voltage VCI to the first voltage VCOMH, Icha2=Cp(VCOMH−VCI)/Δt. Accordingly, power consumed by Icha1 is the reference voltage VCI×Icha1, and power consumed by Icha2 is VCI×Icha2×2. Meanwhile, a discharging current at a time of discharging from the first voltage VCOMH to the second voltage VCOML is the sum of a discharging current from the first voltage VCOMH to the ground potential GND, Idis1=Cp(VCOMH−GND)/Δt, and a discharging current from the ground potential GND to the second voltage VCOML, Idis2=Cp(GND-VCOML)/Δt. Now, if converted in terms of power consumed at the reference voltage VCI, since Idis1 represents discharge to GND, power consumption thereby becomes zero. Then, consumed power due to the discharging current from the ground potential GND to the second voltage VCOML, Idis2, is VCI×Idis2.
摘要翻译：通过将从液晶驱动装置的电源施加的共电极电压的功率分别实现为液晶显示面板的公共电极互连，能够实现液晶显示面板的整体功耗的降低。从第二电压VCOML到第一电压VCOMH的充电过程中的VCOM操作波形示出充电电流Icha表示从VCOML到参考电压VCI的充电电流之和Icha 1 = Cp（VCI-VCOML）/ Deltat ，以及从参考电压VCI到第一电压VCOMH，Icha 2 = Cp（VCOMH-VCI）/ Deltat的充电电流。因此，Icha1消耗的功率是参考电压VCIxIcha1，Icha2消耗的功率是VCIxIcha 2×2。同时，从第一电压VCOMH向第二电压VCOML放电时的放电电流是从第一电压VCOMH到地电位GND的放电电流Idis 1 = Cp（VCOMH-GND）/ Deltat，和从地电位GND到第二电压VCOML的放电电流Idis 2 = Cp（GND-VCOML）/ Deltat。现在，如果以参考电压VCI消耗的功率转换，由于Idis 1表示放电到GND，因此功耗为零。然后，由于从地电位GND到第二电压VCOML，Idis2的放电电流的消耗功率为VCIxIdis 2。

4. 再颁专利

USRE38944E1 Semiconductor memory 有权
标题翻译：半导体存储器
公开(公告)号：USRE38944E1
公开(公告)日：2006-01-24
申请号：US09974962
申请日：2001-10-12
申请人： Tsugio Takahashi , Goro Kitsukawa , Takesada Akiba , Yasushi Kawase , Masayuki Nakamura
发明人： Tsugio Takahashi , Goro Kitsukawa , Takesada Akiba , Yasushi Kawase , Masayuki Nakamura
IPC分类号： G11C8/00
CPC分类号： H01L27/10805 , G11C7/10 , G11C11/408 , G11C11/4096 , G11C11/4097 , H01L27/105
摘要： A semiconductor memory such as a dynamic RAM having memory mats each divided into a plurality of units or sub-memory mats. Each sub-memory mat comprises: a memory array having sub-word lines and sub-bit lines intersecting orthogonally and dynamic memory cells located in lattice fashion at the intersection points between the intersecting sub-word and sub-bit lines; a sub-word line driver including unit sub-word line driving circuits corresponding to the sub-word lines; a sense amplifier including unit amplifier circuits and column selection switches corresponding to the sub-bit lines; and sub-common I/O lines to which designated sub-bit lines are connected selectively via the column selection switches. The sub-memory mats are arranged in lattice fashion. Above the sub-memory mats is a layer of: main word lines and columns selection signal lines intersecting orthogonally, the main word lines having a pitch that is an integer multiple of the pitch of the sub-word lines, the column selection signal lines having a pitch that is an integer multiple of the pitch of the sub-bit lines; and main common I/O lines to which designated sub-common I/O lines are connected selectively.
摘要翻译：具有各自被划分为多个单元或子存储器垫的存储器垫的动态RAM等半导体存储器。每个子存储器垫包括：存储器阵列，其具有在相交的子字和子位线之间的交叉点处以网格方式位于正交和动态存储器单元的子字线和子位线; 子字线驱动器，包括对应于子字线的单元子字线驱动电路; 感测放大器，包括对应于子位线的单位放大器电路和列选择开关; 以及经由列选择开关选择性地连接指定子位线的子公共I / O线。子存储垫以格子排列。子存储垫上面是：主字线和列选择信号线与正交相交的层，主字线具有作为子字线的间距的整数倍的间距，列选择信号线具有间距，是子位线的间距的整数倍; 以及选择性地连接指定的子公共I / O线的主要公共I / O线。

5. 发明授权

US6107869A Semiconductor integrated circuit 失效
公开(公告)号：US6107869A
公开(公告)日：2000-08-22
申请号：US96456
申请日：1998-06-11
申请人： Masashi Horiguchi , Yasushi Kawase , Takesada Akiba , Yoshinobu Nakagome , Kazuhiko Kajigaya
发明人： Masashi Horiguchi , Yasushi Kawase , Takesada Akiba , Yoshinobu Nakagome , Kazuhiko Kajigaya
IPC分类号： G11C11/41 , G11C5/14 , G11C8/08 , G11C11/401 , G11C11/407 , G11C11/409 , H01L21/3205 , H01L21/822 , H01L21/8242 , H01L23/52 , H01L27/04 , H01L27/108 , G05F3/02
CPC分类号： G11C8/08 , G11C5/14 , G11C5/147 , H01L2924/0002
摘要： It is possible to reduce the voltage drop on sub-power supply lines for reducing the subthreshold current and thereby prevent the operating speed of a logic circuit from lowering. Main power supply lines are arranged along one side of a rectangular region including a MOS logic circuit whose subthreshold current must be reduced, and a plurality of sub-power supply lines are arranged on the region in the direction perpendicular to the main power supply lines. A plurality of switching MOS transistors for selectively electrically connecting the sub-power supply lines to the main power supply line are dispersedly arranged with respect to the main power supply line. By dispersedly arranging the switching MOS transistors with respect to the main power supply line, it is possible to reduce the equivalent resistance of the sub-power supply lines compared to the case where switching MOS transistors are provided at one place.

6. 发明授权

US5966341A Semiconductor memory 失效
标题翻译：半导体存储器
公开(公告)号：US5966341A
公开(公告)日：1999-10-12
申请号：US982398
申请日：1997-12-02
申请人： Tsugio Takahashi , Goro Kitsukawa , Takesada Akiba , Yasushi Kawase , Masayuki Nakamura
发明人： Tsugio Takahashi , Goro Kitsukawa , Takesada Akiba , Yasushi Kawase , Masayuki Nakamura
IPC分类号： G11C11/401 , G11C7/10 , G11C11/407 , G11C11/408 , G11C11/409 , G11C11/4096 , G11C11/4097 , H01L21/8242 , H01L27/105 , H01L27/108 , G11C13/00
CPC分类号： H01L27/10805 , G11C11/408 , G11C11/4096 , G11C11/4097 , G11C7/10 , H01L27/105
摘要： A semiconductor memory such as a dynamic RAM having memory mats each divided into a plurality of units or sub-memory mats. Each sub-memory mat comprises: a memory array having sub-word lines and sub-bit lines intersecting orthogonally and dynamic memory cells located in lattice fashion at the intersection points between the intersecting sub-word and sub-bit lines; a sub-word line driver including unit sub-word line driving circuits corresponding to the sub-word lines; a sense amplifier including unit amplifier circuits and column selection switches corresponding to the sub-bit lines; and sub-common I/O lines to which designated sub-bit lines are connected selectively via the column selection switches. The sub-memory mats are arranged in lattice fashion. Above the sub-memory mats is a layer of: main word lines and column selection signal lines intersecting orthogonally, the main word lines having a pitch that is an integer multiple of the pitch of the sub-word lines, the column selection signal lines having a pitch that is an integer multiple of the pitch of the sub-bit lines; and main common I/O lines to which designated sub-common I/O lines are connected selectively.
摘要翻译：具有各自被划分为多个单元或子存储器垫的存储器垫的动态RAM等半导体存储器。每个子存储器垫包括：存储器阵列，其具有在相交的子字和子位线之间的交叉点处以网格方式位于正交和动态存储器单元的子字线和子位线; 子字线驱动器，包括对应于子字线的单元子字线驱动电路; 感测放大器，包括对应于子位线的单位放大器电路和列选择开关; 以及经由列选择开关选择性地连接指定子位线的子公共I / O线。子存储垫以格子排列。在子存储器衬垫之上是与主要字线和列选择信号线正交相交的层，主字线具有作为子字线的间距的整数倍的间距，列选择信号线具有间距，是子位线的间距的整数倍; 以及选择性地连接指定的子公共I / O线的主要公共I / O线。

7. 发明授权

US08345480B2 Semiconductor integrated circuit device for driving liquid crystal display 有权
标题翻译：用于驱动液晶显示器的半导体集成电路器件
公开(公告)号：US08345480B2
公开(公告)日：2013-01-01
申请号：US13305532
申请日：2011-11-28
申请人： Yasushi Kawase , Susumu Ishida , Takesada Akiba , Yasushi Nagata , Naoki Miyamoto , Kazuyoshi Shiba
发明人： Yasushi Kawase , Susumu Ishida , Takesada Akiba , Yasushi Nagata , Naoki Miyamoto , Kazuyoshi Shiba
IPC分类号： G11C11/34
CPC分类号： G09G3/3655 , G09G5/005 , G09G2310/08 , H01L27/0207 , H01L27/11521 , H01L27/11558 , H01L29/42324 , H01L29/42328 , H01L29/7885
摘要： The present invention realizes a semiconductor integrated circuit device for driving liquid crystal (liquid crystal control driver IC) capable of easily setting drive conditions and the like according to specifications of a liquid crystal display to be used. An electrically-programmable nonvolatile memory circuit (EPROM) or an electrically erasable and programmable nonvolatile memory circuit (EEPROM) is provided in a semiconductor integrated circuit device for driving a liquid crystal display, and setting information is stored in the memory circuit. The memory circuit is constructed by a normal device which can be formed in the same process as a semiconductor manufacturing process of forming devices of other circuits.
摘要翻译：本发明实现了一种用于驱动液晶（液晶控制驱动器IC）的半导体集成电路器件，其能够根据要使用的液晶显示器的规格容易地设置驱动条件等。在用于驱动液晶显示器的半导体集成电路器件中提供电可编程非易失性存储器电路（EPROM）或电可擦除和可编程的非易失性存储器电路（EEPROM），并将设置信息存储在存储器电路中。存储电路由与其他电路的形成器件的半导体制造工艺相同的工艺形成的普通器件构成。

8. 发明授权

US08089810B2 Semiconductor integrated circuit device for driving liquid crystal display 有权
标题翻译：用于驱动液晶显示器的半导体集成电路器件
公开(公告)号：US08089810B2
公开(公告)日：2012-01-03
申请号：US12890642
申请日：2010-09-25
申请人： Yasushi Kawase , Susumu Ishida , Takesada Akiba , Yasushi Nagata , Naoki Miyamoto , Kazuyoshi Shiba
发明人： Yasushi Kawase , Susumu Ishida , Takesada Akiba , Yasushi Nagata , Naoki Miyamoto , Kazuyoshi Shiba
IPC分类号： G11C11/34
CPC分类号： G09G3/3655 , G09G5/005 , G09G2310/08 , H01L27/0207 , H01L27/11521 , H01L27/11558 , H01L29/42324 , H01L29/42328 , H01L29/7885
摘要： The present invention realizes a semiconductor integrated circuit device for driving liquid crystal (liquid crystal control driver IC) capable of easily setting drive conditions and the like according to specifications of a liquid crystal display to be used. An electrically-programmable nonvolatile memory circuit (EPROM) or an electrically erasable and programmable nonvolatile memory circuit (EEPROM) is provided in a semiconductor integrated circuit device for driving a liquid crystal display, and setting information is stored in the memory circuit. The memory circuit is constructed by a normal device which can be formed in the same process as a semiconductor manufacturing process of forming devices of other circuits.
摘要翻译：本发明实现了一种用于驱动液晶（液晶控制驱动器IC）的半导体集成电路器件，其能够根据要使用的液晶显示器的规格容易地设定驱动条件等。在用于驱动液晶显示器的半导体集成电路器件中提供电可编程非易失性存储器电路（EPROM）或电可擦除和可编程的非易失性存储器电路（EEPROM），并将设置信息存储在存储器电路中。存储电路由与其他电路的形成器件的半导体制造工艺相同的工艺形成的普通器件构成。

9. 再颁专利

USRE42659E1 Large-capacity semiconductor memory with improved layout for sub-amplifiers to increase speed 有权
标题翻译：大容量半导体存储器，具有改进的子放大器布局，以提高速度
公开(公告)号：USRE42659E1
公开(公告)日：2011-08-30
申请号：US11759316
申请日：2007-06-07
申请人： Tsugio Takahashi , Goro Kitsukawa , Takesada Akiba , Yasushi Kawase , Masayuki Nakamura
发明人： Tsugio Takahashi , Goro Kitsukawa , Takesada Akiba , Yasushi Kawase , Masayuki Nakamura
IPC分类号： G11C8/00
CPC分类号： H01L27/10805 , G11C7/10 , G11C11/408 , G11C11/4096 , G11C11/4097 , H01L27/105
摘要： A semiconductor memory such as a dynamic RAM having memory mats each divided into a plurality of units or sub-memory mats. Each sub-memory mat comprises: a memory array having sub-word lines and sub-bit lines intersecting orthogonally and dynamic memory cells located in lattice fashion at the intersection points between the intersecting sub-word and sub-bit lines; a sub-word line driver including unit sub-word line driving circuits corresponding to the sub-word lines; a sense amplifier including unit amplifier circuits and column selection switches corresponding to the sub-bit lines; and sub-common I/O lines to which designated sub-bit lines are connected selectively via the column selection switches. The sub-memory mats are arranged in lattice fashion. Above the sub-memory mats is a layer of: main word lines and column selection signal lines intersecting orthogonally, the main word lines having a pitch that is an integer multiple of the pitch of the sub-word lines, the column selection signal lines having a pitch that is an integer multiple of the pitch of the sub-bit lines; and main common I/O lines to which designated sub-common I/O lines are connected selectively.
摘要翻译：具有各自被划分为多个单元或子存储器垫的存储器垫的动态RAM等半导体存储器。每个子存储器垫包括：存储器阵列，其具有在相交的子字和子位线之间的交叉点处以网格方式位于正交和动态存储器单元的子字线和子位线; 子字线驱动器，包括对应于子字线的单元子字线驱动电路; 感测放大器，包括对应于子位线的单位放大器电路和列选择开关; 以及经由列选择开关选择性地连接指定子位线的子公共I / O线。子存储垫以格子排列。在子存储器衬垫之上是与主要字线和列选择信号线正交相交的层，主字线具有作为子字线的间距的整数倍的间距，列选择信号线具有间距，是子位线的间距的整数倍; 以及指定的子公共I / O线选择性地连接的主要公共I / O。

10. 发明授权

US06747509B2 Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：US06747509B2
公开(公告)日：2004-06-08
申请号：US10045105
申请日：2002-01-15
申请人： Masashi Horiguchi , Yasushi Kawase , Takesada Akiba , Yoshinobu Nakagome , Kazuhiko Kajigaya
发明人： Masashi Horiguchi , Yasushi Kawase , Takesada Akiba , Yoshinobu Nakagome , Kazuhiko Kajigaya
IPC分类号： G05F110
CPC分类号： G11C8/08 , G11C5/14 , G11C5/147 , H01L2924/0002 , H01L2924/00
摘要： It is possible to reduce the voltage drop on sub-power supply lines for reducing the subthreshold current and thereby prevent the operating speed of a logic circuit from lowering. Main power supply lines are arranged along one side of a rectangular region including a MOS logic circuit whose subthreshold current must be reduced, and a plurality of sub-power supply lines are arranged on the region in the direction perpendicular to the main power supply lines. A plurality of switching MOS transistors for selectively electrically connecting the sub-power supply lines to the main power supply line are dispersedly arranged with respect to the main power supply line. By dispersedly arranging the switching MOS transistors with respect to the main power supply line, it is possible to reduce the equivalent resistance of the sub-power supply lines compared to the case where switching MOS transistors are provided at one place.
摘要翻译：可以减小副电源线上的电压降，以降低亚阈值电流，从而防止逻辑电路的工作速度降低。主电源线沿着包括其亚阈值电流必须减小的MOS逻辑电路的矩形区域的一侧布置，并且在垂直于主电源线的方向上的区域上布置多个子电源线。用于将副电源线选择性地电连接到主电源线的多个开关MOS晶体管相对于主电源线分散布置。通过相对于主电源线分散配置开关MOS晶体管，与在一个地方设置开关MOS晶体管的情况相比，可以降低副电源线的等效电阻。

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