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1. 发明授权

US08345480B2 Semiconductor integrated circuit device for driving liquid crystal display 有权
标题翻译：用于驱动液晶显示器的半导体集成电路器件
公开(公告)号：US08345480B2
公开(公告)日：2013-01-01
申请号：US13305532
申请日：2011-11-28
申请人： Yasushi Kawase , Susumu Ishida , Takesada Akiba , Yasushi Nagata , Naoki Miyamoto , Kazuyoshi Shiba
发明人： Yasushi Kawase , Susumu Ishida , Takesada Akiba , Yasushi Nagata , Naoki Miyamoto , Kazuyoshi Shiba
IPC分类号： G11C11/34
CPC分类号： G09G3/3655 , G09G5/005 , G09G2310/08 , H01L27/0207 , H01L27/11521 , H01L27/11558 , H01L29/42324 , H01L29/42328 , H01L29/7885
摘要： The present invention realizes a semiconductor integrated circuit device for driving liquid crystal (liquid crystal control driver IC) capable of easily setting drive conditions and the like according to specifications of a liquid crystal display to be used. An electrically-programmable nonvolatile memory circuit (EPROM) or an electrically erasable and programmable nonvolatile memory circuit (EEPROM) is provided in a semiconductor integrated circuit device for driving a liquid crystal display, and setting information is stored in the memory circuit. The memory circuit is constructed by a normal device which can be formed in the same process as a semiconductor manufacturing process of forming devices of other circuits.
摘要翻译：本发明实现了一种用于驱动液晶（液晶控制驱动器IC）的半导体集成电路器件，其能够根据要使用的液晶显示器的规格容易地设置驱动条件等。在用于驱动液晶显示器的半导体集成电路器件中提供电可编程非易失性存储器电路（EPROM）或电可擦除和可编程的非易失性存储器电路（EEPROM），并将设置信息存储在存储器电路中。存储电路由与其他电路的形成器件的半导体制造工艺相同的工艺形成的普通器件构成。

2. 发明授权

US08089810B2 Semiconductor integrated circuit device for driving liquid crystal display 有权
标题翻译：用于驱动液晶显示器的半导体集成电路器件
公开(公告)号：US08089810B2
公开(公告)日：2012-01-03
申请号：US12890642
申请日：2010-09-25
申请人： Yasushi Kawase , Susumu Ishida , Takesada Akiba , Yasushi Nagata , Naoki Miyamoto , Kazuyoshi Shiba
发明人： Yasushi Kawase , Susumu Ishida , Takesada Akiba , Yasushi Nagata , Naoki Miyamoto , Kazuyoshi Shiba
IPC分类号： G11C11/34
CPC分类号： G09G3/3655 , G09G5/005 , G09G2310/08 , H01L27/0207 , H01L27/11521 , H01L27/11558 , H01L29/42324 , H01L29/42328 , H01L29/7885
摘要： The present invention realizes a semiconductor integrated circuit device for driving liquid crystal (liquid crystal control driver IC) capable of easily setting drive conditions and the like according to specifications of a liquid crystal display to be used. An electrically-programmable nonvolatile memory circuit (EPROM) or an electrically erasable and programmable nonvolatile memory circuit (EEPROM) is provided in a semiconductor integrated circuit device for driving a liquid crystal display, and setting information is stored in the memory circuit. The memory circuit is constructed by a normal device which can be formed in the same process as a semiconductor manufacturing process of forming devices of other circuits.
摘要翻译：本发明实现了一种用于驱动液晶（液晶控制驱动器IC）的半导体集成电路器件，其能够根据要使用的液晶显示器的规格容易地设定驱动条件等。在用于驱动液晶显示器的半导体集成电路器件中提供电可编程非易失性存储器电路（EPROM）或电可擦除和可编程的非易失性存储器电路（EEPROM），并将设置信息存储在存储器电路中。存储电路由与其他电路的形成器件的半导体制造工艺相同的工艺形成的普通器件构成。

3. 发明申请

US20110147819A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20110147819A1
公开(公告)日：2011-06-23
申请号：US13034698
申请日：2011-02-24
申请人： KAZUYOSHI SHIBA , YASUSHI OKA
发明人： KAZUYOSHI SHIBA , YASUSHI OKA
IPC分类号： H01L29/788
CPC分类号： H01L27/11558 , G11C16/0441 , H01L27/0207 , H01L27/0629 , H01L27/105 , H01L27/11519 , H01L27/11521 , H01L27/11526
摘要： p-type wells are provided within an n-type embedded well of a semiconductor substrate lying in an area for forming a flash memory, in a state of being isolated from one another. A capacitance section, a data write/erase charge injection/discharge section and a data read MIS•FET are disposed in each of the p-type wells. The capacitance section is disposed between the data write/erase charge injection/discharge section and the data read MIS•FET. In the data write/erase charge injection/discharge section, writing and erasing of data by an FN tunnel current at a channel entire surface are performed.
摘要翻译： p型阱设置在位于形成闪存的区域中的半导体衬底的n型嵌入阱中，处于彼此隔离的状态。电容部分，数据写入/擦除电荷注入/放电部分和数据读取MIS·FET被设置在每个p型阱中。电容部分设置在数据写入/擦除电荷注入/放电部分和数据读取MIS•FET之间。在数据写入/擦除电荷注入/放电部分中，执行通道整个表面处的FN隧道电流的数据写入和擦除。

4. 发明授权

US07965563B2 Data line disturbance free memory block divided flash memory and microcomputer having flash memory therein 失效
标题翻译：数据线无干扰存储器块分割闪存和其中具有闪存的微型计算机
公开(公告)号：US07965563B2
公开(公告)日：2011-06-21
申请号：US12320679
申请日：2009-02-02
申请人： Kiyoshi Matsubara , Naoki Yashiki , Shiro Baba , Takashi Ito , Hirofumi Mukai , Masanao Sato , Masaaki Terasawa , Kenichi Kuroda , Kazuyoshi Shiba
发明人： Kiyoshi Matsubara , Naoki Yashiki , Shiro Baba , Takashi Ito , Hirofumi Mukai , Masanao Sato , Masaaki Terasawa , Kenichi Kuroda , Kazuyoshi Shiba
IPC分类号： G11C16/04
CPC分类号： H01L27/11526 , G06F9/445 , G06F15/7814 , G06F15/7821 , G11C7/1045 , G11C16/0416 , G11C16/102 , G11C16/105 , G11C16/12 , G11C16/16 , G11C16/26 , G11C16/30 , G11C16/3418 , G11C16/3427 , G11C16/3445 , G11C16/3459 , H01L27/105 , H01L27/115 , H01L27/11531 , H01L27/11546 , Y02D10/43
摘要： A semiconductor device having an electrically erasable and programmable nonvolatile memory, for example, a rewritable nonvolatile memory including memory cells arranged in rows and columns and disposed to facilitate both flash erasure as well as selective erasure of individual units of plural memory cells. The semiconductor device which functions as a microcomputer chip also has a processing unit and includes an input terminal for receiving an operation mode signal for switching the microcomputer between a first operation mode in which the flash memory is rewritten under control of a processing unit and a second operation mode in which the flash memory is rewritten under control of separate writing circuit externally connectable to the microcomputer.
摘要翻译：具有电可擦除和可编程非易失性存储器的半导体器件，例如，包括以行和列布置的存储器单元的可重写非易失性存储器，并且被设置为便于闪存擦除以及多个存储器单元的各个单元的选择性擦除。用作微计算机芯片的半导体器件还具有处理单元，并且包括：输入端子，用于在处理单元的控制下在闪速存储器被重写的第一操作模式和第二操作模式之间接收用于切换微型计算机的操作模式信号操作模式，其中在外部连接到微型计算机的分离的写入电路的控制下闪存被重写。

5. 发明申请

US20100025754A1 SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20100025754A1
公开(公告)日：2010-02-04
申请号：US12495957
申请日：2009-07-01
申请人： Kazuyoshi SHIBA
发明人： Kazuyoshi SHIBA
IPC分类号： H01L29/792 , H01L21/28
CPC分类号： H01L21/28282 , H01L27/11568 , H01L27/11573 , H01L29/4234
摘要： To improve characteristics of a semiconductor device having a nonvolatile memory.There is provided a semiconductor device having a nonvolatile memory cell that performs memory operations by transferring a charge to/from a charge storage film, wherein the nonvolatile memory cell includes a p well formed in a principal plane of a silicon substrate, and a memory gate electrode formed over the principal plane across the charge storage film, and wherein a memory channel region located beneath the charge storage film of the principal plane of the silicon substrate contains fluorine.
摘要翻译：为了改善具有非易失性存储器的半导体器件的特性。提供了一种具有非易失性存储单元的半导体器件，其通过向电荷存储膜转移电荷而进行存储操作，其中非易失性存储单元包括在硅衬底的主平面上形成的非易失性存储单元，以及存储栅电极形成在电荷储存膜上的主平面上，并且其中位于硅衬底的主平面的电荷存储膜下方的存储通道区域含有氟。

6. 发明授权

US07652917B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07652917B2
公开(公告)日：2010-01-26
申请号：US12260124
申请日：2008-10-29
申请人： Yasushi Oka , Kazuyoshi Shiba
发明人： Yasushi Oka , Kazuyoshi Shiba
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： H01L27/115 , G11C16/0433 , H01L27/11521 , H01L27/11558
摘要： In a data program/erase device of a nonvolatile memory cell, data are re-written by means of an FN tunnel current of an entire channel surface. In a buried n-well of a semiconductor substrate in a flash memory formation region, p wells are placed in the form isolated from each other. In each of the p wells, a capacitor portion, a capacitor portion for programming/erasing data and an MIS•FET for reading data are placed. In the capacitor portion for programming/erasing data, rewriting (programming and erasing) of data is performed by means of an FN tunnel current of an entire channel surface.
摘要翻译：在非易失性存储单元的数据编程/擦除装置中，通过整个通道表面的FN隧道电流重写数据。在闪速存储器形成区域中的半导体衬底的掩埋n阱中，p阱以彼此分离的形式放置。在每个p阱中，放置电容器部分，用于编程/擦除数据的电容器部分和用于读取数据的MIS.FET。在用于编程/擦除数据的电容器部分中，通过整个通道表面的FN隧道电流来执行数据的重写（编程和擦除）。

7. 发明授权

US07575950B2 Semiconductor device and a method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07575950B2
公开(公告)日：2009-08-18
申请号：US11339674
申请日：2006-01-26
申请人： Kazuyoshi Shiba
发明人： Kazuyoshi Shiba
IPC分类号： H01L21/00
CPC分类号： H01L23/585 , H01L24/48 , H01L27/0207 , H01L27/115 , H01L27/2436 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/1675 , H01L2224/48091 , H01L2224/48247 , H01L2924/00014 , H01L2924/01029 , H01L2924/01078 , H01L2924/04941 , H01L2924/1305 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor device having improved performance and improvement manufacturing yield is provided. After a semiconductor integrated circuit including a phase change memory and a nonvolatile memory other than a phase change memory is formed in a semiconductor substrate, an inspection step such as a probe inspection is performed. In accordance with the result of the inspection, data is stored in the nonvolatile memory other than a phase change memory. At this stage, the data is not stored in the phase change memory. Then, the semiconductor substrate is cut by dicing or the like into separate pieces corresponding to individual semiconductor chips. Each of the separate pieces of semiconductor chips is packaged.
摘要翻译：提供了具有改善的性能和提高制造产量的半导体器件。在半导体衬底中形成包括相变存储器和非相容变换存储器以外的非易失性存储器的半导体集成电路之后，进行检查检查等检查步骤。根据检查结果，将数据存储在除了相变存储器之外的非易失性存储器中。在这个阶段，数据不存储在相变存储器中。然后，通过切割等将半导体衬底切割成与各个半导体芯片对应的分离片。每个单独的半导体芯片被封装。

8. 发明申请

US20090093096A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20090093096A1
公开(公告)日：2009-04-09
申请号：US12330637
申请日：2008-12-09
申请人： KAZUYOSHI SHIBA
发明人： KAZUYOSHI SHIBA
IPC分类号： H01L21/8239 , H01L21/28 , H01L21/02 , H01L21/336
CPC分类号： H01L21/02164 , H01L21/0217 , H01L21/02274 , H01L21/3185 , H01L27/0629 , H01L27/105 , H01L27/1052 , H01L27/115 , H01L27/11526 , H01L27/11546 , H01L29/665 , H01L29/7833
摘要： To provide a nonvolatile memory having an excellent data holding property and a technique for manufacturing the memory, a polycrystalline silicon film 7 and an insulating film 8 are sequentially stacked on a gate insulating film 6, then the polycrystalline silicon film 7 and the insulating film 8 are patterned to form gate electrodes 7A, 7B, and then sidewall spacers 12 including a silicon oxide film are formed on sidewalls of the gate electrodes 7A, 7B. After that, a silicon nitride film 19 is deposited on a substrate 1 by a plasma enhanced CVD process so that the gate electrodes 7A, 7B are not directly contacted to the silicon nitride film 19.
摘要翻译：为了提供具有优异的数据保持特性的非易失性存储器和用于制造存储器的技术，多晶硅膜7和绝缘膜8依次层叠在栅绝缘膜6上，然后将多晶硅膜7和绝缘膜8 被图案化以形成栅电极7A，7B，然后在栅电极7A，7B的侧壁上形成包括氧化硅膜的侧壁间隔物12。之后，通过等离子体增强CVD工艺将氮化硅膜19沉积在衬底1上，使得栅电极7A，7B不直接接触氮化硅膜19。

9. 发明授权

US07505329B2 Data line disturbance free memory block divided flash memory and microcomputer having flash memory therein 失效
公开(公告)号：US07505329B2
公开(公告)日：2009-03-17
申请号：US11860762
申请日：2007-09-25
申请人： Kiyoshi Matsubara , Naoki Yashiki , Shiro Baba , Takashi Ito , Hirofumi Mukai , Masanao Sato , Masaaki Terasawa , Kenichi Kuroda , Kazuyoshi Shiba
发明人： Kiyoshi Matsubara , Naoki Yashiki , Shiro Baba , Takashi Ito , Hirofumi Mukai , Masanao Sato , Masaaki Terasawa , Kenichi Kuroda , Kazuyoshi Shiba
IPC分类号： G11C16/04
CPC分类号： H01L27/11526 , G06F9/445 , G06F15/7814 , G06F15/7821 , G11C7/1045 , G11C16/0416 , G11C16/102 , G11C16/105 , G11C16/12 , G11C16/16 , G11C16/26 , G11C16/30 , G11C16/3418 , G11C16/3427 , G11C16/3445 , G11C16/3459 , H01L27/105 , H01L27/115 , H01L27/11531 , H01L27/11546 , Y02D10/43
摘要： A semiconductor device having an electrically erasable and programmable nonvolatile memory, for example, a rewritable nonvolatile memory including memory cells arranged in rows and columns and disposed to facilitate both flash erasure as well as selective erasure of individual units of plural memory cells. The semiconductor device which functions as a microcomputer chip also has a processing unit and includes an input terminal for receiving an operation mode signal for switching the microcomputer between a first operation mode in which the flash memory is rewritten under control of a processing unit and a second operation mode in which the flash memory is rewritten under control of separate writing circuit externally connectable to the microcomputer.

10. 发明申请

US20080211001A1 SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20080211001A1
公开(公告)日：2008-09-04
申请号：US12013470
申请日：2008-01-13
申请人： Kazuyoshi Shiba , Hideyuki Yashima , Yasushi Oka
发明人： Kazuyoshi Shiba , Hideyuki Yashima , Yasushi Oka
IPC分类号： H01L27/06 , H01L21/28
CPC分类号： H01L27/105 , H01L27/1052 , H01L27/11526 , H01L27/11529 , H01L29/7833
摘要： Provided is a semiconductor device having, over the main surface of a semiconductor substrate, a main circuit region and a memory cell array of a flash memory. The memory cell array has a floating gate electrode for accumulating charges of data, while the main circuit region has a gate electrode of MIS•FET constituting the main circuit. In the main circuit region, an insulating film made of a silicon nitride film is formed to cover the gate electrode, whereby miniaturization of elements in the main circuit region is not impaired. The memory cell array has no such insulating film. This means that the upper surface of the floating gate electrode is not contiguous to the insulating film but is covered directly with an interlayer insulating film. According to such a constitution, leakage of electrons from the floating gate electrode of the memory cell array can be suppressed or prevented and the flash memory thus obtained has improved data retention characteristics.
摘要翻译：提供一种半导体器件，其在半导体衬底的主表面上具有闪存的主电路区域和存储单元阵列。存储单元阵列具有用于累积数据电荷的浮栅电极，而主电路区域具有构成主电路的MIS.FET的栅电极。在主电路区域中，形成由氮化硅膜构成的绝缘膜，以覆盖栅电极，从而不损害主电路区域中元件的小型化。存储单元阵列不具有这种绝缘膜。这意味着浮栅电极的上表面不与绝缘膜邻接，而是直接用层间绝缘膜覆盖。根据这种结构，可以抑制或防止电子从存储单元阵列的浮置栅电极泄漏，从而获得的闪速存储器具有改善的数据保持特性。

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