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1. 发明申请

US20130058170A1 NONVOLATILE SEMICONDUCTOR STORAGE DEVICE 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20130058170A1
公开(公告)日：2013-03-07
申请号：US13417719
申请日：2012-03-12
申请人： Yasuhiro SHIINO , Eietsu Takahashi , Yuji Takeuchi
发明人： Yasuhiro SHIINO , Eietsu Takahashi , Yuji Takeuchi
IPC分类号： G11C16/06
CPC分类号： G11C16/06 , G11C16/0483 , G11C16/344
摘要： A nonvolatile semiconductor storage device according to an embodiment includes a drive circuit. A voltage applied to a dummy wire connected to a first dummy cell adjacent to a memory string is defined as a first dummy wire voltage, a voltage applied to a selection wire connected to a first memory cell adjacent to the first dummy cell is defined as a first selection wire voltage, and a voltage applied to a selection wire connected to a second memory cell adjacent to the first memory cell is defined as a second selection wire voltage. When the second selection wire voltage is lower than the first dummy wire voltage in an erase operation, the drive circuit controls voltages so that a difference between the first dummy wire voltage and the second selection wire voltage is less than a difference between the first dummy wire voltage and the first selection wire voltage.
摘要翻译：根据实施例的非易失性半导体存储装置包括驱动电路。将连接到与存储器串相邻的第一虚拟单元的虚设电路施加的虚拟电路的电压定义为第一虚拟线电压，施加到与第一虚拟单元相邻的与第一存储单元相连的选择线的电压被定义为第一选择线电压和施加到连接到与第一存储器单元相邻的第二存储单元的选择线的电压被定义为第二选择线电压。当在擦除操作中第二选择线电压低于第一虚拟线电压时，驱动电路控制电压，使得第一虚拟线电压和第二选择线电压之间的差小于第一虚拟线电压和第一选择线电压。

2. 发明申请

US20120069672A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THEREOF 失效
标题翻译：非易失性半导体存储器件及其操作方法
公开(公告)号：US20120069672A1
公开(公告)日：2012-03-22
申请号：US13169414
申请日：2011-06-27
申请人： Yasuhiro SHIINO , Eietsu Takahashi , Yuji Takeuchi
发明人： Yasuhiro SHIINO , Eietsu Takahashi , Yuji Takeuchi
IPC分类号： G11C16/10
CPC分类号： G11C11/5628 , G11C16/10 , G11C16/3418
摘要： A nonvolatile semiconductor memory device in accordance with an embodiment includes a memory cell array. A control unit performs control of repeating a write operation, a write verify operation, and a step-up operation, the write operation being an operation to apply a write pulse voltage to a selected memory cell and an intermediate voltage to an unselected memory cell. The control unit controls the step-up operation such that, in a first period, the intermediate voltage is maintained at a constant value, and, in a second period, the intermediate voltage is raised by a certain value. The control unit controls the step-up operation such that the first period includes an operation to raise the write pulse voltage by a first step-up value, and the second period includes an operation to raise the write pulse voltage by a second step-up value smaller than the first step-up value.
摘要翻译：根据实施例的非易失性半导体存储器件包括存储单元阵列。控制单元执行重复写入操作，写入验证操作和升压操作的控制，写入操作是将写入脉冲电压施加到所选择的存储器单元和中间电压到未选择存储单元的操作。控制单元控制升压操作，使得在第一时间段中，中间电压保持在恒定值，并且在第二时间段内将中间电压升高一定值。控制单元控制升压操作，使得第一周期包括用于将写入脉冲电压升高第一升压值的操作，并且第二周期包括通过第二升压升高写入脉冲电压的操作值小于第一升压值。

3. 发明授权

US08737134B2 Nonvolatile semiconductor storage device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US08737134B2
公开(公告)日：2014-05-27
申请号：US13417719
申请日：2012-03-12
申请人： Yasuhiro Shiino , Eietsu Takahashi , Yuji Takeuchi
发明人： Yasuhiro Shiino , Eietsu Takahashi , Yuji Takeuchi
IPC分类号： G11C11/34
CPC分类号： G11C16/06 , G11C16/0483 , G11C16/344
摘要： A nonvolatile semiconductor storage device according to an embodiment includes a drive circuit. A voltage applied to a dummy wire connected to a first dummy cell adjacent to a memory string is defined as a first dummy wire voltage, a voltage applied to a selection wire connected to a first memory cell adjacent to the first dummy cell is defined as a first selection wire voltage, and a voltage applied to a selection wire connected to a second memory cell adjacent to the first memory cell is defined as a second selection wire voltage. When the second selection wire voltage is lower than the first dummy wire voltage in an erase operation, the drive circuit controls voltages so that a difference between the first dummy wire voltage and the second selection wire voltage is less than a difference between the first dummy wire voltage and the first selection wire voltage.
摘要翻译：根据实施例的非易失性半导体存储装置包括驱动电路。将连接到与存储器串相邻的第一虚拟单元的虚设电路施加的虚拟电路的电压定义为第一虚拟线电压，施加到与第一虚拟单元相邻的与第一存储单元相连的选择线的电压被定义为第一选择线电压和施加到连接到与第一存储器单元相邻的第二存储单元的选择线的电压被定义为第二选择线电压。当在擦除操作中第二选择线电压低于第一虚拟线电压时，驱动电路控制电压，使得第一虚拟线电压和第二选择线电压之间的差小于第一虚拟线电压和第一选择线电压。

4. 发明授权

US08422301B2 Nonvolatile semiconductor memory device and operating method thereof 失效
标题翻译：非易失性半导体存储器件及其操作方法
公开(公告)号：US08422301B2
公开(公告)日：2013-04-16
申请号：US13169414
申请日：2011-06-27
申请人： Yasuhiro Shiino , Eietsu Takahashi , Yuji Takeuchi
发明人： Yasuhiro Shiino , Eietsu Takahashi , Yuji Takeuchi
IPC分类号： G11C11/34
CPC分类号： G11C11/5628 , G11C16/10 , G11C16/3418
摘要： A nonvolatile semiconductor memory device in accordance with an embodiment includes a memory cell array. A control unit performs control of repeating a write operation, a write verify operation, and a step-up operation, the write operation being an operation to apply a write pulse voltage to a selected memory cell and an intermediate voltage to an unselected memory cell. The control unit controls the step-up operation such that, in a first period, the intermediate voltage is maintained at a constant value, and, in a second period, the intermediate voltage is raised by a certain value. The control unit controls the step-up operation such that the first period includes an operation to raise the write pulse voltage by a first step-up value, and the second period includes an operation to raise the write pulse voltage by a second step-up value smaller than the first step-up value.
摘要翻译：根据实施例的非易失性半导体存储器件包括存储单元阵列。控制单元执行重复写入操作，写入验证操作和升压操作的控制，写入操作是将写入脉冲电压施加到所选择的存储器单元和中间电压到未选择存储单元的操作。控制单元控制升压操作，使得在第一时间段中，中间电压保持在恒定值，并且在第二时间段内将中间电压升高一定值。控制单元控制升压操作，使得第一周期包括用于将写入脉冲电压升高第一升压值的操作，并且第二周期包括通过第二升压升高写入脉冲电压的操作值小于第一升压值。

5. 发明申请

US20110186921A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE HAVING ELEMENT ISOLATING REGION OF TRENCH TYPE 有权
标题翻译：具有元件分离区域的非挥发性半导体存储器件
公开(公告)号：US20110186921A1
公开(公告)日：2011-08-04
申请号：US13085884
申请日：2011-04-13
申请人： Michiharu MATSUI , Seiichi Mori , Riichiro Shirota , Yuji Takeuchi , Takeshi Kamigaichi
发明人： Michiharu MATSUI , Seiichi Mori , Riichiro Shirota , Yuji Takeuchi , Takeshi Kamigaichi
IPC分类号： H01L29/788
CPC分类号： H01L27/11526 , H01L21/76229 , H01L27/105 , H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11524 , H01L27/11529 , H01L27/11531 , H01L27/11543 , H01L29/7887
摘要： Disclosure is semiconductor device of a selective gate region, comprising a semiconductor layer, a first insulating film formed on the semiconductor layer, a first electrode layer formed on the first insulating layer, an element isolating region comprising an element isolating insulating film formed to extend through the first electrode layer and the first insulating film to reach an inner region of the semiconductor layer, the element isolating region isolating a element region and being self-aligned with the first electrode layer, a second insulating film formed on the first electrode layer and the element isolating region, an open portion exposing a surface of the first electrode layer being formed in the second insulating film, and a second electrode layer formed on the second insulating film and the exposed surface of the first electrode layer, the second electrode layer being electronically connected to the first electrode layer via the open portion.
摘要翻译：公开是选择性栅极区域的半导体器件，包括半导体层，形成在半导体层上的第一绝缘膜，形成在第一绝缘层上的第一电极层，元件隔离区域，其包括形成为延伸穿过的元件隔离绝缘膜所述第一电极层和所述第一绝缘膜到达所述半导体层的内部区域，所述元件隔离区域隔离元件区域并且与所述第一电极层自对准;第二绝缘膜，形成在所述第一电极层上，元件隔离区域，暴露在第二绝缘膜中形成的第一电极层的表面的开口部分和形成在第二绝缘膜和第一电极层的暴露表面上的第二电极层，第二电极层是电子经由开口部与第一电极层连接。

6. 发明授权

US07893477B2 Nonvolatile semiconductor memory 有权
公开(公告)号：US07893477B2
公开(公告)日：2011-02-22
申请号：US11829320
申请日：2007-07-27
申请人： Hiroshi Watanabe , Hiroshi Nakamura , Kazuhiro Shimizu , Seiichi Aritome , Toshitake Yaegashi , Yuji Takeuchi , Kenichi Imamiya , Ken Takeuchi , Hideko Oodaira
发明人： Hiroshi Watanabe , Hiroshi Nakamura , Kazuhiro Shimizu , Seiichi Aritome , Toshitake Yaegashi , Yuji Takeuchi , Kenichi Imamiya , Ken Takeuchi , Hideko Oodaira
IPC分类号： H01L27/108 , H01L29/73
CPC分类号： H01L27/11521 , G11C16/0483 , G11C16/10 , H01L27/105 , H01L27/115 , H01L27/11524 , H01L27/11526 , H01L27/11529
摘要： A select gate transistor has a select gate electrode composed of a first-level conductive layer and a second-level conductive layer. The first-level conductive layer has contact areas. The second-level conductive layer has its portions removed that are located above the contact areas. Two adjacent select gate electrodes that are adjacent to each other in the column direction are arranged such that the contact areas of one select gate electrode are not opposed to the contact areas of the other select gate electrode. One select gate electrode has its first- and second-level conductive layers removed in their portions that are opposed to the contact areas of the other select gate electrode.

7. 发明申请

US20110010402A1 DATA-DRIVEN DATABASE PROCESSOR 有权
标题翻译：数据驱动数据库处理器
公开(公告)号：US20110010402A1
公开(公告)日：2011-01-13
申请号：US12812016
申请日：2008-12-24
申请人： Ken Takeuchi , Yuji Takeuchi , Takahiro Yodo
发明人： Ken Takeuchi , Yuji Takeuchi , Takahiro Yodo
IPC分类号： G06F7/00
CPC分类号： G06F17/3051 , G06F17/30371 , G06F17/30595
摘要： Provided is a technique for a data-driven database which frees a user from having to be conscious of a sequence in which instructions of a program for accessing a database are described, an interrelation of data items, and the like, and from having to describe redundant instructions. A data-driven database processor includes: schema definition storage means 2 for storing a schema definition of a database 24; derived definition storage means 3 for storing a derived definition describing a cause-and-effect relationship that exists when a value of a given data item is derived from a value of another data item; derived definition processing means 26 for generating a trigger program 27 that makes a chain of changes to values of data items based on the cause-and-effect relationship described in the derived definition; and a database management system 23 for executing the trigger program 27 when a change is made to the other data item that affects the value of the given data item.
摘要翻译：提供了一种用于数据驱动数据库的技术，其释放用户不必意识到描述用于访问数据库的程序的指令，数据项的相关性等的序列，并且不必描述冗余指令。数据驱动数据库处理器包括：用于存储数据库24的模式定义的模式定义存储装置2; 派生定义存储装置3，用于存储描述当从另一数据项的值导出给定数据项的值时存在的因果关系的派生定义; 导出定义处理装置26，用于基于导出的定义中描述的因果关系，产生触发程序27，触发程序27使数据项的值变化链; 以及数据库管理系统23，用于当对影响给定数据项的值的其他数据项进行改变时，执行触发程序27。

8. 发明授权

US07595522B2 Nonvolatile semiconductor memory 有权
标题翻译：非易失性半导体存储器
公开(公告)号：US07595522B2
公开(公告)日：2009-09-29
申请号：US11565822
申请日：2006-12-01
申请人： Yuji Takeuchi
发明人： Yuji Takeuchi
IPC分类号： H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L29/42336 , H01L27/115 , H01L27/11521
摘要： According to the invention, there is provided a nonvolatile semiconductor memory having: a floating gate electrode formed on a gate insulating film on an element region isolated by an element isolation region on a semiconductor substrate; an inter-gate insulating film formed to cover a portion from an upper surface to a middle of a side surface of the floating gate electrode; and a control gate electrode formed on the floating gate electrode via the inter-gate insulating film, wherein a portion from the upper surface of the floating gate electrode to at least a middle of the portion of the side surface which is covered with the inter-gate insulating film has a tapered shape largely inclined to a direction perpendicular to a surface of the semiconductor substrate, compared to the other portion of the side surface.
摘要翻译：根据本发明，提供了一种非易失性半导体存储器，其具有：形成在由半导体衬底上的元件隔离区域隔离的元件区域上的栅极绝缘膜上的浮栅电极; 形成为覆盖从所述浮栅电极的侧面的上表面到中间的部分的栅极间绝缘膜; 以及通过所述栅极间绝缘膜形成在所述浮栅上的控制栅电极，其中，从所述浮栅电极的上表面到所述侧表面的所述部分的至少中间的部分，与侧面的其他部分相比，栅极绝缘膜具有大致倾斜于垂直于半导体衬底的表面的方向的锥形形状。

9. 发明授权

US07504294B2 Method of manufacturing an electrically erasable programmable read-only memory (EEPROM) 有权
标题翻译：制造电可擦除可编程只读存储器（EEPROM）的方法
公开(公告)号：US07504294B2
公开(公告)日：2009-03-17
申请号：US10881180
申请日：2004-07-01
申请人： Kikuko Sugimae , Hiroyuki Kutsukake , Masayuki Ichige , Michiharu Matsui , Yuji Takeuchi , Riichiro Shirota
发明人： Kikuko Sugimae , Hiroyuki Kutsukake , Masayuki Ichige , Michiharu Matsui , Yuji Takeuchi , Riichiro Shirota
IPC分类号： H01L21/8238
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/11529
摘要： A semiconductor device comprises a memory cell array portion and peripheral circuit portion, wherein a first insulation film including elements as main components other than nitrogen fills between the memory cell gate electrodes of the memory cell array portion, the first insulation film is formed as a liner on a sidewall of a peripheral gate electrode of the peripheral circuit portion simultaneously with the memory cell portion, and a second insulation film including nitrogen as the main component is formed on the sidewall of the peripheral gate electrode via the first insulation film, thus enabling not only the formation of the memory cell portion having high reliability, but also the formation of a peripheral circuit with good efficiency, simultaneously, and avoiding gate offset of a peripheral gate.
摘要翻译：半导体器件包括存储单元阵列部分和外围电路部分，其中包括作为除氮之外的主要成分的元素的第一绝缘膜填充在存储单元阵列部分的存储单元栅电极之间，第一绝缘膜形成为衬垫在周边电路部分的外围栅电极的侧壁上与存储单元部分同时，并且通过第一绝缘膜在外围栅电极的侧壁上形成包括氮作为主要成分的第二绝缘膜，从而不能仅形成具有高可靠性的存储单元部分，而且形成具有良好效率的周边电路，同时避免了外围栅极的栅极偏移。

10. 发明申请

US20080290396A1 SEMICONDUCTOR MEMORY 审中-公开
标题翻译：半导体存储器
公开(公告)号：US20080290396A1
公开(公告)日：2008-11-27
申请号：US12125546
申请日：2008-05-22
申请人： Yasuhiko MATSUNAGA , Yuji Takeuchi , Takashi Shigeoka
发明人： Yasuhiko MATSUNAGA , Yuji Takeuchi , Takashi Shigeoka
IPC分类号： H01L29/00
CPC分类号： H01L27/105 , H01L27/0207 , H01L27/11519 , H01L27/11526 , H01L27/11529
摘要： A semiconductor memory according to an aspect of this invention comprises a semiconductor substrate which includes a memory cell array region and an interconnect line region adjoining the memory cell array region, memory cells which are provided in the memory cell array region, contact plugs which are provided in the interconnect line region, and control gate lines which are provided so as to extend from the interconnect line region to the memory cell array region and which connect the contact plugs with the memory cells, wherein the control gate lines provided in the memory cell array region include metal silicide and the control gate lines provided in the interconnect line region include no metal silicide at any part of the interconnect line region.
摘要翻译：根据本发明的一个方面的半导体存储器包括半导体衬底，其包括存储单元阵列区域和与存储单元阵列区域相邻的互连线区域，设置在存储单元阵列区域中的存储单元，提供的接触插头以及控制栅极线，其设置为从互连线区域延伸到存储单元阵列区域，并将接触插头与存储器单元连接，其中设置在存储单元阵列中的控制栅极线区域包括金属硅化物，并且设置在互连线区域中的控制栅极线在互连线区域的任何部分不包括金属硅化物。

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