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1. 发明申请

US20120069672A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THEREOF 失效
标题翻译：非易失性半导体存储器件及其操作方法
公开(公告)号：US20120069672A1
公开(公告)日：2012-03-22
申请号：US13169414
申请日：2011-06-27
申请人： Yasuhiro SHIINO , Eietsu Takahashi , Yuji Takeuchi
发明人： Yasuhiro SHIINO , Eietsu Takahashi , Yuji Takeuchi
IPC分类号： G11C16/10
CPC分类号： G11C11/5628 , G11C16/10 , G11C16/3418
摘要： A nonvolatile semiconductor memory device in accordance with an embodiment includes a memory cell array. A control unit performs control of repeating a write operation, a write verify operation, and a step-up operation, the write operation being an operation to apply a write pulse voltage to a selected memory cell and an intermediate voltage to an unselected memory cell. The control unit controls the step-up operation such that, in a first period, the intermediate voltage is maintained at a constant value, and, in a second period, the intermediate voltage is raised by a certain value. The control unit controls the step-up operation such that the first period includes an operation to raise the write pulse voltage by a first step-up value, and the second period includes an operation to raise the write pulse voltage by a second step-up value smaller than the first step-up value.
摘要翻译：根据实施例的非易失性半导体存储器件包括存储单元阵列。控制单元执行重复写入操作，写入验证操作和升压操作的控制，写入操作是将写入脉冲电压施加到所选择的存储器单元和中间电压到未选择存储单元的操作。控制单元控制升压操作，使得在第一时间段中，中间电压保持在恒定值，并且在第二时间段内将中间电压升高一定值。控制单元控制升压操作，使得第一周期包括用于将写入脉冲电压升高第一升压值的操作，并且第二周期包括通过第二升压升高写入脉冲电压的操作值小于第一升压值。

2. 发明授权

US08737134B2 Nonvolatile semiconductor storage device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US08737134B2
公开(公告)日：2014-05-27
申请号：US13417719
申请日：2012-03-12
申请人： Yasuhiro Shiino , Eietsu Takahashi , Yuji Takeuchi
发明人： Yasuhiro Shiino , Eietsu Takahashi , Yuji Takeuchi
IPC分类号： G11C11/34
CPC分类号： G11C16/06 , G11C16/0483 , G11C16/344
摘要： A nonvolatile semiconductor storage device according to an embodiment includes a drive circuit. A voltage applied to a dummy wire connected to a first dummy cell adjacent to a memory string is defined as a first dummy wire voltage, a voltage applied to a selection wire connected to a first memory cell adjacent to the first dummy cell is defined as a first selection wire voltage, and a voltage applied to a selection wire connected to a second memory cell adjacent to the first memory cell is defined as a second selection wire voltage. When the second selection wire voltage is lower than the first dummy wire voltage in an erase operation, the drive circuit controls voltages so that a difference between the first dummy wire voltage and the second selection wire voltage is less than a difference between the first dummy wire voltage and the first selection wire voltage.
摘要翻译：根据实施例的非易失性半导体存储装置包括驱动电路。将连接到与存储器串相邻的第一虚拟单元的虚设电路施加的虚拟电路的电压定义为第一虚拟线电压，施加到与第一虚拟单元相邻的与第一存储单元相连的选择线的电压被定义为第一选择线电压和施加到连接到与第一存储器单元相邻的第二存储单元的选择线的电压被定义为第二选择线电压。当在擦除操作中第二选择线电压低于第一虚拟线电压时，驱动电路控制电压，使得第一虚拟线电压和第二选择线电压之间的差小于第一虚拟线电压和第一选择线电压。

3. 发明申请

US20130058170A1 NONVOLATILE SEMICONDUCTOR STORAGE DEVICE 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20130058170A1
公开(公告)日：2013-03-07
申请号：US13417719
申请日：2012-03-12
申请人： Yasuhiro SHIINO , Eietsu Takahashi , Yuji Takeuchi
发明人： Yasuhiro SHIINO , Eietsu Takahashi , Yuji Takeuchi
IPC分类号： G11C16/06
CPC分类号： G11C16/06 , G11C16/0483 , G11C16/344
摘要： A nonvolatile semiconductor storage device according to an embodiment includes a drive circuit. A voltage applied to a dummy wire connected to a first dummy cell adjacent to a memory string is defined as a first dummy wire voltage, a voltage applied to a selection wire connected to a first memory cell adjacent to the first dummy cell is defined as a first selection wire voltage, and a voltage applied to a selection wire connected to a second memory cell adjacent to the first memory cell is defined as a second selection wire voltage. When the second selection wire voltage is lower than the first dummy wire voltage in an erase operation, the drive circuit controls voltages so that a difference between the first dummy wire voltage and the second selection wire voltage is less than a difference between the first dummy wire voltage and the first selection wire voltage.
摘要翻译：根据实施例的非易失性半导体存储装置包括驱动电路。将连接到与存储器串相邻的第一虚拟单元的虚设电路施加的虚拟电路的电压定义为第一虚拟线电压，施加到与第一虚拟单元相邻的与第一存储单元相连的选择线的电压被定义为第一选择线电压和施加到连接到与第一存储器单元相邻的第二存储单元的选择线的电压被定义为第二选择线电压。当在擦除操作中第二选择线电压低于第一虚拟线电压时，驱动电路控制电压，使得第一虚拟线电压和第二选择线电压之间的差小于第一虚拟线电压和第一选择线电压。

4. 发明授权

US08422301B2 Nonvolatile semiconductor memory device and operating method thereof 失效
标题翻译：非易失性半导体存储器件及其操作方法
公开(公告)号：US08422301B2
公开(公告)日：2013-04-16
申请号：US13169414
申请日：2011-06-27
申请人： Yasuhiro Shiino , Eietsu Takahashi , Yuji Takeuchi
发明人： Yasuhiro Shiino , Eietsu Takahashi , Yuji Takeuchi
IPC分类号： G11C11/34
CPC分类号： G11C11/5628 , G11C16/10 , G11C16/3418
摘要： A nonvolatile semiconductor memory device in accordance with an embodiment includes a memory cell array. A control unit performs control of repeating a write operation, a write verify operation, and a step-up operation, the write operation being an operation to apply a write pulse voltage to a selected memory cell and an intermediate voltage to an unselected memory cell. The control unit controls the step-up operation such that, in a first period, the intermediate voltage is maintained at a constant value, and, in a second period, the intermediate voltage is raised by a certain value. The control unit controls the step-up operation such that the first period includes an operation to raise the write pulse voltage by a first step-up value, and the second period includes an operation to raise the write pulse voltage by a second step-up value smaller than the first step-up value.
摘要翻译：根据实施例的非易失性半导体存储器件包括存储单元阵列。控制单元执行重复写入操作，写入验证操作和升压操作的控制，写入操作是将写入脉冲电压施加到所选择的存储器单元和中间电压到未选择存储单元的操作。控制单元控制升压操作，使得在第一时间段中，中间电压保持在恒定值，并且在第二时间段内将中间电压升高一定值。控制单元控制升压操作，使得第一周期包括用于将写入脉冲电压升高第一升压值的操作，并且第二周期包括通过第二升压升高写入脉冲电压的操作值小于第一升压值。

5. 发明授权

US08446777B2 Non-volatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US08446777B2
公开(公告)日：2013-05-21
申请号：US13280618
申请日：2011-10-25
申请人： Koki Ueno , Eietsu Takahashi , Shigefumi Irieda , Yasuhiro Shiino , Manabu Sakaniwa
发明人： Koki Ueno , Eietsu Takahashi , Shigefumi Irieda , Yasuhiro Shiino , Manabu Sakaniwa
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C16/14 , G11C11/5635 , G11C16/16 , G11C16/344
摘要： A non-volatile semiconductor memory device according to one embodiment of the present invention includes a memory cell array and a control unit. The control unit is configured to control a repeat of an erase operation, an erase verify operation, and a step-up operation. The control unit is configured to perform a soft-programming operation of setting the memory cells from an over-erased state to a first threshold voltage distribution state when, in a series of erase operations, the number of erase voltage applications is more than a first number and less than a second number (the first number
摘要翻译：根据本发明的一个实施例的非易失性半导体存储器件包括存储单元阵列和控制单元。控制单元被配置为控制擦除操作，擦除验证操作和升压操作的重复。控制单元被配置为执行将存储单元从过擦除状态设置为第一阈值电压分布状态的软编程操作，当在一系列擦除操作中擦除电压应用的数量多于第一阈值电压分配状态时，数字和小于第二个数字（第一个数字<第二个数字）。当擦除电压应用的数量等于或小于第一数量或等于或大于第二数量时，控制单元被配置为不执行软编程操作。

6. 发明申请

US20130058171A1 SEMICONDUCTOR STORAGE DEVICE 有权
标题翻译：半导体存储设备
公开(公告)号：US20130058171A1
公开(公告)日：2013-03-07
申请号：US13425121
申请日：2012-03-20
申请人： Yasuhiro SHIINO , Shigefumi Irieda , Kenri Nakai , Eietsu Takahashi , Koki Ueno
发明人： Yasuhiro SHIINO , Shigefumi Irieda , Kenri Nakai , Eietsu Takahashi , Koki Ueno
IPC分类号： G11C16/06 , G11C16/04
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/06 , G11C16/3418
摘要： A semiconductor storage device has a plurality of memory cells each having a control gate that are formed on a well. The semiconductor storage device has a control circuit that applies a voltage to the well and the control gates.In an erase operation of the memory cell, the control circuit applies a first pulse wave of a first erasure voltage that rises stepwise to the well and then applies a second pulse wave of a second erasure voltage to the well.
摘要翻译：半导体存储装置具有多个存储单元，每个存储单元具有形成在阱上的控制栅极。半导体存储装置具有向井和控制门施加电压的控制电路。在存储单元的擦除操作中，控制电路施加第一擦除电压的第一脉冲波，该第一脉冲波逐步上升到阱，然后向阱施加第二擦除电压的第二脉冲波。

7. 发明授权

US08149631B2 Non-volatile semiconductor storage device 有权
标题翻译：非易失性半导体存储装置
公开(公告)号：US08149631B2
公开(公告)日：2012-04-03
申请号：US12796964
申请日：2010-06-09
申请人： Yasuhiro Shiino , Daisuke Kouno , Shigefumi Irieda , Kenri Nakai , Eietsu Takahashi
发明人： Yasuhiro Shiino , Daisuke Kouno , Shigefumi Irieda , Kenri Nakai , Eietsu Takahashi
IPC分类号： G11C11/34
CPC分类号： G11C16/14 , G11C16/16 , G11C16/3445
摘要： For data erase from an electrically erasable and programmable non-volatile memory cell, the following operations are performed: an erase operation to apply an erase pulse voltage to a memory cell for data erase, an erase verify operation to verify whether data erase is completed, and a step-up operation to increase the erase pulse voltage by a certain step-up voltage if data erase is not completed. A control unit controls voltages so that at least a first erase pulse voltage initially generated in the erase operation has a longer rise time than that of a second erase pulse voltage generated subsequent to the first erase pulse voltage.
摘要翻译：对于从电可擦除和可编程的非易失性存储单元进行的数据擦除，执行以下操作：将擦除脉冲电压施加到用于数据擦除的存储单元的擦除操作，擦除验证操作以验证数据擦除是否完成，以及如果数据擦除未完成，则通过一定的升压电压来增加擦除脉冲电压的升压操作。控制单元控制电压，使得在擦除操作中最初产生的至少第一擦除脉冲电压具有比在第一擦除脉冲电压之后产生的第二擦除脉冲电压更长的上升时间。

8. 发明授权

US08873298B2 Nonvolatile semiconductor storage device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US08873298B2
公开(公告)日：2014-10-28
申请号：US13451843
申请日：2012-04-20
申请人： Yasuhiro Shiino , Eietsu Takahashi
发明人： Yasuhiro Shiino , Eietsu Takahashi
IPC分类号： G11C11/34 , G11C11/56 , G11C16/34 , G11C16/04
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/3459 , G11C2211/5621 , G11C2211/5644
摘要： A nonvolatile semiconductor storage device according to an embodiment includes: a memory cell array including plural memory cells; and a control circuit that repeatedly performs a write loop including a program operation and a verify operation in data write performed to the memory cell, the verify operation including a preverify step to check whether a threshold voltage of the memory cell transitions to a preverify voltage, and a real verify step to check whether the threshold voltage of the memory cell transitions to the real verify voltage, the write loop including one or at least two verify operations corresponding to pieces of the data, the control circuit performing the write loop in which the preverify step of the verify operation corresponding to a first data is omitted after obtaining a first condition.
摘要翻译：根据实施例的非易失性半导体存储装置包括：包括多个存储单元的存储单元阵列; 以及控制电路，其重复执行包括对所述存储单元执行的数据写入中的编程操作和验证操作的写入循环，所述验证操作包括预验证步骤，用于检查所述存储器单元的阈值电压是否转换到预验电压，以及真实验证步骤，用于检查存储器单元的阈值电压是否转换到真实验证电压，写入循环包括与数据片段相对应的一个或至少两个验证操作，该控制电路执行写入循环，其中在获得第一条件之后，省略对与第一数据相对应的验证操作的预验证步骤。

9. 发明授权

US08385126B2 Nonvolatile semiconductor memory device 有权
公开(公告)号：US08385126B2
公开(公告)日：2013-02-26
申请号：US13246004
申请日：2011-09-27
申请人： Yasuhiro Shiino , Eietsu Takahashi , Koki Ueno
发明人： Yasuhiro Shiino , Eietsu Takahashi , Koki Ueno
IPC分类号： G11C16/04
CPC分类号： G11C16/26 , G11C11/5628 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/14 , G11C16/3427 , G11C16/349
摘要： A nonvolatile semiconductor memory device according to one embodiment of the present invention includes: a memory cell array and a control circuit. The control circuit executes a first reading operation and a second reading operation. The first reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between a control gate electrode and source of the selected memory cell to a first value. The second reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between the control gate electrode and source of the selected memory cell to a second value lower than the first value. When executing the second reading operation, the control circuit keeps a voltage of the control gate electrode of the selected memory cell to 0 or a positive value.

10. 发明授权

US08953371B2 Semiconductor storage device 有权
标题翻译：半导体存储设备
公开(公告)号：US08953371B2
公开(公告)日：2015-02-10
申请号：US13425121
申请日：2012-03-20
申请人： Yasuhiro Shiino , Shigefumi Irieda , Kenri Nakai , Eietsu Takahashi , Koki Ueno
发明人： Yasuhiro Shiino , Shigefumi Irieda , Kenri Nakai , Eietsu Takahashi , Koki Ueno
IPC分类号： G11C11/34 , G11C11/56 , G11C16/06 , G11C16/04 , G11C16/34
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/06 , G11C16/3418
摘要： A semiconductor storage device has a plurality of memory cells each having a control gate that are formed on a well. The semiconductor storage device has a control circuit that applies a voltage to the well and the control gates.In an erase operation of the memory cell, the control circuit applies a first pulse wave of a first erasure voltage that rises stepwise to the well and then applies a second pulse wave of a second erasure voltage to the well.
摘要翻译：半导体存储装置具有多个存储单元，每个存储单元具有形成在阱上的控制栅极。半导体存储装置具有向井和控制门施加电压的控制电路。在存储单元的擦除操作中，控制电路施加第一擦除电压的第一脉冲波，该第一脉冲波逐步上升到阱，然后向阱施加第二擦除电压的第二脉冲波。

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