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1. 发明授权

US5288948A Structure of a semiconductor chip having a conductive layer 失效
标题翻译：具有导电层的半导体芯片的结构
公开(公告)号：US5288948A
公开(公告)日：1994-02-22
申请号：US778881
申请日：1991-12-26
申请人： Yasuhiro Fukuda , Tetsuhiko Sugahara , Norio Hirashita , Mitsuhiro Matsuo , Minoru Saito , Masayuki Kobayakawa , Fumitaka Yokoyama
发明人： Yasuhiro Fukuda , Tetsuhiko Sugahara , Norio Hirashita , Mitsuhiro Matsuo , Minoru Saito , Masayuki Kobayakawa , Fumitaka Yokoyama
IPC分类号： H01L23/528 , H05K1/00
CPC分类号： H01L23/5286 , H01L2924/0002
摘要： In order to prevent the occurrence of corrosion due to the sliding of a relatively wide aluminum conductive layer (12) such as a power source conductive layer or a ground conductive layer, formed on a semiconductor substrate (11), breakage of a lower conductive layer due to the sliding of an upper aluminum conductive layer (12) in case of a multilayer interconnection, and the creation of voids in the lower aluminum conductive layer due to the moisture beneath the relatively wide metal conductive layer in case of a multi layer interconnection etc., the conductive layer structure is constructed so that the conductive layer (12) relatively great in width is divided into several conductive layer portions and so that the width of each of the divided conductive layer portions is in a range of 10 .mu.m to 40 .mu.m.
摘要翻译： PCT No.PCT / JP90 / 00424 Sec。 371 1991年12月26日第 102（e）日期1991年12月26日PCT 1990年3月29日PCT PCT。出版物WO91 / 0061600 日期为1991年1月10日。为了防止由形成在半导体基板（11）上的诸如电源导体层或接地导电层的相对宽的铝导电层（12）滑动引起的腐蚀，在多层互连的情况下由于上部铝导电层（12）的滑动导致的下部导电层的破损，以及由于相对较宽的金属导电层下面的水分导致的下部铝导电层中的空隙的产生多层互连的情况等，导电层结构被构造为使得宽度相对较大的导电层（12）被分成几个导电层部分，并且使得每个分离的导电层部分的宽度为范围10（我）m到40（我）m。

2. 发明授权

US07479682B2 Structure of a field effect transistor having metallic silicide and manufacturing method thereof 有权
标题翻译：具有金属硅化物的场效应晶体管的结构及其制造方法
公开(公告)号：US07479682B2
公开(公告)日：2009-01-20
申请号：US11711746
申请日：2007-02-28
申请人： Norio Hirashita , Takashi Ichimori
发明人： Norio Hirashita , Takashi Ichimori
IPC分类号： H01L29/772
CPC分类号： H01L29/665 , H01L29/458 , H01L29/78609 , H01L2924/0002 , H01L2924/00
摘要： A field effect transistor having metallic silicide layers is formed in a semiconductor layer on an insulating layer of an SOI substrate. The metallic silicide layers are composed of refractory metal and silicon. The metallic silicide layers extend to bottom surfaces of source and drain regions. A ratio of the metal to the silicon in the metallic silicide layers is X to Y. A ratio of the metal to the silicon of metallic silicide having the lowest resistance among stoichiometric metallic silicides is X0 to Y0. X, Y, X0 and Y0 satisfy the following inequality: (X/Y)>(X0/Y0).
摘要翻译：具有金属硅化物层的场效应晶体管形成在SOI衬底的绝缘层上的半导体层中。金属硅化物层由难熔金属和硅组成。金属硅化物层延伸到源区和漏区的底表面。金属硅化物层中的金属与硅的比例为X〜Y。化学计量金属硅化物中具有最低电阻的金属硅化物的金属与硅的比例为X 0〜Y 0。 X，Y，X0和Y0满足以下不等式：（X / Y）>（X0 / Y0）。

3. 发明授权

US07244996B2 Structure of a field effect transistor having metallic silicide and manufacturing method thereof 有权
标题翻译：具有金属硅化物的场效应晶体管的结构及其制造方法
公开(公告)号：US07244996B2
公开(公告)日：2007-07-17
申请号：US09825973
申请日：2001-04-05
申请人： Norio Hirashita , Takashi Ichimori
发明人： Norio Hirashita , Takashi Ichimori
IPC分类号： H01L29/76
CPC分类号： H01L29/665 , H01L29/458 , H01L29/78609 , H01L2924/0002 , H01L2924/00
摘要： A field effect transistor having metallic silicide layers is formed in a semiconductor layer on an insulating layer of an SOI substrate. The metallic silicide layers are composed of refractory metal and silicon. The metallic silicide layers extend to bottom surfaces of a source and a drain regions. A ratio of the metal to the silicon in the metallic silicide layers is X to Y. A ratio of the metal to the silicon of metallic silicide having the lowest resistance among stoichiometaric metallic silicides is X0 to Y0. X, Y, X0 and Y0 satisfy the following inequity: (X/Y)>(X0/Y0).
摘要翻译：具有金属硅化物层的场效应晶体管形成在SOI衬底的绝缘层上的半导体层中。金属硅化物层由难熔金属和硅组成。金属硅化物层延伸到源极和漏极区域的底表面。金属硅化物层中的金属与硅的比例为X至Y.化学计量金属硅化物中具有最低电阻的金属硅化物的金属与硅的比例为X 0至Y 0。（X / Y）>（X 0 / Y 0）满足以下不等式：X，Y，X 0，Y 0。

4. 发明授权

US07199030B2 Method of manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US07199030B2
公开(公告)日：2007-04-03
申请号：US10446078
申请日：2003-05-28
申请人： Satoshi Ikeda , Yutaka Kamata , Ikuo Kurachi , Norio Hirashita
发明人： Satoshi Ikeda , Yutaka Kamata , Ikuo Kurachi , Norio Hirashita
IPC分类号： H01L21/425 , H01L21/265
CPC分类号： H01L29/6659 , H01L21/2652 , H01L21/324 , H01L29/7842
摘要： An impurity is ion-implanted with a silicon nitride film formed on a silicon substrate as a mask film to form a source/drain layer of a MOS transistor. Heat treatment for activating the impurity is done as it is without removing the silicon nitride film to thereby produce heat treatment-based stress between the silicon nitride film and the silicon substrate.
摘要翻译：用在硅衬底上形成的氮化硅膜作为掩模膜离子注入杂质以形成MOS晶体管的源极/漏极层。用于激活杂质的热处理是按照原样进行的，而不去除氮化硅膜，从而在氮化硅膜和硅衬底之间产生基于热处理的应力。

5. 发明申请

US20060145271A1 Semiconductor device having low parasitic resistance and small junction leakage characteristic 审中-公开
标题翻译：具有低寄生电阻和小结漏电特性的半导体器件
公开(公告)号：US20060145271A1
公开(公告)日：2006-07-06
申请号：US11367575
申请日：2006-03-06
申请人： Takashi Ichimori , Norio Hirashita
发明人： Takashi Ichimori , Norio Hirashita
IPC分类号： H01L29/76
CPC分类号： H01L29/66772 , H01L29/458 , H01L29/665
摘要： A semiconductor device includes diffusion layers formed in a SOI layer under a side-wall, a channel formed between the diffusion layers, silicide layers sandwiching the diffusion layers wherein interface junctions between the diffusion layers and the silicide layers are (111) silicon planes.
摘要翻译：半导体器件包括形成在侧壁下的SOI层中的扩散层，形成在扩散层之间的沟道，夹着扩散层的硅化物层，其中扩散层和硅化物层之间的界面接合为（111）硅平面。

6. 发明申请

US20110223724A1 Semiconductor device having low parasitic resistance and small junction leakage characteristic and method of manufacturing the same 审中-公开
标题翻译：具有低寄生电阻和小结漏电特性的半导体器件及其制造方法
公开(公告)号：US20110223724A1
公开(公告)日：2011-09-15
申请号：US13067214
申请日：2011-05-17
申请人： Takashi Ichimori , Norio Hirashita
发明人： Takashi Ichimori , Norio Hirashita
IPC分类号： H01L21/336
CPC分类号： H01L29/66772 , H01L29/458 , H01L29/665
摘要： A semiconductor device includes diffusion layers formed in a SOI layer under a side-wall, a channel formed between the diffusion layers, silicide layers sandwiching the diffusion layers wherein interface junctions between the diffusion layers and the silicide layers are (111) silicon planes.
摘要翻译：半导体器件包括形成在侧壁下的SOI层中的扩散层，形成在扩散层之间的沟道，夹着扩散层的硅化物层，其中扩散层和硅化物层之间的界面接合为（111）硅平面。

7. 发明授权

US07759228B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07759228B2
公开(公告)日：2010-07-20
申请号：US11449687
申请日：2006-06-09
申请人： Naoharu Sugiyama , Norio Hirashita , Tsutomu Tezuka
发明人： Naoharu Sugiyama , Norio Hirashita , Tsutomu Tezuka
IPC分类号： H01L21/84 , H01L21/324 , H01L21/20
CPC分类号： H01L29/78687 , H01L29/045
摘要： A method of manufacturing a semiconductor device. In the method, a substrate is prepared, which includes a buried oxide film and a SiGe layer formed on the buried oxide film. Then, heat treatment is performed on the substrate at a temperature equal to or lower than a first temperature, to form a protective oxide film on a surface of the SiGe layer. Next, the substrate having the protective oxide film is heated in a non-oxidizing atmosphere to a second temperature higher than the first temperature. Further, heat treatment is performed on the substrate thus heated, in an oxidizing atmosphere at a temperature equal to or higher than the second temperature, to form oxide the SiGe layer, make the SiGe layer thinner and increasing Ge concentration in the SiGe layer, thus forming a SiGe layer having the increased Ge concentration.
摘要翻译：一种制造半导体器件的方法。在该方法中，制备了包括掩埋氧化物膜和形成在掩埋氧化膜上的SiGe层的衬底。然后，在等于或低于第一温度的温度下在基板上进行热处理，以在SiGe层的表面上形成保护氧化膜。接着，将具有保护氧化膜的基板在非氧化性气氛中加热至高于第一温度的第二温度。此外，在等于或高于第二温度的氧化气氛中对如此加热的基板进行热处理，以氧化SiGe层，使SiGe层更薄并增加SiGe层中的Ge浓度，从而形成具有增加的Ge浓度的SiGe层。

8. 发明授权

US06197601B1 Method of correcting temperature of semiconductor substrate 失效
标题翻译：校正半导体衬底温度的方法
公开(公告)号：US06197601B1
公开(公告)日：2001-03-06
申请号：US09427085
申请日：1999-10-26
申请人： Norio Hirashita
发明人： Norio Hirashita
IPC分类号： H01L2100
CPC分类号： H01L22/26 , H01L22/12
摘要： In a semiconductor manufacturing apparatus, a semiconductor substrate ion-implanted with an ion species is heated and thereby raised in temperature under vacuum. At this time, a partial pressure of a gas released from the semiconductor substrate is measured by a quadrupole mass spectrometer. Further, a change in partial pressure with time is observed and compared with a pre-measured release characteristic, whereby the temperature of the semiconductor substrate is corrected.
摘要翻译：在半导体制造装置中，离子注入离子种的半导体衬底被加热，从而在真空下升高温度。此时，通过四极质谱仪测量从半导体衬底释放的气体的分压。此外，观察到分压随时间的变化，并与预先测定的释放特性进行比较，由此校正半导体衬底的温度。

9. 发明授权

US06861322B2 Method of manufacturing a semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US06861322B2
公开(公告)日：2005-03-01
申请号：US10154825
申请日：2002-05-28
申请人： Norio Hirashita , Takashi Ichimori , Toshiyuki Nakamura
发明人： Norio Hirashita , Takashi Ichimori , Toshiyuki Nakamura
IPC分类号： H01L27/08 , H01L21/265 , H01L21/324 , H01L21/336 , H01L21/8238 , H01L21/84 , H01L27/092 , H01L27/10 , H01L27/12 , H01L29/45 , H01L29/786
CPC分类号： H01L29/66757 , H01L21/26513 , H01L21/324 , H01L21/84 , H01L27/1203 , H01L29/458
摘要： A heat treatment for diffusing impurity ions implanted into a silicon layer is performed at a heat treatment temperature which is less than an aggregation temperature of the silicon layer. A thermal aggregation of the silicon layer can be inhibited, thereby reducing a silicon deficiency of the silicon layer.
摘要翻译：在散热杂质离子注入硅层的热处理是在比硅层的聚集温度小的热处理温度下进行的。可以抑制硅层的热聚集，从而减少硅层的硅缺陷。

10. 发明授权

US06750088B2 SOI MOS field effect transistor and manufacturing method therefor 失效
标题翻译： SOI MOS场效应晶体管及其制造方法
公开(公告)号：US06750088B2
公开(公告)日：2004-06-15
申请号：US10342191
申请日：2003-01-15
申请人： Norio Hirashita , Takashi Ichimori
发明人： Norio Hirashita , Takashi Ichimori
IPC分类号： H01L21336
CPC分类号： H01L27/1203 , H01L21/84 , H01L29/458 , H01L29/78612 , H01L29/78618
摘要： A device isolation region made up of a silicon oxide film, which is perfectly isolated up to the direction of the thickness of an SOI silicon layer, and an activation region of the SOI silicon layer, whose only ends are locally thinned, are formed on an SOI substrate. A source diffusion layer and a drain diffusion layer of a MOS field effect transistor in the activation region are provided so that according to the silicidization of the SOI silicon layer subsequent to the formation of a high melting-point metal, a Schottky junction is formed only at each end of the activation region and a PN junction is formed at a portion other than each end thereof.
摘要翻译：由氧化硅膜构成的器件隔离区域，其被完全隔离到SOI硅层的厚度方向，SOI层的局部变薄的SOI硅层的激活区域形成在 SOI衬底。提供激活区域中的MOS场效应晶体管的源极扩散层和漏极扩散层，使得根据形成高熔点金属后的SOI硅层的硅化，只形成肖特基结在激活区域的每个端部处，并且在其每个端部以外的部分处形成PN结。

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