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1. 发明授权

US4264968A Basic circuit for electronic timepieces 失效
标题翻译：电子钟表基本电路
公开(公告)号：US4264968A
公开(公告)日：1981-04-28
申请号：US864714
申请日：1977-12-27
申请人： Yasoji Suzuki , Fuminari Tanaka , Yasushi Sato
发明人： Yasoji Suzuki , Fuminari Tanaka , Yasushi Sato
IPC分类号： G01R19/00 , G04G3/02 , G04G9/00 , G04G99/00 , G04C3/00
CPC分类号： G04G99/00 , G04G3/022
摘要： There is provided an electronic timepiece basic circuit comprising a pulse generating circuit for generating 1 Hz pulses, a first terminal group having a plurality of terminals including a terminal connected to the output terminal of the pulse generating circuit, a second terminal group having terminals to be connected to the terminals of the first terminal group, respectively, 10 scale counters coupled with the second terminal group, 6 scale counters connected to the 10 scale counters, a display unit, and a decoder which is coupled with the 10 scale counters and the 6 scale counters and decodes the contents of the 10 and 6 scale counters and delivers the decoded contents to the display unit. The first and second terminal groups are properly coupled to each other. The combination of the 10 scale counters and the 6 scale counters is properly modified so as to form a 12, 24, or 60 scale counter, as necessary.
摘要翻译：提供了一种电子钟表基本电路，包括用于产生1Hz脉冲的脉冲发生电路，具有包括连接到脉冲发生电路的输出端的端子的多个端子的第一端子组，具有端子的第二端子组分别连接到第一终端组的终端，与第二终端组耦合的10个比例计数器，连接到10个比例计数器的6个比例计数器，显示单元和与10个比例计数器耦合的解码器，6 缩放计数器并解码10和6比例计数器的内容，并将解码的内容传送到显示单元。第一和第二端子组彼此适当地联接。 10个刻度计数器和6个刻度计数器的组合被适当修改，以便根据需要形成12个，24个或60个刻度计数器。

2. 发明授权

US4404663A Integrated circuit 失效
标题翻译：集成电路
公开(公告)号：US4404663A
公开(公告)日：1983-09-13
申请号：US234438
申请日：1981-02-13
申请人： Yukihiro Saeki , Fuminari Tanaka , Yasoji Suzuki
发明人： Yukihiro Saeki , Fuminari Tanaka , Yasoji Suzuki
IPC分类号： G06F1/18 , G06F3/00 , G11C5/06 , G11C7/10 , G11C7/00
CPC分类号： G11C5/063 , G11C7/10 , G11C7/1006
摘要： An integrated circuit wherein a gate circuit is provided on a bus line mounted on a semiconductor substrate. The gate circuit is used to separate an unused circuit block from other circuit blocks which are connected to a bus line through an input-output circuit for high speed data transmission, thereby reducing a parasitic capacity which might be imparted to the bus line by the separated circuit block. The input-output circuit is formed of a clocked inverter. The gate circuit is formed of a C.multidot.MOS transmission gate. The input-output circuit and gate circuit are so connected that where the gate of the inverter is opened, then the C.multidot.MOS transmission gate is closed; and where the gate of the inverter is closed, then the C.multidot.MOS transmission gate is opened.
摘要翻译：一种集成电路，其中门电路设置在安装在半导体衬底上的总线上。门电路用于将未使用的电路块与通过用于高速数据传输的输入 - 输出电路连接到总线的其它电路块分离，从而减少可能通过分离的总线赋予总线的寄生电容电路块。输入输出电路由时钟反相器构成。门电路由CxMOS传输门形成。输入输出电路和门电路如此连接，使逆变器的门打开，则CxMOS传输门关闭; 并且逆变器的门关闭，则CxMOS传输门打开。

3. 发明授权

US4821084A Insulated gate type field effect transistor 失效
标题翻译：绝缘栅型场效应晶体管
公开(公告)号：US4821084A
公开(公告)日：1989-04-11
申请号：US5668
申请日：1987-01-21
申请人： Masanori Kinugasa , Fuminari Tanaka , Hiroshi Shigehara , Hirokata Ohta
发明人： Masanori Kinugasa , Fuminari Tanaka , Hiroshi Shigehara , Hirokata Ohta
IPC分类号： H01L29/78 , H01L23/528 , H01L27/118 , H01L29/417 , H01L29/423 , H01L29/94 , H01L27/10
CPC分类号： H01L23/528 , H01L27/11898 , H01L29/41758 , H01L2924/0002
摘要： Extension directions of source electrode layer and a drain electrode are parallel to rows or columns of an array of alternately arranged source regions and drain regions, thereby forming widths of source and drain electrode layers wider than those of a conventional transistor to obtain a large mutual conductance.
摘要翻译：源极电极层和漏电极的延伸方向平行于交替排列的源极区域和漏极区域的阵列的行或列，从而形成比常规晶体管宽的源极和漏极电极层的宽度以获得大的互导。

4. 发明授权

US5128567A Output circuit of semiconductor integrated circuit with reduced power source line noise 失效
标题翻译：具有减少电源线噪声的半导体集成电路的输出电路
公开(公告)号：US5128567A
公开(公告)日：1992-07-07
申请号：US345259
申请日：1989-05-01
申请人： Fuminari Tanaka , Satoshi Nonaka
发明人： Fuminari Tanaka , Satoshi Nonaka
IPC分类号： H01L29/43 , H03K17/00 , H03K17/16 , H03K19/003 , H03K19/0175
CPC分类号： H01L29/435 , H03K17/164 , H03K19/00361 , H03K2217/0036
摘要： An output circuit of a semiconductor integrated circuit includes a plurality of output transistors having different current driving abilities for a load, and a plurality of signal delay means for delaying signals for driving each of the output transistors by different delay times, wherein the current driving ability of that one of the plurality of output transistors which is driven by the delay signal of one of the signal delay means which has a first delay time is set to be larger than the current driving ability of that one of the plurality of output transistors which is driven by the delay signal of one of the signal delay means which has a second delay time shorter than the first delay time.

5. 发明授权

US4701877A Highspeed parallel adder with clocked switching circuits 失效
标题翻译：具有时钟开关电路的高速并行加法器
公开(公告)号：US4701877A
公开(公告)日：1987-10-20
申请号：US675303
申请日：1984-11-27
申请人： Masayuki Sahoda , Fuminari Tanaka , Tetsuya Iida
发明人： Masayuki Sahoda , Fuminari Tanaka , Tetsuya Iida
IPC分类号： G06F7/505 , G06F7/50 , G06F7/502 , G06F7/506
CPC分类号： G06F7/502 , G06F2207/3876
摘要： In a parallel adder circuit, first and second full adders each having an addend input terminal, an augend input terminal, a sum output terminal, a carry input terminal, and a carry output terminal are alternately connected such that the carry output terminal of the preceding full adder is directly connected to the carry input terminal of the succeeding full adder. In order to shorten the carry propagation delay time, the first full adder is arranged to receive an inverted carry signal (FALSE) from the preceding stage and to provide a carry signal (TRUE) to the succeeding stage, while the second full adder is arranged to receive a carry signal (TRUE) from the preceding stage and to provide an inverted carry signal (FALSE) to the succeeding stage.
摘要翻译：在并行加法器电路中，交替地连接第一和第二全加法器，每个加法器具有加数输入端，加法输入端，和输出端，进位输入端和进位输出端，使得前面的进位输出端全加器直接连接到后续全加器的进位输入端。为了缩短进位传播延迟时间，第一全加器被布置为从前一级接收反向进位信号（FALSE），并且向后级提供进位信号（TRUE），而第二全加器布置从前级接收进位信号（TRUE），并向后级提供反转进位信号（FALSE）。

6. 发明授权

US4890016A Output circuit for CMOS integrated circuit with pre-buffer to reduce distortion of output signal 失效
标题翻译：输出电路用于具有预缓冲器的CMOS集成电路，以减少输出信号的失真
公开(公告)号：US4890016A
公开(公告)日：1989-12-26
申请号：US197979
申请日：1988-05-24
申请人： Fuminari Tanaka , Satoshi Nonaka
发明人： Fuminari Tanaka , Satoshi Nonaka
IPC分类号： H03K17/16 , H03K17/687 , H03K19/003 , H03K19/0175
CPC分类号： H03K19/00361 , H03K19/00392
摘要： An output circuit includes a plurality of output buffer circuits and a plurality of pre-buffer circuits connected to drive the output buffer circuits. Some of the pre-buffer circuits are each constituted by P- and N-channel MOS transistors having channel widths or channel lengths which are large enough to drive the output buffer circuits, and the remaining pre-buffer circuits are each constituted by P- and N-channel MOS transistors whose channel widths and channel lengths are so determined as to set the current driving ability thereof sufficiently smaller than that of the corresponding output buffer circuits.
摘要翻译：输出电路包括多个输出缓冲电路和连接以驱动输出缓冲电路的多个预缓冲器电路。一些预缓冲电路各自由具有足够大的驱动输出缓冲电路的沟道宽度或沟道长度的P-沟道MOS晶体管和N沟道MOS晶体管构成，其余的预缓冲电路各自由P-和其通道宽度和沟道长度被确定为将其电流驱动能力设定得足够小于对应的输出缓冲电路的电流驱动能力的N沟道MOS晶体管。

7. 发明授权

US4669121A Speech synthesizing apparatus 失效
标题翻译：语音合成装置
公开(公告)号：US4669121A
公开(公告)日：1987-05-26
申请号：US526798
申请日：1983-08-26
申请人： Hiroshi Shigehara , Fuminari Tanaka
发明人： Hiroshi Shigehara , Fuminari Tanaka
IPC分类号： G10L13/00 , G10L13/04 , G10L5/00
CPC分类号： G10L13/047
摘要： A speech synthesizing apparatus has a first memory storing a plurality of phrase data each including speech data, an address designating circuit for designating an address of the first memory, a second memory for storing synthesizing condition data, and a synthesizer for synthesizing a speech signal based on speech data from the first memory in accordance with the synthesizing condition data stored in the second memory. Each phrase data stored in the first memory also includes the corresponding synthesizing condition data. When each phrase data is read out from the first memory, the synthesizing condition data is first read out and is stored in the second memory, and then the speech data is read out and is supplied to the synthesizer.
摘要翻译：语音合成装置具有第一存储器，其存储包括语音数据的多个短语数据，用于指定第一存储器的地址的地址指定电路，用于存储合成条件数据的第二存储器和用于合成基于语音信号的合成器根据存储在第二存储器中的合成条件数据，从第一存储器输入语音数据。存储在第一存储器中的每个短语数据还包括相应的合成条件数据。当从第一存储器中读出每个短语数据时，首先读出合成条件数据并将其存储在第二存储器中，然后将语音数据读出并提供给合成器。

8. 发明授权

US4599522A Analog switch circuit having output offset compensation circuit 失效
标题翻译：模拟开关电路具有输出偏移补偿电路
公开(公告)号：US4599522A
公开(公告)日：1986-07-08
申请号：US552791
申请日：1983-11-17
申请人： Kenji Matsuo , Fuminari Tanaka
发明人： Kenji Matsuo , Fuminari Tanaka
IPC分类号： H03K17/06 , H03K17/16 , H03K17/687
CPC分类号： H03K17/687 , H03K17/06 , H03K17/162 , H03K17/6872
摘要： An analog switch circuit which is provided with a transmission gate consisting of a first n channel MOS transistor and a first p channel MOS transistor, which transistors are connected in parallel, wherein the output terminal of said transmission gate is connected to a second n channel MOS transistor and a second p channel MOS transistor, which transistors are supplied with an output voltage Vout from the transmission gate, and wherein mirror capacitances C.sub.mP12, C.sub.mP13, C.sub.mN12, C.sub.mN13 are provided at the output terminal of the transmission gate to offset a difference between the mirror capacitance C.sub.mN11 of the first n channel MOS transistor and the mirror capacitance C.sub.mP11 of the first p channel MOS transistor.
摘要翻译：一种模拟开关电路，其设置有由第一n沟道MOS晶体管和第一p沟道MOS晶体管组成的传输门，该晶体管并联连接，其中所述传输门的输出端连接到第二n沟道MOS 晶体管和第二p沟道MOS晶体管，这些晶体管被提供有来自传输栅极的输出电压Vout，并且其中反射镜电容CmP12，CmP13，CmN12，CmN13设置在传输门的输出端，以抵消第一n沟道MOS晶体管的反射镜电容CmN11和第一p沟道MOS晶体管的反射镜电容CmP11。

9. 发明授权

US5034629A Output control circuit for reducing through current in CMOS output buffer 失效
标题翻译：用于减少CMOS输出缓冲器中的直流电流的输出控制电路
公开(公告)号：US5034629A
公开(公告)日：1991-07-23
申请号：US552855
申请日：1990-07-16
申请人： Masanori Kinugasa , Fuminari Tanaka , Satoshi Nonaka , Munenobu Kida
发明人： Masanori Kinugasa , Fuminari Tanaka , Satoshi Nonaka , Munenobu Kida
IPC分类号： H03K17/16 , G11C11/409 , H03K19/003 , H03K19/0185 , H03K19/094 , H03K19/0948
CPC分类号： H03K19/00361 , H03K19/09429 , H03K19/0948
摘要： In an output circuit for use in a semiconductor IC comprising a CMOS transistors constituting an output buffer, a transfer gate of CMOS structure is connected between the gates of the CMOS transistors as a resistive element. The transfer gate reduces the changes in the gate potentials of output transistors, which occur when logic inputs are supplied to the gates of the output control transistors. Hence, the deformation of the output waveform, which has resulted from the through currents flowing through the output transistors, is minimized.

10. 发明授权

US4924339A Input protecting circuit in use with a MOS semiconductor device 失效
标题翻译： MOS半导体器件使用的输入保护电路
公开(公告)号：US4924339A
公开(公告)日：1990-05-08
申请号：US291476
申请日：1988-12-28
申请人： Shigeru Atsumi , Toru Yoshida , Yasuo Kawahara , Fuminari Tanaka
发明人： Shigeru Atsumi , Toru Yoshida , Yasuo Kawahara , Fuminari Tanaka
IPC分类号： H01L29/78 , H01L21/8234 , H01L27/02 , H01L27/088 , H02H9/04
CPC分类号： H01L27/0251
摘要： A bipolar transistor for clamping an excess input potential is provided near an input pad. A signal from the input pad is supplied through a wire to the gate of a MOS transistor in the input stage. A diode is provided near the gate of the MOS transistor. The diode absorbs a potential oscillation generated in the wire near the gate of the transistor, which is due to action of an inductance involved in the wire.

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