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1. 发明授权

US07675118B2 Semiconductor structure with enhanced performance using a simplified dual stress liner configuration 失效
标题翻译：使用简化的双重应力衬垫配置提高性能的半导体结构
公开(公告)号：US07675118B2
公开(公告)日：2010-03-09
申请号：US11468958
申请日：2006-08-31
申请人： Dureseti Chidambarrao , Yaocheng Liu , William K. Henson
发明人： Dureseti Chidambarrao , Yaocheng Liu , William K. Henson
IPC分类号： H01L27/12
CPC分类号： H01L21/28097 , H01L21/7624 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L27/1203 , H01L29/045 , H01L29/4908 , H01L29/4975 , H01L29/665 , H01L29/66545 , H01L29/7843
摘要： A semiconductor structure including an nFET having a fully silicided gate electrode wherein a new dual stress liner configuration is used to enhance the stress in the channel region that lies beneath the gate electrode is provided. The new dual stress liner configuration includes a first stress liner that has an upper surface that is substantially planar with an upper surface of a fully silicided gate electrode of the nFET. In accordance with the present invention, the first stress liner is not present atop the nFET including the fully silicided gate electrode. Instead, the first stress liner of the present invention partially wraps around, i.e., surrounds the sides of, the nFET with the fully silicided gate electrode. A second stress liner having an opposite polarity as that of the first stress liner (i.e., of an opposite stress type) is located on the upper surface of the first stress liner as well as atop the nFET that contains the fully silicided FET. In accordance with the present invention, the first stress liner is a tensile stress liner and the second stress liner is a compressive stress liner.
摘要翻译：提供了包括具有完全硅化栅电极的nFET的半导体结构，其中使用新的双应力衬垫配置来增强位于栅电极下方的沟道区中的应力。新的双应力衬垫构造包括第一应力衬垫，其具有与nFET的完全硅化栅电极的上表面基本上平面的上表面。根据本发明，第一应力衬垫不存在于包括全硅化物栅电极的nFET顶部。相反，本发明的第一应力衬垫部分地包裹着nFET的侧面，即用完全硅化的栅电极包围nFET。具有与第一应力衬垫相反极性（即相反应力类型）的第二应力衬垫位于第一应力衬垫的上表面上以及位于包含完全硅化FET的nFET顶上。根据本发明，第一应力衬垫是拉伸应力衬垫，第二应力衬垫是压应力衬垫。

2. 发明授权

US07485519B2 After gate fabrication of field effect transistor having tensile and compressive regions 失效
标题翻译：栅极制造具有拉伸和压缩区域的场效应晶体管
公开(公告)号：US07485519B2
公开(公告)日：2009-02-03
申请号：US11693786
申请日：2007-03-30
申请人： Dureseti Chidambarrao , William K. Henson , Yaocheng Liu
发明人： Dureseti Chidambarrao , William K. Henson , Yaocheng Liu
IPC分类号： H01L21/8238
CPC分类号： H01L29/66628 , H01L21/84 , H01L29/1083 , H01L29/66772 , H01L29/7842 , H01L29/7843 , H01L29/7848 , H01L29/7849 , H01L29/78654
摘要： A field effect transistor (“FET”) is formed to include a stress in a channel region of an active semiconductor region of an SOI substrate. A gate is formed to overlie the active semiconductor region, after which a sacrificial stressed layer is formed which overlies the gate and the active semiconductor region. Then, the SOI substrate is heated to cause a flowable dielectric material in a buried dielectric layer of the SOI substrate to soften and reflow. As a result of the reflowing, the sacrificial stressed layer induces stress in a channel region of the active semiconductor region underlying the gate. A source region and a drain region are formed in the active semiconductor region, desirably after removing the sacrificial stressed layer.
摘要翻译：形成场效应晶体管（“FET”）以在SOI衬底的有源半导体区域的沟道区域中包括应力。形成栅极覆盖有源半导体区域，之后形成覆盖在栅极和有源半导体区域上的牺牲应力层。然后，加热SOI衬底，使SOI衬底的埋入介质层中的可流动介电材料软化和回流。作为回流的结果，牺牲应力层在栅极下方的有源半导体区域的沟道区域中引起应力。源极区域和漏极区域形成在有源半导体区域中，理想地在除去牺牲应力层之后。

3. 发明申请

US20080258234A1 SEMICONDUCTOR STRUCTURE FOR LOW PARASITIC GATE CAPACITANCE 有权
标题翻译：低隔离栅电容的半导体结构
公开(公告)号：US20080258234A1
公开(公告)日：2008-10-23
申请号：US11738666
申请日：2007-04-23
申请人： William K. Henson , Paul Chung-Muh Chang , Dureseti Chidambarrao , Ricardo A. Donaton , Yaocheng Liu , Shreesh Narasimha , Amanda L. Tessier
发明人： William K. Henson , Paul Chung-Muh Chang , Dureseti Chidambarrao , Ricardo A. Donaton , Yaocheng Liu , Shreesh Narasimha , Amanda L. Tessier
IPC分类号： H01L21/285 , H01L21/336
CPC分类号： H01L21/823807 , H01L21/28097 , H01L21/76814 , H01L21/7682 , H01L21/76832 , H01L21/76844 , H01L21/823864 , H01L29/4975 , H01L29/517 , H01L29/66545 , H01L29/7843
摘要： A semiconductor structure provides lower parasitic capacitance between the gate electrode and contact vias while providing substantially the same level of stress applied by a nitride liner as conventional MOSFETs by reducing the height of the gate electrode and maintaining substantially the same height for the gate spacer. The nitride liner contacts only the outer sidewalls of the gate spacer, while not contacting inner sidewalls, or only a small area of the inner sidewalls of the gate spacer, therefore applying substantially the same level of stress to the channel of the MOSFET as conventional MOSFETs. The volume surrounded by the gate spacer and located above the gate electrode is either filled with a low-k dielectric material or occupied by a cavity having a dielectric constant of substantially 1.0. The reduced height of the gate electrode and the low-k dielectric gate filler or the cavity reduces the parasitic capacitance.
摘要翻译：半导体结构在栅电极和接触通孔之间提供较低的寄生电容，同时通过降低栅极电极的高度并保持与栅极间隔件基本上相同的高度，提供与常规MOSFET相同的氮化物衬垫施加的基本相同的应力水平。氮化物衬垫仅接触栅极间隔物的外侧壁，而不接触内侧壁，或者仅接触栅极隔离物的内侧壁的小面积，因此与常规MOSFET相比施加与MOSFET的通道基本相同的应力水平。由栅极间隔物围绕并位于栅极电极上方的体积填充有低k电介质材料或由具有基本上1.0的介电常数的空腔占据。栅电极和低k电介质栅极填充物或空腔的降低的高度减小了寄生电容。

4. 发明申请

US20080191281A1 STRESSED SOI FET HAVING TENSILE AND COMPRESSIVE DEVICE REGIONS 失效
标题翻译：具有拉伸和压缩设备区域的应力SOI FET
公开(公告)号：US20080191281A1
公开(公告)日：2008-08-14
申请号：US11673716
申请日：2007-02-12
申请人： Dureseti Chidambarrao , William K. Henson , Yaocheng Liu
发明人： Dureseti Chidambarrao , William K. Henson , Yaocheng Liu
IPC分类号： H01L27/12 , H01L21/84
CPC分类号： H01L29/78603 , H01L21/84 , H01L27/1203 , H01L29/7843
摘要： A method is provided for fabricating a field effect transistor (“FET”) having a channel region in a semiconductor-on-insulator (“SOI”) layer of an SOI substrate. Desirably, in such method, a sacrificial stressed layer is formed to overlie a first portion of an active semiconductor region but not overlie second portion of the active semiconductor region which shares a common boundary with the first portion. After forming trenches in the SOI layer, the SOI substrate is heated with the stressed layer thereon sufficiently to cause the stressed layer to relax, thereby causing the stressed layer to apply a first stress to the first portion and to apply a second stress to the second portion. For example, when the first stress is tensile, the second stress is compressive, or the first stress can be compressive when the second stress is tensile. Desirably, the stressed layer is then removed to expose the first and second portions of the active semiconductor region. Desirably, the field effect transistor (“FET”) is formed to include (i) a source region in the first portion, (ii) a drain region in the first portion, and (iii) a channel region in the second portion.
摘要翻译：提供一种用于制造在SOI衬底的绝缘体上半导体（“SOI”）层中具有沟道区的场效应晶体管（“FET”）的方法。理想地，在这种方法中，牺牲应力层形成为覆盖有源半导体区域的第一部分，但不覆盖与第一部分共用公共边界的有源半导体区域的第二部分。在SOI层中形成沟槽之后，将SOI衬底上的应力层充分加热，使得应力层松弛，从而使应力层对第一部分施加第一应力并向第二部分施加第二应力一部分。例如，当第一应力是拉伸时，第二应力是压缩的，或者当第二应力是拉伸时，第一应力可以是压缩的。理想地，应力层被去除以暴露有源半导体区域的第一和第二部分。期望地，场效应晶体管（“FET”）形成为包括（i）第一部分中的源极区域，（ii）第一部分中的漏极区域，以及（iii）第二部分中的沟道区域。

5. 发明授权

US07888197B2 Method of forming stressed SOI FET having doped glass box layer using sacrificial stressed layer 有权
标题翻译：使用牺牲应力层形成具有掺杂玻璃盒层的应力SOI FET的方法
公开(公告)号：US07888197B2
公开(公告)日：2011-02-15
申请号：US11622056
申请日：2007-01-11
申请人： Dureseti Chidambarrao , William K. Henson , Yaocheng Liu
发明人： Dureseti Chidambarrao , William K. Henson , Yaocheng Liu
IPC分类号： H01L21/8238
CPC分类号： H01L29/78696 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L27/1203 , H01L29/045 , H01L29/7849
摘要： A method is provided for fabricating a semiconductor-on-insulator (“SOI”) substrate. In such method an SOI substrate is formed to include (i) an SOI layer of monocrystalline silicon separated from (ii) a bulk semiconductor layer by (iii) a buried oxide (“BOX”) layer including a layer of doped silicate glass. A sacrificial stressed layer is deposited onto the SOI substrate to overlie the SOI layer. Trenches are then etched through the sacrificial stressed layer and into the SOI layer. The SOI substrate is heated with the sacrificial stressed layer sufficiently to cause the glass layer to soften and the sacrificial stressed layer to relax, to thereby apply a stress to the SOI layer to form a stressed SOI layer. The trenches in the stressed SOI layer are then filled with a dielectric material to form trench isolation regions contacting peripheral edges of the stressed SOI layer, the trench isolation regions extending downwardly from a major surface of the stressed SOI layer towards the BOX layer. The sacrificial stressed layer is then removed to expose the stressed SOI layer. Field effect transistors can then be formed in the stressed SOI layer.
摘要翻译：提供了一种用于制造绝缘体上半导体（“SOI”）衬底的方法。在这种方法中，形成SOI衬底，其包括（i）通过（iii）包含掺杂硅酸盐玻璃层的掩埋氧化物（“BOX”）层从（ii）体半导体层分离的单晶硅的SOI层。牺牲应力层沉积在SOI衬底上以覆盖SOI层。然后将沟槽蚀刻穿过牺牲应力层并进入SOI层。用牺牲应力层将SOI衬底充分加热，使玻璃层软化，牺牲应力层松弛，从而向SOI层施加应力以形成受应力的SOI层。然后用电介质材料填充受应力的SOI层中的沟槽，以形成接触应力SOI层的外围边缘的沟槽隔离区，沟槽隔离区域从受应力的SOI层的主表面向BOX层向下延伸。然后去除牺牲应力层以暴露受应力的SOI层。然后可以在受应力的SOI层中形成场效应晶体管。

6. 发明申请

US20080054357A1 SEMICONDUCTOR STRUCTURE WITH ENHANCED PERFORMANCE USING A SIMPLIFIED DUAL STRESS LINER CONFIGURATION 失效
标题翻译：使用简化的双应力衬里配置提高性能的半导体结构
公开(公告)号：US20080054357A1
公开(公告)日：2008-03-06
申请号：US11468958
申请日：2006-08-31
申请人： Dureseti Chidambarrao , Yaocheng Liu , William K. Henson
发明人： Dureseti Chidambarrao , Yaocheng Liu , William K. Henson
IPC分类号： H01L27/12
CPC分类号： H01L21/28097 , H01L21/7624 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L27/1203 , H01L29/045 , H01L29/4908 , H01L29/4975 , H01L29/665 , H01L29/66545 , H01L29/7843
摘要： A semiconductor structure including an nFET having a fully silicided gate electrode wherein a new dual stress liner configuration is used to enhance the stress in the channel region that lies beneath the gate electrode is provided. The new dual stress liner configuration includes a first stress liner that has an upper surface that is substantially planar with an upper surface of a fully silicided gate electrode of the nFET. In accordance with the present invention, the first stress liner is not present atop the nFET including the fully silicided gate electrode. Instead, the first stress liner of the present invention partially wraps around, i.e., surrounds the sides of, the nFET with the fully silicided gate electrode. A second stress liner having an opposite polarity as that of the first stress liner (i.e., of an opposite stress type) is located on the upper surface of the first stress liner as well as atop the nFET that contains the fully silicided FET. In accordance with the present invention, the first stress liner is a tensile stress liner and the second stress liner is a compressive stress liner.
摘要翻译：提供了包括具有完全硅化栅电极的nFET的半导体结构，其中使用新的双应力衬垫配置来增强位于栅电极下方的沟道区中的应力。新的双应力衬垫构造包括第一应力衬垫，其具有与nFET的完全硅化栅电极的上表面基本上平面的上表面。根据本发明，第一应力衬垫不存在于包括全硅化物栅电极的nFET顶部。相反，本发明的第一应力衬垫部分地包裹着nFET的侧面，即用完全硅化的栅电极包围nFET。具有与第一应力衬垫相反极性（即相反应力类型）的第二应力衬垫位于第一应力衬垫的上表面上以及位于包含完全硅化FET的nFET顶上。根据本发明，第一应力衬垫是拉伸应力衬垫，第二应力衬垫是压应力衬垫。

7. 发明授权

US07632724B2 Stressed SOI FET having tensile and compressive device regions 失效
标题翻译：具有拉伸和压缩装置区域的受压SOI FET
公开(公告)号：US07632724B2
公开(公告)日：2009-12-15
申请号：US11673716
申请日：2007-02-12
申请人： Dureseti Chidambarrao , William K. Henson , Yaocheng Liu
发明人： Dureseti Chidambarrao , William K. Henson , Yaocheng Liu
IPC分类号： H01L21/00
CPC分类号： H01L29/78603 , H01L21/84 , H01L27/1203 , H01L29/7843
摘要： A method is provided for fabricating a field effect transistor (“FET”) having a channel region in a semiconductor-on-insulator (“SOI”) layer of an SOI substrate. Desirably, in such method, a sacrificial stressed layer is formed to overlie a first portion of an active semiconductor region but not overlie second portion of the active semiconductor region which shares a common boundary with the first portion. After forming trenches in the SOI layer, the SOI substrate is heated with the stressed layer thereon sufficiently to cause the stressed layer to relax, thereby causing the stressed layer to apply a first stress to the first portion and to apply a second stress to the second portion. For example, when the first stress is tensile, the second stress is compressive, or the first stress can be compressive when the second stress is tensile. Desirably, the stressed layer is then removed to expose the first and second portions of the active semiconductor region. Desirably, the field effect transistor (“FET”) is formed to include (i) a source region in the first portion, (ii) a drain region in the first portion, and (iii) a channel region in the second portion.
摘要翻译：提供一种用于制造在SOI衬底的绝缘体上半导体（“SOI”）层中具有沟道区的场效应晶体管（“FET”）的方法。理想地，在这种方法中，牺牲应力层形成为覆盖有源半导体区域的第一部分，但不覆盖与第一部分共用共同边界的有源半导体区域的第二部分。在SOI层中形成沟槽之后，将SOI衬底上的应力层充分加热，使得应力层松弛，从而使应力层对第一部分施加第一应力并向第二部分施加第二应力一部分。例如，当第一应力是拉伸时，第二应力是压缩的，或者当第二应力是拉伸时，第一应力可以是压缩的。理想地，应力层被去除以暴露有源半导体区域的第一和第二部分。期望地，场效应晶体管（“FET”）形成为包括（i）第一部分中的源极区域，（ii）第一部分中的漏极区域，以及（iii）第二部分中的沟道区域。

8. 发明授权

US07709910B2 Semiconductor structure for low parasitic gate capacitance 有权
标题翻译：用于低寄生栅极电容的半导体结构
公开(公告)号：US07709910B2
公开(公告)日：2010-05-04
申请号：US11738666
申请日：2007-04-23
申请人： William K. Henson , Paul Chung-Muh Chang , Dureseti Chidambarrao , Ricardo A. Donaton , Yaocheng Liu , Shreesh Narasimha , Amanda L. Tessier
发明人： William K. Henson , Paul Chung-Muh Chang , Dureseti Chidambarrao , Ricardo A. Donaton , Yaocheng Liu , Shreesh Narasimha , Amanda L. Tessier
IPC分类号： H01L29/78
CPC分类号： H01L21/823807 , H01L21/28097 , H01L21/76814 , H01L21/7682 , H01L21/76832 , H01L21/76844 , H01L21/823864 , H01L29/4975 , H01L29/517 , H01L29/66545 , H01L29/7843
摘要： A semiconductor structure provides lower parasitic capacitance between the gate electrode and contact vias while providing substantially the same level of stress applied by a nitride liner as conventional MOSFETs by reducing the height of the gate electrode and maintaining substantially the same height for the gate spacer. The nitride liner contacts only the outer sidewalls of the gate spacer, while not contacting inner sidewalls, or only a small area of the inner sidewalls of the gate spacer, therefore applying substantially the same level of stress to the channel of the MOSFET as conventional MOSFETs. The volume surrounded by the gate spacer and located above the gate electrode is either filled with a low-k dielectric material or occupied by a cavity having a dielectric constant of substantially 1.0. The reduced height of the gate electrode and the low-k dielectric gate filler or the cavity reduces the parasitic capacitance.
摘要翻译：半导体结构在栅电极和接触通孔之间提供较低的寄生电容，同时通过降低栅极电极的高度并保持与栅极间隔件基本上相同的高度，提供与常规MOSFET相同的氮化物衬垫施加的基本相同的应力水平。氮化物衬垫仅接触栅极间隔物的外侧壁，而不接触内侧壁，或者仅接触栅极隔离物的内侧壁的小面积，因此与常规MOSFET相比施加与MOSFET的通道基本相同的应力水平。由栅极间隔物围绕并位于栅极电极上方的体积填充有低k电介质材料或由具有基本上1.0的介电常数的空腔占据。栅电极和低k电介质栅极填充物或空腔的降低的高度减小了寄生电容。

9. 发明申请

US20080237709A1 AFTER GATE FABRICATION OF FIELD EFFECT TRANSISTOR HAVING TENSILE AND COMPRESSIVE REGIONS 失效
标题翻译：在具有拉伸和压缩区域的场效应晶体管的栅格制造之后
公开(公告)号：US20080237709A1
公开(公告)日：2008-10-02
申请号：US11693786
申请日：2007-03-30
申请人： Dureseti Chidambarrao , William K. Henson , Yaocheng Liu
发明人： Dureseti Chidambarrao , William K. Henson , Yaocheng Liu
IPC分类号： H01L29/78 , H01L21/84
CPC分类号： H01L29/66628 , H01L21/84 , H01L29/1083 , H01L29/66772 , H01L29/7842 , H01L29/7843 , H01L29/7848 , H01L29/7849 , H01L29/78654
摘要： A field effect transistor (“FET”) is formed to include a stress in a channel region of an active semiconductor region of an SOI substrate. A gate is formed to overlie the active semiconductor region, after which a sacrificial stressed layer is formed which overlies the gate and the active semiconductor region. Then, the SOI substrate is heated to cause a flowable dielectric material in a buried dielectric layer of the SOI substrate to soften and reflow. As a result of the reflowing, the sacrificial stressed layer induces stress in a channel region of the active semiconductor region underlying the gate. A source region and a drain region are formed in the active semiconductor region, desirably after removing the sacrificial stressed layer.
摘要翻译：形成场效应晶体管（“FET”）以在SOI衬底的有源半导体区域的沟道区域中包含应力。形成栅极覆盖有源半导体区域，之后形成覆盖在栅极和有源半导体区域上的牺牲应力层。然后，加热SOI衬底，使SOI衬底的埋入介质层中的可流动介电材料软化和回流。作为回流的结果，牺牲应力层在栅极下方的有源半导体区域的沟道区域中引起应力。源极区域和漏极区域形成在有源半导体区域中，理想地在除去牺牲应力层之后。

10. 发明申请

US20080169508A1 STRESSED SOI FET HAVING DOPED GLASS BOX LAYER 有权
标题翻译：具有DOPED GLASS BOX LAYER的应力SOI FET
公开(公告)号：US20080169508A1
公开(公告)日：2008-07-17
申请号：US11622056
申请日：2007-01-11
申请人： Dureseti Chidambarrao , William K. Henson , Yaocheng Liu
发明人： Dureseti Chidambarrao , William K. Henson , Yaocheng Liu
IPC分类号： H01L27/12 , H01L21/84
CPC分类号： H01L29/78696 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L27/1203 , H01L29/045 , H01L29/7849
摘要： A method is provided for fabricating a semiconductor-on-insulator (“SOI”) substrate including (i) an SOI layer of monocrystalline silicon separated from (ii) a bulk semiconductor layer by (ii) a buried oxide (“BOX”) layer, the BOX layer including a layer of doped silicate glass. In such method, a sacrificial stressed layer is deposited to overlie the SOI layer and trenches are etched through the sacrificial stressed layer and into the SOI layer. The SOI substrate is heated with the sacrificial stressed layer sufficiently to cause the glass layer to soften, thereby causing the sacrificial stressed layer to apply stress to the SOI layer to form a stressed SOI layer. A dielectric material can then be deposited in the trenches to form isolation regions contacting peripheral edges of the stressed SOI layer, the isolation regions extending from a major surface of the stressed SOI layer towards the BOX layer. The sacrificial stressed layer can then be removed to expose the stressed SOI layer.
摘要翻译：提供了一种用于制造绝缘体上半导体（“SOI”）衬底的方法，其包括（i）通过（ii）掩埋氧化物（“BOX”）层从（ii）体半导体层分离的单晶硅的SOI层 BOX层包括一层掺杂的硅酸盐玻璃。在这种方法中，沉积牺牲应力层以覆盖SOI层，并且通过牺牲应力层蚀刻沟槽并进入SOI层。用牺牲应力层对SOI衬底进行充分加热，使玻璃层软化，从而使牺牲应力层向SOI层施加应力以形成受应力的SOI层。然后可以将电介质材料沉积在沟槽中以形成接触应力SOI层的外围边缘的隔离区域，隔离区域从受应力的SOI层的主表面延伸到BOX层。然后可以去除牺牲应力层以暴露受应力的SOI层。

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