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1. 发明申请

US20140223592A1 PIG MYOSTATIN GENE LOCUS AND USES THEREOF 审中-公开
标题翻译： PIG MYOSTATIN基因位点及其用途
公开(公告)号：US20140223592A1
公开(公告)日：2014-08-07
申请号：US14128995
申请日：2011-07-06
申请人： Yanzhen Bi , Xinmin Zheng , Xianfeng Qiao , Ximei Liu , Liping Zhang , Wenjun Hua , Li Li , Hongwei Xiao , Jingrong Zhou , Qingxin Wei
发明人： Yanzhen Bi , Xinmin Zheng , Xianfeng Qiao , Ximei Liu , Liping Zhang , Wenjun Hua , Li Li , Hongwei Xiao , Jingrong Zhou , Qingxin Wei
IPC分类号： C12N15/85 , A01K67/027
CPC分类号： A01K67/0275 , C07K14/475 , C12N15/8509
摘要： A pig myostatin gene locus and uses thereof are provided. Also provided includes an expression cassette comprising a promoter, a foreign gene and a following terminator; the promoter is a DNA molecule as set forth in any of 1)-4): 1) nucleotides at positions 2642-3778 starting from the 5′ end of SEQ ID NO. 1 in the sequence listing; 2) nucleotides as set forth in SEQ ID NO. 1 in the sequence listing; 3) a DNA molecule, hybridizing and having the same function with the DNA sequence as defined in 1) or 2) under stringent condition. Experiments show that the pig myostatin gene locus provides a valuable gene source for gene targeting, as well as introducing and expressing a foreign gene at this site.
摘要翻译：提供猪肌生成抑制素基因位点及其用途。还提供了包含启动子，外源基因和以下终止子的表达盒; 启动子是1）-4）中任一项所示的DNA分子：1）从SEQ ID NO：5的末端开始的位置2642-3778处的核苷酸。 1序列表; 2）如SEQ ID NO： 1序列表; 3）DNA分子，在严格条件下与1）或2）中定义的DNA序列杂交并具有相同的功能。实验表明，猪肌生成抑制素基因位点为基因靶向提供了有价值的基因来源，并在该位点引入和表达外源基因。

2. 发明授权

US08687417B2 Electronic device and method of biasing 有权
标题翻译：电子设备和偏置方法
公开(公告)号：US08687417B2
公开(公告)日：2014-04-01
申请号：US11867743
申请日：2007-10-05
申请人： Ruigang Li , Jingrong Zhou , David Donggang Wu , Zhonghai Shi , James F. Buller , Akif Sultan , Fred Hause , Donna Michael
发明人： Ruigang Li , Jingrong Zhou , David Donggang Wu , Zhonghai Shi , James F. Buller , Mark W. Michael , Akif Sultan , Fred Hause
IPC分类号： G11C11/34 , G11C16/04 , G11C16/02 , G11C16/00
CPC分类号： H01L21/84 , H01L27/1203
摘要： A first bias charge is provided to first bias region at a first level of an electronic device, the first bias region directly underlying a first transistor having a channel region at a second level that is electrically isolated from the first bias region. A voltage threshold of the first transistor is based upon the first bias charge. A second bias charge is provided to second bias region at the first level of an electronic device, the second bias region directly underlying a second transistor having a channel region at a second level that is electrically isolated from the first bias region. A voltage threshold of the second transistor is based upon the second bias charge.
摘要翻译：第一偏置电荷被提供给电子器件的第一电平处的第一偏置区域，直接位于第一晶体管下方的第一偏置区域具有与第一偏置区域电隔离的第二电平的沟道区域。第一晶体管的电压阈值基于第一偏置电荷。第二偏置电荷被提供给电子器件的第一电平处的第二偏置区域，第二偏置区域直接位于具有与第一偏置区域电隔离的第二电平的沟道区域的第二晶体管的正下方。第二晶体管的电压阈值基于第二偏置电荷。

3. 发明授权

US07727835B2 SOI device with charging protection and methods of making same 有权
标题翻译：具有充电保护的SOI器件及其制造方法
公开(公告)号：US07727835B2
公开(公告)日：2010-06-01
申请号：US12194006
申请日：2008-08-19
申请人： David D. Wu , Jingrong Zhou
发明人： David D. Wu , Jingrong Zhou
IPC分类号： H01L21/00
CPC分类号： H01L27/1203 , H01L21/84 , H01L27/0251 , H01L29/78603 , H01L29/78639
摘要： The present invention is directed to an SOI device with charging protection and methods of making same. In one illustrative embodiment, a device is formed on an SOI substrate including a bulk substrate, a buried insulation layer and an active layer. The device includes a transistor formed in an isolated portion of the active layer, the transistor including a gate electrode and a source region. The device further includes a first conductive bulk substrate contact extending through the active layer and the buried insulation layer, the first conductive bulk substrate contact being conductively coupled to the source region and the bulk substrate, and a second conductive bulk substrate contact extending through the active layer and the buried insulation layer, the second conductive bulk substrate being conductively coupled to the gate electrode and the bulk substrate.
摘要翻译：本发明涉及具有充电保护的SOI器件及其制造方法。在一个说明性实施例中，在包括体基板，掩埋绝缘层和有源层的SOI衬底上形成器件。该器件包括形成在有源层的隔离部分中的晶体管，晶体管包括栅电极和源极区。该器件还包括延伸穿过有源层和掩埋绝缘层的第一导电体衬底接触件，第一导电体衬底接触件导电耦合到源极区域和本体衬底，以及延伸穿过有源层的第二导电体衬底触点层和所述掩埋绝缘层，所述第二导电体基板导电耦合到所述栅电极和所述块体基板。

4. 发明授权

US07414289B2 SOI Device with charging protection and methods of making same 有权
标题翻译：具有充电保护的SOI器件及其制造方法
公开(公告)号：US07414289B2
公开(公告)日：2008-08-19
申请号：US11457927
申请日：2006-07-17
申请人： David D. Wu , Jingrong Zhou
发明人： David D. Wu , Jingrong Zhou
IPC分类号： H01L27/01
CPC分类号： H01L27/1203 , H01L21/84 , H01L27/0251 , H01L29/78603 , H01L29/78639
摘要： The present invention is directed to an SOI device with charging protection and methods of making the same. In one illustrative embodiment, a device is formed on an SOI substrate including a bulk substrate, a buried insulation layer and an active layer. The device includes a transistor formed in an isolated portion of the active layer, the transistor including a gate electrode and a source region. The device further includes a first conductive bulk substrate contact extending through the active layer and the buried insulation layer, the first conductive bulk substrate contact being conductively coupled to the source region and the bulk substrate, and a second conductive bulk substrate contact extending through the active layer and the buried insulation layer, the second conductive bulk substrate being conductively coupled to the gate electrode and the bulk substrate.
摘要翻译：本发明涉及具有充电保护的SOI器件及其制造方法。在一个说明性实施例中，在包括体基板，掩埋绝缘层和有源层的SOI衬底上形成器件。该器件包括形成在有源层的隔离部分中的晶体管，晶体管包括栅电极和源极区。该器件还包括延伸穿过有源层和掩埋绝缘层的第一导电体衬底接触件，第一导电体衬底接触件导电耦合到源极区域和本体衬底，以及延伸穿过有源层的第二导电体衬底触点层和所述掩埋绝缘层，所述第二导电体基板导电耦合到所述栅电极和所述块体基板。

5. 发明申请

US20070298524A1 METHODS OF QUANTIFYING VARIATIONS RESULTING FROM MANUFACTURING-INDUCED CORNER ROUNDING OF VARIOUS FEATURES, AND STRUCTURES FOR TESTING SAME 有权
标题翻译：定量生成各种特征的角膜绕组变化量化方法及其测试结构
公开(公告)号：US20070298524A1
公开(公告)日：2007-12-27
申请号：US11425913
申请日：2006-06-22
申请人： DAVID D. WU , Mark W. Michael , Akif Sultan , Jingrong Zhou
发明人： DAVID D. WU , Mark W. Michael , Akif Sultan , Jingrong Zhou
IPC分类号： H01L21/66 , G01R31/26
CPC分类号： H01L22/34 , G03F7/70658 , H01L22/12
摘要： The present invention is directed to methods of quantifying variations resulting from manufacturing-induced corner rounding of various features, and structures for testing same. In one illustrative embodiment, the method includes forming a plurality of test structures on a semiconducting substrate, each of the test structures having at least one physical dimension that varies relative to the other of the plurality of test structures, at least some of the test structures exhibiting at least some degree of manufacturing-induced corner rounding, forming at least one reference test structure, performing at least one electrical test on the plurality of test structures and on the reference test structure to thereby produce electrical test results, and analyzing the test results to determine an impact of the manufacturing-induced corner rounding on the performance of the plurality of test structures.
摘要翻译：本发明涉及量化由各种特征的制造引起的角舍入引起的变化的方法和用于测试相同结构的方法。在一个说明性实施例中，该方法包括在半导体衬底上形成多个测试结构，每个测试结构具有相对于多个测试结构中的另一个变化的至少一个物理尺寸，至少一些测试结构表现出至少一定程度的制造引起的角落四舍五入，形成至少一个参考测试结构，对多个测试结构和参考测试结构进行至少一次电测试，从而产生电测试结果，并分析测试结果以确定制造性角落四舍五入对多个测试结构的性能的影响。

6. 发明授权

US08050077B2 Semiconductor device with transistor-based fuses and related programming method 有权
标题翻译：具有晶体管保险丝和相关编程方法的半导体器件
公开(公告)号：US08050077B2
公开(公告)日：2011-11-01
申请号：US12392645
申请日：2009-02-25
申请人： Ruigang Li , David Donggang Wu , James F. Buller , Jingrong Zhou
发明人： Ruigang Li , David Donggang Wu , James F. Buller , Jingrong Zhou
IPC分类号： G11C17/18 , G11C17/16 , G11C17/14 , G11C17/08 , G11C17/00
CPC分类号： H01L27/112 , G11C17/16 , G11C17/18 , H01H9/50 , H01H35/24 , H01H77/101 , H01L27/11206
摘要： A transistor-based fuse structure is realized in a semiconductor device having a semiconductor substrate, transistor devices formed on the semiconductor substrate, and the transistor-based fuse structure formed on the semiconductor substrate. The transistor-based fuse structure includes a plurality of transistor-based fuses, and the method begins by selecting, from the plurality of transistor-based fuses, a first target fuse to be programmed for operation in a low-resistance/high-current state, the first target fuse having a first source, a first gate, a first drain, and a first gate insulator layer between the first gate and the semiconductor substrate. The method applies a first set of program voltages to the first source, the first gate, and the first drain to cause breakdown of the first gate insulator layer such that current can flow from the first source to the first gate through the first gate insulator layer, and from the first gate to the first drain through the first gate insulator layer.
摘要翻译：在具有半导体衬底的半导体器件，形成在半导体衬底上的晶体管器件和形成在半导体衬底上的基于晶体管的熔丝结构的半导体器件中实现基于晶体管的熔丝结构。基于晶体管的熔丝结构包括多个基于晶体管的熔丝，并且该方法开始于从多个基于晶体管的熔丝中选择待编程的第一目标熔丝，以在低电阻/高电流状态下工作所述第一靶保险丝在所述第一栅极和所述半导体衬底之间具有第一源极，第一栅极，第一漏极和第一栅极绝缘体层。该方法将第一组编程电压施加到第一源极，第一栅极和第一漏极，以引起第一栅极绝缘体层的击穿，使得电流可以通过第一栅极绝缘体层从第一源极流到第一栅极，并且通过第一栅极绝缘体层从第一栅极到第一漏极。

7. 发明授权

US07598161B2 Method of forming transistor devices with different threshold voltages using halo implant shadowing 有权
标题翻译：使用光晕植入物阴影形成具有不同阈值电压的晶体管器件的方法
公开(公告)号：US07598161B2
公开(公告)日：2009-10-06
申请号：US11861534
申请日：2007-09-26
申请人： Jingrong Zhou , Mark Michael , Donna Michael, legal representative , David Wu , James F. Buller , Akif Sultan
发明人： Jingrong Zhou , Mark Michael , David Wu , James F. Buller , Akif Sultan
IPC分类号： H01L21/425
CPC分类号： H01L21/26513 , H01L21/26586 , H01L21/823807 , H01L29/1083
摘要： The halo implant technique described herein employs a halo implant mask that creates a halo implant shadowing effect during halo dopant bombardment. A first transistor device structure and a second transistor device structure are formed on a wafer such that they are orthogonally oriented to each other. A common halo implant mask is created with features that prevent halo implantation of the diffusion region of the second transistor device structure during halo implantation of the diffusion region of the first transistor device structure, and with features that prevent halo implantation of the diffusion region of the first transistor device structure during halo implantation of the diffusion region of the second transistor device structure. The orthogonal orientation of the transistor device structures and the pattern of the halo implant mask obviates the need to create multiple implant masks to achieve different threshold voltages for the transistor device structures.
摘要翻译：本文描述的光晕植入技术采用在光晕掺杂剂轰击期间产生晕轮植入物阴影效应的光晕注入掩模。第一晶体管器件结构和第二晶体管器件结构形成在晶片上，使得它们彼此正交地取向。创建了常见的光晕注入掩模，其特征在于，在第一晶体管器件结构的扩散区域的晕圈注入期间防止第二晶体管器件结构的扩散区域的光晕注入，并且具有防止第在第二晶体管器件结构的扩散区的晕圈注入期间的第一晶体管器件结构。晶体管器件结构的正交取向和光晕注入掩模的图案消除了创建多个注入掩模以实现晶体管器件结构的不同阈值电压的需要。

8. 发明申请

US20090090969A1 ELECTRONIC DEVICE AND METHOD OF BIASING 有权
标题翻译：电子设备和偏置方法
公开(公告)号：US20090090969A1
公开(公告)日：2009-04-09
申请号：US11867743
申请日：2007-10-05
申请人： Ruigang Li , Jingrong Zhou , David Donggang Wu , Zhonghai Shi , James F. Buller , Mark W. Michael , Donna Michael , Akif Sultan , Fred Hause
发明人： Ruigang Li , Jingrong Zhou , David Donggang Wu , Zhonghai Shi , James F. Buller , Mark W. Michael , Donna Michael , Akif Sultan , Fred Hause
IPC分类号： H01L27/12 , H01L21/84
CPC分类号： H01L21/84 , H01L27/1203
摘要： A first bias charge is provided to first bias region at a first level of an electronic device, the first bias region directly underlying a first transistor having a channel region at a second level that is electrically isolated from the first bias region. A voltage threshold of the first transistor is based upon the first bias charge. A second bias charge is provided to second bias region at the first level of an electronic device, the second bias region directly underlying a second transistor having a channel region at a second level that is electrically isolated from the first bias region. A voltage threshold of the second transistor is based upon the second bias charge.
摘要翻译：第一偏置电荷被提供给电子器件的第一电平处的第一偏置区域，直接位于第一晶体管下方的第一偏置区域具有与第一偏置区域电隔离的第二电平的沟道区域。第一晶体管的电压阈值基于第一偏置电荷。第二偏置电荷被提供给电子器件的第一电平处的第二偏置区域，第二偏置区域直接位于具有与第一偏置区域电隔离的第二电平的沟道区域的第二晶体管的正下方。第二晶体管的电压阈值基于第二偏置电荷。

9. 发明申请

US20080012072A1 SOI DEVICE WITH CHARGING PROTECTION AND METHODS OF MAKING SAME 有权
标题翻译：具有充电保护的SOI器件及其制造方法
公开(公告)号：US20080012072A1
公开(公告)日：2008-01-17
申请号：US11457927
申请日：2006-07-17
申请人： David D. Wu , Jingrong Zhou
发明人： David D. Wu , Jingrong Zhou
IPC分类号： H01L27/12
CPC分类号： H01L27/1203 , H01L21/84 , H01L27/0251 , H01L29/78603 , H01L29/78639
摘要： The present invention is directed to an SOI device with charging protection and methods of making the same. In one illustrative embodiment, a device is formed on an SOI substrate including a bulk substrate, a buried insulation layer and an active layer. The device includes a transistor formed in an isolated portion of the active layer, the transistor including a gate electrode and a source region. The device further includes a first conductive bulk substrate contact extending through the active layer and the buried insulation layer, the first conductive bulk substrate contact being conductively coupled to the source region and the bulk substrate, and a second conductive bulk substrate contact extending through the active layer and the buried insulation layer, the second conductive bulk substrate being conductively coupled to the gate electrode and the bulk substrate.
摘要翻译：本发明涉及具有充电保护的SOI器件及其制造方法。在一个说明性实施例中，在包括体基板，掩埋绝缘层和有源层的SOI衬底上形成器件。该器件包括形成在有源层的隔离部分中的晶体管，晶体管包括栅电极和源极区。该器件还包括延伸穿过有源层和掩埋绝缘层的第一导电体衬底接触件，第一导电体衬底接触件导电耦合到源极区域和本体衬底，以及延伸穿过有源层的第二导电体衬底触点层和所述掩埋绝缘层，所述第二导电体基板导电耦合到所述栅电极和所述块体基板。

10. 发明申请

US20120007182A1 CHARGING PROTECTION DEVICE 有权
标题翻译：充电保护装置
公开(公告)号：US20120007182A1
公开(公告)日：2012-01-12
申请号：US13239865
申请日：2011-09-22
申请人： Jingrong Zhou , David Wu , James F. Buller
发明人： Jingrong Zhou , David Wu , James F. Buller
IPC分类号： H01L27/12
CPC分类号： H01L27/0255 , H01L21/84 , H01L27/1203
摘要： Shallow trench isolation silicon-on-insulator (SOI) devices are formed with improved charge protection. Embodiments include an SOI film diode and a P+ substrate junction as a charging protection device. Embodiments also include a conductive path from the SOI transistor drain, through a conductive contact, a metal line, a second conductive contact, an SOI diode, isolated from the transistor, a third conductive contact, a second conductive line, and a fourth conductive contact to a P+-doped substrate contact in the bulk silicon layer of the SOI substrate.
摘要翻译：形成具有改进的电荷保护的浅沟槽隔离绝缘体上硅（SOI）器件。实施例包括作为充电保护装置的SOI膜二极管和P +衬底结。实施例还包括从SOI晶体管漏极，通过导电触点，金属线，第二导电触点，与晶体管隔离的SOI二极管，第三导电触点，第二导线和第四导电触点的导电路径到SOI衬底的体硅层中的P +掺杂的衬底接触。

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