专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07254140B1 Method and apparatus for transceiving data in a micro-area network 有权
标题翻译：用于在微区域网络中收发数据的方法和装置
公开(公告)号：US07254140B1
公开(公告)日：2007-08-07
申请号：US10047368
申请日：2002-01-14
申请人： Shahriar Rokhsaz , Jinghui Lu , Moises E. Robinson
发明人： Shahriar Rokhsaz , Jinghui Lu , Moises E. Robinson
IPC分类号： H04J3/16
CPC分类号： H04L67/2823 , H04L12/5692 , H04L67/28 , H04L67/2895
摘要： A method and apparatus for transceiving data in a micro-area network includes processing that begins by obtaining a data unit for transmission by a first data transceiving entity of a micro area network. The processing then continues when the first data transceiving entity formats the payload data using a first transmission format convention. The first data transceiving entity also formats the overhead data using a second transmission formatting convention to produce formatted overhead data. The formatting of the overhead data and/or payload data may include encoding and/or modulating the data. The processing continues when the first data transceiving entity transmits the formatted payload data and the formatted overhead data to at least one target entity within the micro-area network. The process continues when a target entity receives the formatted payload data and the formatted overhead data. The target entity then deformats the formatted payload data using the first transmission format convention to recapture the payload data and deformats the formatted overhead data using the second transmission format convention to retrieve the overhead data. The target entity then reconstructs the data unit from the retrieved payload data and the retrieved overhead data.
摘要翻译：用于在微区域网络中收发数据的方法和装置包括通过获得数据单元开始的处理，以便由微区域网络的第一数据收发实体进行传输。然后，当第一数据收发实体使用第一传输格式约定格式化有效载荷数据时，处理继续。第一数据收发实体还使用第二传输格式化规则对开销数据进行格式化以产生格式化的开销数据。开销数据和/或有效载荷数据的格式化可以包括编码和/或调制数据。当第一数据收发实体将格式化的有效载荷数据和格式化的开销数据发送到微区域网络内的至少一个目标实体时，处理继续。当目标实体接收格式化的有效载荷数据和格式化的开销数据时，该过程继续。目标实体然后使用第一传输格式惯例对格式化的有效载荷数据进行格式化，以重新捕获有效载荷数据，并使用第二传输格式惯例对格式化的开销数据进行格式化以检索开销数据。目标实体然后从检索到的有效载荷数据和检索的开销数据中重构数据单元。

2. 发明授权

US07523215B1 Method and apparatus for configuring data transmissions within a micro-area network 有权
标题翻译：用于在微区域网络内配置数据传输的方法和装置
公开(公告)号：US07523215B1
公开(公告)日：2009-04-21
申请号：US10047195
申请日：2002-01-14
申请人： Moises E. Robinson , Shahriar Rokhsaz , Jinghui Lu
发明人： Moises E. Robinson , Shahriar Rokhsaz , Jinghui Lu
IPC分类号： G06F15/16
CPC分类号： H04L69/24
摘要： A method and apparatus for a transmitting entity within a micro-area network to establish a data transmission within the network includes processing that begins by determining the identity of a target entity within the micro-area network. The processing then continues by determining transmission characteristics of at least one communication path between the transmitting entity and target entity of the micro-area network. The processing then continues by determining a transmission convention based on the transmission characteristics. The processing then continues by providing the transmission convention to the target entity.
摘要翻译：用于在微区域网内发送实体以建立网络内的数据传输的方法和装置包括通过确定微区域网内的目标实体的身份开始的处理。然后通过确定微区域网络的发送实体和目标实体之间的至少一个通信路径的传输特性来继续处理。然后通过基于传输特性确定传输约定来继续处理。然后通过向目标实体提供传输约定来继续处理。

3. 发明授权

US07058120B1 Integrated high-speed serial-to-parallel and parallel-to-serial transceiver 有权
标题翻译：集成的高速串并行和并行到串行收发器
公开(公告)号：US07058120B1
公开(公告)日：2006-06-06
申请号：US10051222
申请日：2002-01-18
申请人： Jinghui Lu , Shahriar Rokhsaz , Stephen D. Anderson , Michael A. Nix , Ahmed Younis , Michael Ren Kent , Yvette P. Lee , Firas N. Abughazaleh , Brian T. Brunn , Moises E. Robinson , Kazi S. Hossain
发明人： Jinghui Lu , Shahriar Rokhsaz , Stephen D. Anderson , Michael A. Nix , Ahmed Younis , Michael Ren Kent , Yvette P. Lee , Firas N. Abughazaleh , Brian T. Brunn , Moises E. Robinson , Kazi S. Hossain
IPC分类号： H03K11/00 , H04L25/60 , H04L25/64
CPC分类号： H03L7/093 , H03K5/1565 , H03M9/00 , H04L7/0004 , H04L7/033 , H04W4/18
摘要： A transceiver includes a receiver section and a transmitter section. The receiver section includes a clocking circuit, a serial-to-parallel module, and compensation. The transmitter section includes a clocking circuit, parallel-to-serial module, and compensation. The compensation within the receiver section and transmitter section compensates for integrated circuit (IC) processing limits and/or integrated circuit (IC) fabrication limits within the clocking circuits, serial-to-parallel module, and parallel-to-serial module that would otherwise limit the speed at which the transceiver could transport data.
摘要翻译：收发机包括接收机部分和发射机部分。接收器部分包括时钟电路，串行到并行模块和补偿。发射机部分包括时钟电路，并行到串行模块和补偿。接收器部分和发射器部分内的补偿补偿了时钟控制电路，串行到并行模块和并行到串行模块的集成电路（IC）处理限制和/或集成电路（IC）制造限制，否则限制收发器可以传输数据的速度。

4. 发明授权

US07315220B1 Voltage controlled oscillator 有权
标题翻译：压控振荡器
公开(公告)号：US07315220B1
公开(公告)日：2008-01-01
申请号：US11340998
申请日：2006-01-27
申请人： Moises E. Robinson , Shahriar Rokhsaz , Marwan M. Hassoun , Earl E. Swartzlander, Jr.
发明人： Moises E. Robinson , Shahriar Rokhsaz , Marwan M. Hassoun , Earl E. Swartzlander, Jr.
IPC分类号： H03B5/20
CPC分类号： H03L7/0995 , H03B5/1212 , H03B5/1221 , H03B5/1228 , H03K3/354 , H03K3/356113 , H03L2207/06
摘要： A voltage controlled oscillator (VCO) having a single stage ring-oscillator having both coarse and fine control of the frequency of oscillation is described. In an embodiment the VCO may include a first n-channel latch having a first output and a second output; a first P-channel transistor coupled between a voltage supply and a first VCO output, where a gate of the first P-channel transistor is coupled to the first output of the first n-channel latch; a first programmable resistor circuit coupled between the first VCO output and the first output of the first n-channel latch; and a second n-channel latch coupled to the first VCO output.
摘要翻译：描述具有振荡频率的粗略和精细控制的具有单级环形振荡器的压控振荡器（VCO）。在一个实施例中，VCO可以包括具有第一输出和第二输出的第一n沟道锁存器; 耦合在电压源和第一VCO输出端之间的第一P沟道晶体管，其中第一P沟道晶体管的栅极耦合到第一n沟道锁存器的第一输出; 耦合在所述第一VCO输出和所述第一n沟道锁存器的所述第一输出端之间的第一可编程电阻器电路; 以及耦合到第一VCO输出的第二n沟道锁存器。

5. 发明授权

US07224760B1 High-speed wide bandwidth data detection circuit 有权
标题翻译：高速宽带数据检测电路
公开(公告)号：US07224760B1
公开(公告)日：2007-05-29
申请号：US10421512
申请日：2003-04-22
申请人： Shahriar Rokhsaz , Moises E. Robinson , Ahmed Younis , Brian T. Brunn
发明人： Shahriar Rokhsaz , Moises E. Robinson , Ahmed Younis , Brian T. Brunn
IPC分类号： H03D3/24
CPC分类号： H04L7/0331 , H03D13/003 , H03L7/087 , H03L7/0896 , H03L7/091 , H03L7/10
摘要： A high-speed, wide bandwidth data detection circuit includes a phase detection module, a data detection module, a loop filter, and a voltage controlled oscillator. The phase detection module is operably coupled to produce a controlled current based on a current mode mathematical manipulation of differences between an incoming data stream and a recovered clock. The phase detection module performs the current mode mathematical manipulations and produces the controlled current in the current domain. The data detection module is operably coupled to produce the detected data based on the incoming data stream and the recovered clock. The loop filter is operably coupled to convert the controlled current into a controlled voltage. The voltage controlled oscillator is operably coupled to convert the control voltage into the recovered clock.
摘要翻译：高速，宽带宽数据检测电路包括相位检测模块，数据检测模块，环路滤波器和压控振荡器。相位检测模块可操作地耦合以基于对输入数据流和恢复的时钟之间的差异的当前模式数学操作产生受控电流。相位检测模块执行当前模式的数学操作并产生当前域中的受控电流。数据检测模块可操作地耦合以基于输入数据流和恢复的时钟产生检测到的数据。环路滤波器可操作地耦合以将受控电流转换成受控电压。压控振荡器可操作地耦合以将控制电压转换成恢复的时钟。

6. 发明授权

US06624668B1 Digitally programmable phase-lock loop for high-speed data communications 有权
公开(公告)号：US06624668B1
公开(公告)日：2003-09-23
申请号：US10005736
申请日：2001-11-06
申请人： Moises E. Robinson , Michael J. Gaboury , Bernard L. Grung
发明人： Moises E. Robinson , Michael J. Gaboury , Bernard L. Grung
IPC分类号： H02M1100
CPC分类号： H03L7/18 , H03L7/087 , H03L7/0898 , H03L7/0995 , H03L2207/04 , H04L7/0008 , H04L7/02
摘要： Electronic devices are typically coupled together to operate as systems that require the communication of data between two or more devices. Many of these devices includes a communications circuit, such as receiver, transmitter, or transceiver for this purpose. A typical component in these communication circuits is the phase-lock loop, a circuit that in receiver circuits determines the timing of pulses in a received data signal and in transmitter circuits clocks the data out at a predetermined rate. One problem with phase-lock loops and thus the receiver and transmitter circuits that incorporate them is that they are generally tuned, or tailored, to operate at a certain frequency. This means that one cannot generally use a receiver or transmitter circuit having phase-lock loops tuned for one frequency to communicate at another frequency. The inability to communicate at other frequencies limits the usefulness of not only the receiver and transmitter circuits but also their electronic devices. Accordingly, the present inventors devised a digitally programmable phase-lock loop which operates at a frequency selected from a set of two of more frequencies. One such phase-lock loop includes a charge pump, a loop filter, and a voltage-controlled oscillator, all of which are programmable to control the operating frequency of the phase-lock loop and thus devices, such as receivers, transmitters, and transceivers incorporating it. Moreover, the programmability of these three components enables the exemplary embodiment to maintains a constant damping factor and a constant ratio of input frequency to loop bandwidth for each frequency setting, thereby promoting loop stability and rapid settling at each selected frequency.

7. 发明授权

US06501339B1 Ring oscillators with improved signal-path matching for high-speed data communications 有权
标题翻译：环形振荡器具有改进的信号路径匹配，用于高速数据通信
公开(公告)号：US06501339B1
公开(公告)日：2002-12-31
申请号：US09927146
申请日：2001-08-10
申请人： Ahmed Younis , Moises E. Robinson , Michael A. Nix , Brian T. Brunn
发明人： Ahmed Younis , Moises E. Robinson , Michael A. Nix , Brian T. Brunn
IPC分类号： H03B524
CPC分类号： H03L7/0995 , H03K3/0315 , H03L7/087 , H03L7/0891 , H03L7/18
摘要： Electronic devices are typically coupled together to operate as systems that require the communication of data from one device to another. Many such devices include a ring oscillator, a circuit that generates one or more oscillating signals using a series of interconnected delay circuits. One problem with conventional ring oscillators concerns differences in the signal paths between the delay circuits. Accordingly, the present inventors devised several oscillators having unique layouts, which reduce differences in the signal paths between delay circuits. One exemplary oscillator includes a sequence of delay circuits having input-output connections between at least two pairs of non-adjacent delay circuits. Another exemplary oscillator provides two groups of delay circuits with a bus between the two groups, intercoupling the circuits. And, another exemplary oscillator arranges three or more delay circuits to form a closed loop. Applications for these oscillators include not only receivers, transmitters, and transceivers, but also programmable integrated circuits, electronic devices, and systems.
摘要翻译：电子设备通常耦合在一起以作为需要从一个设备到另一个设备的数据通信的系统进行操作。许多这样的设备包括环形振荡器，使用一系列互连的延迟电路产生一个或多个振荡信号的电路。常规环形振荡器的一个问题涉及延迟电路之间的信号路径的差异。因此，本发明人设计了具有独特布局的几个振荡器，其减小延迟电路之间的信号路径的差异。一个示例性振荡器包括在至少两对非相邻延迟电路之间具有输入 - 输出连接的延迟电路序列。另一个示例性振荡器提供两组延迟电路，其中两组之间的总线相互耦合。并且，另一示例性振荡器布置三个或更多个延迟电路以形成闭环。这些振荡器的应用不仅包括接收器，发射器和收发器，还包括可编程集成电路，电子设备和系统。

8. 发明授权

US06809676B1 Method and system for VCO-based analog-to-digital conversion (ADC) 有权
标题翻译：基于VCO的模数转换（ADC）的方法和系统
公开(公告)号：US06809676B1
公开(公告)日：2004-10-26
申请号：US10224977
申请日：2002-08-20
申请人： Ahmed Younis , Marwan M. Hassoun , Moises E. Robinson
发明人： Ahmed Younis , Marwan M. Hassoun , Moises E. Robinson
IPC分类号： H03M160
CPC分类号： H03M1/60
摘要： A VCO (110) can be configured to convert an analog input signal (105) to a digital output signal (125). In accordance with the inventive arrangements, the VCO can convert the analog input signal to at least one intermediate signal (130) having a frequency dependent on the analog input signal. A frequency detector (115) can be configured to determine a frequency of at least one intermediate signal. Subsequently, a mapping circuit (120) can be configured to map the determined frequency of the at least one intermediate signal to an output value representing the digital output signal (125).
摘要翻译： VCO（110）可以被配置为将模拟输入信号（105）转换成数字输出信号（125）。根据本发明的结构，VCO可以将模拟输入信号转换成具有取决于模拟输入信号的频率的至少一个中间信号（130）。频率检测器（115）可被配置为确定至少一个中间信号的频率。随后，映射电路（120）可以被配置为将所确定的至少一个中间信号的频率映射到表示数字输出信号（125）的输出值。

9. 发明授权

US06650720B1 Phase lock loop and transconductance circuit for clock recovery 有权
标题翻译：用于时钟恢复的锁相环和跨导电路
公开(公告)号：US06650720B1
公开(公告)日：2003-11-18
申请号：US09218382
申请日：1998-12-22
申请人： Bernard L. Grung , Moises E. Robinson
发明人： Bernard L. Grung , Moises E. Robinson
IPC分类号： H03D324
CPC分类号： H03L7/085 , H03L7/087 , H03L7/093 , H03L7/14 , H04L7/033
摘要： A high speed data communication system includes a receiver to recover data and clock signals from communicated data. The receiver circuit has a dual phase lock loop (PLL) circuit. A fine loop of the PLL includes a phase detector providing a differential analog voltage output. Transconductance circuitry converts the differential analog voltage output to a low current analog output. The transconductance circuitry has a high impedance output, a small transconductance value and can provide variable gain control. A coarse loop of the PLL allows for frequency acquisition of an internal oscillator.
摘要翻译：高速数据通信系统包括从通信数据恢复数据和时钟信号的接收机。接收器电路具有双锁相环（PLL）电路。 PLL的精细环路包括提供差分模拟电压输出的相位检测器。跨导电路将差分模拟电压输出转换为低电流模拟输出。跨导电路具有高阻抗输出，小跨导值，并可提供可变增益控制。 PLL的粗略回路允许对内部振荡器进行频率采集。

10. 发明授权

US06356160B1 Phase lock loop and automatic gain control circuitry for clock recovery 有权
标题翻译：锁相环和自动增益控制电路，用于时钟恢复
公开(公告)号：US06356160B1
公开(公告)日：2002-03-12
申请号：US09347256
申请日：1999-07-02
申请人： Moises E. Robinson , Bernard L. Grung , Yiqin Chen
发明人： Moises E. Robinson , Bernard L. Grung , Yiqin Chen
IPC分类号： H03L707
CPC分类号： H03L7/093 , H03L7/085 , H03L7/087 , H03L7/14 , H04L7/033
摘要： A high speed data communication system includes a receiver to recover data and clock signals from communicated data. The receiver circuit has a dual phase lock loop (PLL) circuit. A fine loop of the PLL includes a phase detector providing a differential analog voltage output. Transconductance circuitry converts the differential analog voltage output to a low current analog output. The transconductance circuitry has a variable gain which is controlled by an automatic gain adjust circuit. A coarse loop of the PLL allows for fast frequency acquisition of an internal oscillator.
摘要翻译：高速数据通信系统包括从通信数据恢复数据和时钟信号的接收机。接收器电路具有双锁相环（PLL）电路。 PLL的精细环路包括提供差分模拟电压输出的相位检测器。跨导电路将差分模拟电压输出转换为低电流模拟输出。跨导电路具有由自动增益调节电路控制的可变增益。 PLL的粗略回路允许快速采集内部振荡器。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式