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1. 发明授权

US07094669B2 Structure and method of liner air gap formation 有权
公开(公告)号：US07094669B2
公开(公告)日：2006-08-22
申请号：US10910499
申请日：2004-08-03
申请人： Xiaomei Bu , Alex See , Tae Jong Lee , Fan Zhang , Yeon Kheng Lim , Liang Choo Hsia
发明人： Xiaomei Bu , Alex See , Tae Jong Lee , Fan Zhang , Yeon Kheng Lim , Liang Choo Hsia
IPC分类号： H01L21/46 , H01L21/78 , H01L21/301 , H01L21/76 , H01L21/4763
CPC分类号： H01L21/7682 , H01L21/76807 , H01L21/76831 , H01L23/5222 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A structure and method of a semiconductor device with liner air gaps next to interconnects and dielectric layers. A dielectric layer is formed over a lower dielectric layer and a lower interconnect over a substrate. We form an interconnect opening in the dielectric layer. The opening has sidewalls of the dielectric layer. A sacrificial liner is formed over the sidewalls of the interconnect opening. An upper interconnect is formed that fills the opening. We remove the sacrificial liner/spacers to form (air) liner gaps.

2. 发明申请

US20070293039A1 Combined copper plating method to improve gap fill 有权
标题翻译：组合镀铜方法提高间隙填充
公开(公告)号：US20070293039A1
公开(公告)日：2007-12-20
申请号：US11454397
申请日：2006-06-16
申请人： Xiaomei Bu , Alex See , Fan Zhang , Jane Hui , Tae Jong Lee , Liang Choo Hsia
发明人： Xiaomei Bu , Alex See , Fan Zhang , Jane Hui , Tae Jong Lee , Liang Choo Hsia
IPC分类号： H01L21/4763 , H01L21/44
CPC分类号： H01L21/288 , H01L21/2885 , H01L21/76873 , H01L21/76877
摘要： A method of filling gaps in dielectric layers is disclosed. A wafer is provided having a dielectric layer containing gaps to be filled with copper, some of the gaps, denoted deeper gaps, having aspect ratios so large that filling these gaps with copper using ECP could result in pinhole like voids. A blanket conformal metal barrier layer is formed and the wafer is then submerged in a solution to electroless plate a blanket conformal copper seed layer. A partial filling of deeper gaps with copper reduces the effective aspect ratios of the deeper gaps to the extent that ECP could be used to complete the copper filling of the gaps without forming pinhole like voids. ECP is then used to complete the copper filling of the gaps. The wafer is annealed and CMP performed to planarize the surface, giving rise to a structure in which the gaps are filled with copper and are separated by the dielectric layer.
摘要翻译：公开了一种在电介质层中填充间隙的方法。提供具有包含要填充铜的间隙的电介质层的晶片，其中一些间隙表示为更深的间隙，其纵横比大到使用ECP填充这些间隙的铜可导致针孔状空隙。形成覆盖的共形金属阻挡层，然后将晶片浸没在无电镀平板上的覆盖层保形铜种子层的溶液中。用铜部分填充更深的间隙可以减少较深间隙的有效纵横比，使得ECP可以用于完成间隙的铜填充而不形成针孔如空隙的程度。然后使用ECP来完成间隙的铜填充。对晶片进行退火并进行CMP以平坦化表面，产生其中间隙被铜填充并由介电层分离的结构。

3. 发明授权

US07989338B2 Grain boundary blocking for stress migration and electromigration improvement in CU interconnects 有权
标题翻译：用于CU互连中的应力迁移和电迁移改进的谷物边界阻塞
公开(公告)号：US07989338B2
公开(公告)日：2011-08-02
申请号：US11153747
申请日：2005-06-15
申请人： Fan Zhang , Kho Liep Chok , Alex See , Cheng-Cheh Tan , Xiaomei Bu , Tae Jong Lee , Liang Choo Hsia
发明人： Fan Zhang , Kho Liep Chok , Alex See , Cheng-Cheh Tan , Xiaomei Bu , Tae Jong Lee , Liang Choo Hsia
IPC分类号： H01L21/4763
CPC分类号： H01L21/76859 , H01L21/76856 , H01L21/76864
摘要： Example embodiments of a structure and method for forming a copper interconnect having a doped region near a top surface. The doped region has implanted alloying elements that block grain boundaries and reduce stress and electro migration. In a first example embodiment, the barrier layer is left over the inter metal dielectric layer during the alloying element implant. The barrier layer is later removed with a planarization process. In a second example embodiment the barrier layer is removed before the alloying element implant and a hard mask blocks the alloying element from being implanted in the inter metal dielectric layer.
摘要翻译：用于形成具有在顶表面附近的掺杂区域的铜互连的结构和方法的示例实施例。掺杂区域已经植入了阻挡晶界并减少应力和电迁移的合金元素。在第一示例性实施例中，在合金元素植入期间，阻挡层留在金属间介电层上。稍后通过平坦化处理去除阻挡层。在第二示例性实施例中，在合金元素注入之前去除阻挡层，并且硬掩模阻止合金元素被注入在金属间介电层中。

4. 发明授权

US07585768B2 Combined copper plating method to improve gap fill 有权
标题翻译：组合镀铜方法提高间隙填充
公开(公告)号：US07585768B2
公开(公告)日：2009-09-08
申请号：US11454397
申请日：2006-06-16
申请人： Xiaomei Bu , Alex See , Fan Zhang , Jane Hui , Tae Jong Lee , Liang Choo Hsia
发明人： Xiaomei Bu , Alex See , Fan Zhang , Jane Hui , Tae Jong Lee , Liang Choo Hsia
IPC分类号： H01L21/44
CPC分类号： H01L21/288 , H01L21/2885 , H01L21/76873 , H01L21/76877
摘要： A method of filling gaps in dielectric layers is disclosed. A wafer is provided having a dielectric layer containing gaps to be filled with copper, some of the gaps, denoted deeper gaps, having aspect ratios so large that filling these gaps with copper using ECP could result in pinhole like voids. A blanket conformal metal barrier layer is formed and the wafer is then submerged in a solution to electroless plate a blanket conformal copper seed layer. A partial filling of deeper gaps with copper reduces the effective aspect ratios of the deeper gaps to the extent that ECP could be used to complete the copper filling of the gaps without forming pinhole like voids. ECP is then used to complete the copper filling of the gaps. The wafer is annealed and CMP performed to planarize the surface, giving rise to a structure in which the gaps are filled with copper and are separated by the dielectric layer.
摘要翻译：公开了一种在电介质层中填充间隙的方法。提供具有包含要填充铜的间隙的电介质层的晶片，其中一些间隙表示为更深的间隙，其纵横比大到使用ECP填充这些间隙的铜可导致针孔状空隙。形成覆盖的共形金属阻挡层，然后将晶片浸没在无电镀平板上的覆盖层保形铜种子层的溶液中。用铜部分填充更深的间隙可以减少较深间隙的有效纵横比，使得ECP可以用于完成间隙的铜填充而不形成针孔如空隙的程度。然后使用ECP来完成间隙的铜填充。对晶片进行退火并进行CMP以平坦化表面，产生其中间隙被铜填充并由介电层分离的结构。

5. 发明授权

US09318378B2 Slot designs in wide metal lines 有权
公开(公告)号：US09318378B2
公开(公告)日：2016-04-19
申请号：US10923123
申请日：2004-08-21
申请人： Yeow Kheng Lim , Alex See , Tae Jong Lee , David Vigar , Liang Choo Hsia , Kin Leong Pey
发明人： Yeow Kheng Lim , Alex See , Tae Jong Lee , David Vigar , Liang Choo Hsia , Kin Leong Pey
IPC分类号： H01L21/76 , H01L21/768 , H01L23/522 , H01L23/528 , H01L23/532
CPC分类号： H01L23/528 , H01L21/0276 , H01L21/288 , H01L21/3212 , H01L21/76802 , H01L21/76808 , H01L21/76816 , H01L21/7684 , H01L21/76843 , H01L21/7685 , H01L21/76879 , H01L23/5226 , H01L23/53228 , H01L23/53295 , H01L23/562 , H01L2924/0002 , H01L2924/00
摘要： A method and structure for slots in wide lines to reduce stress. An example embodiment method and structure for is an interconnect structure comprising: interconnect comprising a wide line. The wide line has a first slot. The first slot is spaced a first distance from a via plug so that the first slot relieves stress on the wide line and the via plug. The via plug can contact the wide line from above or below. Another example embodiment is a dual damascene interconnect structure comprising: an dual damascene shaped interconnect comprising a via plug, a first slot and a wide line. The wide line has the first slot. The first slot is spaced a first distance from the via plug so that the first slot relieves stress on the wide line and the via plug.

6. 发明申请

US20060286797A1 Grain boundary blocking for stress migration and electromigration improvement in CU interconnects 有权
标题翻译：用于CU互连中的应力迁移和电迁移改进的谷物边界阻塞
公开(公告)号：US20060286797A1
公开(公告)日：2006-12-21
申请号：US11153747
申请日：2005-06-15
申请人： Fan Zhang , Kho Liep , Alex See , Cheng-Cheh Tou , Xiaomei Bu , Tae Lee , Liang Hsia
发明人： Fan Zhang , Kho Liep , Alex See , Cheng-Cheh Tou , Xiaomei Bu , Tae Lee , Liang Hsia
IPC分类号： H01L21/44 , H01L21/4763
CPC分类号： H01L21/76859 , H01L21/76856 , H01L21/76864
摘要： Example embodiments of a structure and method for forming a copper interconnect having a doped region near a top surface. The doped region has implanted alloying elements that block grain boundaries and reduce stress and electro migration. In a first example embodiment, the barrier layer is left over the inter metal dielectric layer during the alloying element implant. The barrier layer is later removed with a planarization process. In a second example embodiment the barrier layer is removed before the alloying element implant and a hard mask blocks the alloying element from being implanted in the inter metal dielectric layer.
摘要翻译：用于形成具有在顶表面附近的掺杂区域的铜互连的结构和方法的示例实施例。掺杂区域已经植入了阻挡晶界并减少应力和电迁移的合金元素。在第一示例性实施例中，在合金元素植入期间，阻挡层留在金属间介电层上。稍后通过平坦化处理去除阻挡层。在第二示例性实施例中，在合金元素注入之前去除阻挡层，并且硬掩模阻止合金元素被注入在金属间介电层中。

7. 发明申请

US20060030128A1 Structure and method of liner air gap formation 有权
标题翻译：衬里气隙形成的结构和方法
公开(公告)号：US20060030128A1
公开(公告)日：2006-02-09
申请号：US10910499
申请日：2004-08-03
申请人： Xiaomei Bu , Alex See , Tae Lee , Fan Zhang , Yeon Lim , Liang Hsia
发明人： Xiaomei Bu , Alex See , Tae Lee , Fan Zhang , Yeon Lim , Liang Hsia
IPC分类号： H01L21/78
CPC分类号： H01L21/7682 , H01L21/76807 , H01L21/76831 , H01L23/5222 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A structure and method of a semiconductor device with liner air gaps next to interconnects and dielectric layers. A dielectric layer is formed over a lower dielectric layer and a lower interconnect over a substrate. We form an interconnect opening in the dielectric layer. The opening has sidewalls of the dielectric layer. A sacrificial liner is formed over the sidewalls of the interconnect opening. An upper interconnect is formed that fills the opening. We remove the sacrificial liner/spacers to form (air) liner gaps.
摘要翻译：一种半导体器件的结构和方法，衬底气隙靠近互连和电介质层。介电层形成在衬底上的下介电层和下互连之上。我们在电介质层中形成互连开口。开口具有介电层的侧壁。牺牲衬垫形成在互连开口的侧壁上。形成填充开口的上互连。我们移除牺牲衬垫/垫片以形成（空气）衬垫间隙。

8. 发明授权

US06558994B2 Dual silicon-on-insulator device wafer die 失效
公开(公告)号：US06558994B2
公开(公告)日：2003-05-06
申请号：US09841564
申请日：2001-03-01
申请人： Randall Cher Liang Cha , Yeow Kheng Lim , Alex See , Tae Jong Lee , Wang Ling Goh
发明人： Randall Cher Liang Cha , Yeow Kheng Lim , Alex See , Tae Jong Lee , Wang Ling Goh
IPC分类号： H01L2100
CPC分类号： H01L21/76264 , H01L21/76278 , H01L21/76281 , H01L21/76283 , H01L2924/0002 , Y10S438/967 , H01L2924/00
摘要： A silicon-on-insulator semiconductor device and manufacturing method therefor is provided in which a single wafer die contains a transistor over an insulator layer to form a fully depleted silicon-on-insulator device and a transistor formed in a semiconductor island over an insulator structure on the semiconductor wafer forms a partially depleted silicon-on-insulator device.

9. 发明授权

US06319767B1 Method to eliminate top metal corner shaping during bottom metal patterning for MIM capacitors via plasma ashing and hard masking technique 有权
标题翻译：用于通过等离子体灰化和硬掩蔽技术消除MIM电容器底金属图案化期间的顶部金属角成形的方法
公开(公告)号：US06319767B1
公开(公告)日：2001-11-20
申请号：US09798639
申请日：2001-03-05
申请人： Randall Cher Liang Cha , Tae Jong Lee , Alex See , Lap Chan , Yeow Kheng Lim
发明人： Randall Cher Liang Cha , Tae Jong Lee , Alex See , Lap Chan , Yeow Kheng Lim
IPC分类号： H01L218242
CPC分类号： H01L28/60 , H01L21/31122 , H01L21/31144 , H01L21/32136 , H01L21/32139
摘要： A method for fabricating a metal-insulator-metal capacitor wherein top metal corner shaping during patterning is eliminated is described. An insulating layer is provided overlying a semiconductor substrate. A composite metal stack is formed comprising a first metal layer overlying the insulating layer, a capacitor dielectric layer overlying the first metal layer, a second metal layer overlying the capacitor dielectric layer, and a hard mask layer overlying the second metal layer. A first photoresist mask is formed overlying the hard mask layer. The composite metal stack is patterned using the first photoresist mask as an etching mask whereby the patterned first metal layer forms a bottom electrode of the capacitor. A portion of the first photoresist mask is removed by plasma ashing to form a second photoresist mask narrower than the first photoresist mask. The hard mask layer is patterned using the second photoresist mask as an etching mask. The second metal layer is patterned using the hard mask layer as an etching mask whereby the second metal layer forms a top electrode of the capacitor to complete fabrication of a metal-insulator-metal capacitor.
摘要翻译：描述了一种用于制造金属 - 绝缘体 - 金属电容器的方法，其中消除了图案化期间的顶部金属角成形。绝缘层设置在半导体衬底上。形成复合金属堆叠，其包括覆盖绝缘层的第一金属层，覆盖第一金属层的电容器电介质层，覆盖电容器电介质层的第二金属层和覆盖第二金属层的硬掩模层。第一光致抗蚀剂掩模形成在硬掩模层上。使用第一光致抗蚀剂掩模将复合金属堆叠图案化为蚀刻掩模，由此图案化的第一金属层形成电容器的底部电极。通过等离子体灰化除去第一光致抗蚀剂掩模的一部分，以形成比第一光致抗蚀剂掩模窄的第二光刻胶掩模。使用第二光致抗蚀剂掩模将硬掩模层图案化为蚀刻掩模。使用硬掩模层作为蚀刻掩模对第二金属层进行构图，由此第二金属层形成电容器的顶部电极，以完成金属 - 绝缘体 - 金属电容器的制造。

10. 发明授权

US06849928B2 Dual silicon-on-insulator device wafer die 失效
标题翻译：双硅绝缘体上硅器件芯片
公开(公告)号：US06849928B2
公开(公告)日：2005-02-01
申请号：US10327309
申请日：2002-12-19
申请人： Randall Cher Liang Cha , Yeow Kheng Lim , Alex See , Tae Jong Lee , Wang Ling Goh
发明人： Randall Cher Liang Cha , Yeow Kheng Lim , Alex See , Tae Jong Lee , Wang Ling Goh
IPC分类号： H01L21/762 , H01L23/28
CPC分类号： H01L21/76264 , H01L21/76278 , H01L21/76281 , H01L21/76283 , H01L2924/0002 , Y10S438/967 , H01L2924/00
摘要： A silicon-on-insulator semiconductor device is provided in which a single wafer die contains a transistor over an insulator layer to form a fully depleted silicon-on-insulator device and a transistor formed in a semiconductor island over an insulator structure on the semiconductor wafer forms a partially depleted silicon-on-insulator device.
摘要翻译：提供一种绝缘体上半导体器件，其中单个晶片管芯在绝缘体层上包含晶体管以形成完全耗尽的绝缘体上硅器件，并且在半导体晶片上的绝缘体结构上形成半导体岛中的晶体管形成部分耗尽的绝缘体上硅器件。

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